A Multi-Channel High Precision CMOS Time-to-Digital Converter for Laserscanner Based Perception Systems

1 A Multi-Channel High Precision CMOS Time-to-Digital Converter for Laserscanner Based Perception Systems Jussi-Pekka Jansson, Vesa Koskinen, Antti Mäntyniemi and Juha Kostamovaara, Member, IEEE Abstract A multi-channel time-to-digital converter implemented with 0.35µm CMOS technology is described which uses a low frequency crystal as a reference and measures the time intervals with counter and delay line interpolation techniques. The multi-channel measurement architecture provides information on the time intervals between several timing signals. The circuit can be used for laser time-of-flight distance measurements, for example, where it can determine time intervals between a transmitted laser pulse and several reflected pulses and also pulse widths or rise times, in order to compensate for the timing walk error. The article shows how several measurement channels can be integrated into one TDC without losing the measurement performance. The circuit offers a measurement precision better than 8ps and a measurement range of up to 74µs. In terms of laser distance measurement its performance is equivalent to millimetre-level precision within a 11 km range. Index Terms time interval measurement, laser ranging, pulsed time-of-flight, lidar, RF pulse detection, time-to-digital conversion, walk error compensation, traffic perception. Manuscript received October 24, 2011. This work was financially supported by the Academy of Finland, Finnish Funding Agency for Technology and Innovation (TEKES) and by Minifaros project (part of the 7 th Framework Programme, funded by the European Commission). All funders are gratefully acknowledged. The authors are with the Electronics Laboratory, 90014 University of Oulu, Finland. (email: jussi.jansson@ee.oulu.fi; vesa.koskinen@ee.oulu.fi; antti.mantyniemi@ee.oulu.fi; juha.kostamovaara@ee.oulu.fi). Fax: +35885532700; Phone: +35885532706

2 1. INTRODUCTION A time-to-digital converter (TDC) measures the time interval between two or more timing signals and converts the result to a digital word. Accurate time domain information on signals is needed in a wide area of applications. Nuclear science [1], [2], telecommunications [3], [4], timing parameter verification of high speed circuits and components [5], [6], and analogue-to-digital converters [6], [7], for example, can make use of high precision time interval measurements. One of the most demanding applications is pulsed laser time-of-flight (TOF) distance measurement, where the transit time of a short laser pulse (typically around 3ns limited by the switching speed of highcurrent laser diode drivers) is measured as it propagates to the target and reflects back to the receiver, see Fig. 1a [9]-[11]. Both high measurement precision and a large measurement range are needed in order to measure long distances at high levels of accuracy. Emerging area for laser ranging devices is the traffic perception, where the vehicle environment should be automatically observed in order to improve the safety and assist the driver [12]-[15]. Small, fully integrated laser scanners can provide a very cost effective way to monitor obstacles near the car or truck as well as at higher distance in order to prevent collisions and maintain a proper distance to the preceding vehicle. In this specific application, for example, a typical measurement range R needed is up to 100m, which corresponds to 670ns in time ( t=2*r/c). In addition to precision and measurement range, certain other TDC characteristics are also desirable in real environment applications. These are low power consumption and high flash-type conversion speed to enable high measurement rate to be achieved, for example. In addition, automatic calibration techniques to combat process parameter, voltage, and temperature (PVT) variations would be called for to minimize the need for separate calibration and the resulting system complexity in practical applications. Finally, full integration with common moderate line width CMOS technology would be also beneficial to reduce the costs when moderate production volumes are involved.

3 A TDC with the capability to measure not only a single start-stop time interval but to a multiple of start-stop signals would be highly beneficial in practical applications [16], [17]. In traffic perception, for example, the highly varying environmental conditions make the monitoring challenging and cause uncertainty to the measurement. The laser pulse can during its journey from the transmitter to the target be partly reflected from several objects, such as a cover window, rain or fog, and finally from the target (another car, passenger etc.) and thus several adjacent stop pulses can reach the TDC as a result of a single laser flash. In order to be able for the laser radar to keep track on the targets properly, the TDC should be able to separately measure the time positions of all these stop pulses with respect to the laser shot (start pulse). Furthermore, as suggested in more details below in section II, the capability of the TDC to measure simultaneously (within a single measurement shot) to several stop signals could be used to compensate for the distance measurement error caused by the varying amplitude of the reflected laser pulse, a phenomenon known as timing walk error [11]. This error can be reduced, as is explained in detail below, by estimating the pulse shape in time domain with a multi-channel time-to-digital converter. The goal of the present research was to develop a high precision multi-channel CMOS TDC capable of measuring time intervals between 7 timing signals (start and six separate stops). The TDC was designed mainly for a pulsed TOF laser radar to be applied for vehicular perception in a project whose specific aims are presented in more details in [18]. This project aims at the development of a low cost, lightweight and miniature laser scanner sensor for environmental perception to significantly increase the penetration of advanced driver assistance systems, ADAS, in the automotive market. The project vision is to have an accident-free traffic environment by the use of effective environment perception systems. Laser scanners are believed to be the predominant generic environment sensing technology having potential to solve many of the potential driver assistance functions. To reach the objectives of small and low cost laser scanner a number of new techniques have to be developed and evaluated. These include, for example, the use of custom designed omnidirectional lens, very large micro-electromechanical (MEMS) mirror and the use of

4 high-performance integrated circuits for the laser pulse detection and time-of-flight measurement (TDC). The TDC specifications aimed at were a measurement range of several microseconds (100m=670ns), a single shot precision of about 10ps and low sensitivity to PVT (process, supply voltage, temperature). Since the circuit developed demonstrates the integration of a picosecond accurate multi-channel TDC on a single CMOS die, it is believed that suggested technology may find other applications as well especially since the configuration of the circuit with respect to the number of start and stop channels, for example, can easily be modified. The paper is organized as follows. Section II explains briefly the use of a multi-channel time-todigital converter in pulsed time-of-flight laser ranging and especially in timing walk error compensation, section III goes through the operation and architecture of the TDC designed here, section IV focuses on the measurement results, and the conclusions are summarized in section V. II. TIME-DOMAIN WALK ERROR COMPENSATION One of the basic functions of the receiver in any optical pulsed TOF radar range-finder is to detect the time position of the optical echo received from the target with respect to a reference signal (transmitted pulse or other pulse signal having a known time relation to the transmitted pulse). The receiver typically consists of an optical detector (avalanche photo detector), a transimpedance type preamplifier, post amplifiers and a timing discriminator. The task of the timing discriminator circuit is to produce in some way a timing mark whose time position would be independent of the varying amplitude of the received analogue timing signal (low timing walk ). Unfortunately, there can be wide variations in the power of the received echo, and thus also in its amplitude. Fig. 1b shows how timing walk error is produced in case of constant threshold detection, for example. In a pulsed TOF laser radar intended for a traffic perception system application, for example, the amplitude of the received optical echo may vary in a range of 1:100 000 or even more and yet the timing walk error should be less than 70ps (corresponding to a distance of +/-5mm). This dynamic range arises

5 from variations in the optical reflectivity and in the distance to be measured [11]. An object which may on one occasion be a shining metal surface (specular surface) may in other cases be covered in mud, for example. Moreover, as the timing discriminator is preceded by a sensitive, low noise amplifier chain to convert the low current signal from the avalanche photo diode (APD) to a voltage-signal for timing discrimination, the timing walk error arises not only due to the finite rise time of the timing signal but also because of non-constant electrical delay in the electronic receiver [19]. It should also be noted that the dynamic range of the optical input signal inevitably exceeds the linear dynamic range of the receiver amplifier (typically <1:500 for a transimpedance preamplifier), which poses an additional challenge for the timing discrimination. As can be seen in Fig. 1b, both the slew-rate of the leading edge and apparent width (at constant threshold level) of the analogue timing pulse change with the changing pulse amplitude. If one of them or both could be measured, this information could be exploited to compensate for the timing walk error. In this method the timing walk error would be measured and recorded in a separate calibration measurement in beforehand and then this data would be used in the real measurement for the timing walk compensation (from a look-up-table, for example). The multi-channel time-todigital converter is able to measure time intervals between several timing signals that lie close to each other. In addition to the time interval between the transmitted and reflected pulse corresponding the distance of the object, the pulse width, for example, can be measured simultaneously. Moreover, the slew-rate-based compensation technique could perhaps enable one to calculate the time position of the pulse probably without any need for the time walk pre-calibration contrary to what was suggested above and implemented in [20], [21]. It should be noted that the proposed timing discrimination techniques call for picosecond-level accuracy in multi-channel time interval measurement, since the typical pulse widths and rise times are in a nanosecond or subnanosecond range. Compensation techniques which call for multi-channel time interval measurement techniques of ps accuracy have the additional advantage that they rely on a time

6 interval measurement facility which is already present in the time-of-flight system in any case, and that they also work when the signal amplitude is clipped in the receiver channel. Based on what was presented above it should be clear that a multi-channel time-to-digital converter could serve as a basic element in pulsed time-of-flight studies not only for the determination of the time intervals between pulses but also for the compensation of the timing walk error due to varying timing pulse amplitudes. III. THE MULTI-CHANNEL TDC A. Operation modes The TDC designed here has two operating modes, Mode 0 and Mode 1, which differ in the way they use the two available stop signals to measure the width or slew-rate of the received stop pulses. In Mode 0 the TDC digitizes the arrival time of the rising edge of the start pulse and the rising and falling edges of a maximum of three stop pulses in one stop channel, as shown in Fig. 2. By measuring the arrival time of both edges of the stop pulses (trailing and leading), the pulse positions (T SP1 -T SP3 ) and widths (T w1 -T w3, apparent widths at a constant timing comparator threshold) can be determined for three separate stop signals. In Mode 1 the stop pulses arrive through two separate inputs to the TDC. Each of the inputs may have up to 3 separate stop pulses (stop0 and stop1 in the lower diagram in Fig. 2). The circuit measures the positions of the trailing edges of each of the stop0 pulses with respect to the start pulse, as in Mode 0 (T SP1 -T SP3 ), but in addition it measures the time intervals between the corresponding stop0 and stop1 edges (T r1 -T r3 ). Mode 1 can be used for slew-rate-based walk error compensation, for example [20]. In this case stop0 and stop1 would be generated with two separate timing comparators having different thresholds but the same analogue timing signal at their inputs. B. Measurement principle

7 The TDC uses an on-chip reference oscillator (external crystal) to stabilize the internal interpolation time delays with respect to PVT variations and jitter. The internal interpolation time delays are a dividend of the reference clock cycle time, as depicted in Fig. 3, and the TDC uses a counter and a two-level interpolation architecture to resolve the time intervals between the timing signals (start and stops) [16], [17], [22], [23]. The counter counts the full clock cycles between the timing signals. The first interpolation level (coarse interpolator) locates the timing signal within the counter clock cycle by creating multiple even-sized time samples within it and registering the relevant time samples, ST C and SP C in Fig. 3. The second interpolation level (fine interpolator) locates the timing signals within the result of the first interpolation level, ST F and SP F in Fig. 3. The final measurement result T meas is composed of the results of the counter and interpolators. C. Measurement core architecture The architecture of the measurement core is presented in Fig 4. The circuit employs several techniques which are explained here briefly. More detailed descriptions of the reference recycling technique, synchronization techniques and interpolation techniques and their effects on the measurement performance can be found in [22], [24], [25]. The first interpolation level, the coarse interpolator, creates a multiphase clock out of the external ~10MHz reference clock F REF. The reference signal propagates through 8 differential adjustable delay elements and creates time samples after every element with a time difference of ~320ps. The delay line uses a reference recycling technique in order to reduce the reference clock frequency needed and to improve the integral non-linearity of the interpolation [22], [26]. The delay elements are of the multiplexer type, and the end of the last delay element is connected back to the first element. The signal is recycled in the delay line several times (selectable from 1 64) before the new reference edge arrives and removes the accumulating jitter from the time sample generation. The internal delay line frequency is hence 1 64 times the reference frequency. The total delay in the recycled delay line is delay-locked to the reference clock cycle time with a phase detector (PD)

8 and charge pump (CP), which stabilize the time sample generation with respect to process, voltage and temperature variations. The asynchronous timing signals (start and 6 stops) register the state of the delay line, and the location of the timing signal within the delay line can be resolved using this information. The first arrived timing signal enables a 14-bit counter, which counts the rounds of the recycling delay line. The following timing signals take samples from this counter, which provides a time interval measurement range of ±74.4µs with 220MHz internal frequency. The negative measurement result corresponds to the situation when the stop signals arrive before the start signal, which may well be the case in a practical laser radar at short measurement distances due to the electronic delay in the start pulse generation. The fine interpolator, structure presented in Fig. 5a, resolves the location of the timing signal within the delay of the first interpolator delay element, as registered at the coarse interpolation stage. After the result at the coarse interpolation level has been obtained, a synchronized time sample from the coarse delay line is fed to the fine interpolation, signal sync in Figs. 4 and 5a. This creates 8 parallel time samples with a time difference of ~10ps. Analogously, the asynchronous timing signal (start or stop) is first delayed in order to compensate for the synchronization delay and then fed to the fine interpolator, signal async in Figs. 4 and 5a, where it creates 8 parallel time samples with a time difference of 80ps. The coincidence of the 16 time samples varies according to the time difference between the asynchronous and synchronized timing signals from the coarse delay line. A register bank stores the coincidence, and the location of the timing signal within the coarse interpolation result is decoded from this information. The parallel high resolution time samples are created with load capacitor-scaled delay elements presented in Fig. 5b [22]. The delay of the element increases with even steps when the number of unit capacitors, n, inside the element is increased. The number inside the elements in Fig. 5a describes the amount of unit capacitors in that element. Totally 16 delay elements and 64 arbiters in Fig. 5a are able to create 64 interpolation points to the fine interpolation stage. However, only 32 interpolation points in the middle are effective and the additional elements are for synchronization delay offset compensation [24]. Together with the 16

9 interpolation points in the coarse interpolator the measurement resolution LSB can be deduced from the chosen reference frequency f REF and the recycling factor RF: LSB = 1 / (f REF x RF x 16 x 32). (1) D. Circuit architecture The architecture of the whole TDC circuit is presented in Fig. 6. The circuit includes an on-chip oscillator which uses a crystal as a time reference, although an external TCXO (Temperature Compensated Crystal Oscillator) can also be used. From the oscillator, the reference signal goes to the delay-locked loop presented in Fig. 4. Seven parallel time digitizers then resolve the locations of the timing signals with respect to the reference clock. The ALU decodes the raw data from the counter and interpolators to form a binary word and calculates the time intervals between the start and stop pulses. The data interface to and from the TDC is a SPI (Serial Peripheral Interface) which can transmit serial data at a frequency of 100MHz. The TDC indicates the availability of a new measurement result by setting the output signal Ready. The circuit can be tested without external timing signals by means of a BIST (Built-In Self Test) in which the timing signals are created by corresponding control words at the SPI interface. The SPI-master, e.g. a microprocessor, can launch timing signals one by one and the time interval measurement result depends on the time difference between the control words. The block Input Control directs the correct timing signals to the digitization unit: one external start signal (rising edge) and a total of six external stop signals (rising and falling edges in turn) in Mode 0, one external start and three external stops from both inputs, stop0 and stop1, in Mode 1, or an SPI-generated start and six stops in BIST mode. The ALU, SPI interface, Control & Status and BIST blocks were modelled with Verilog HDL and synthesized at the circuit level.

10 IV. MEASUREMENT RESULTS The TDC circuit was fabricated in 0.35µm CMOS technology. The circuit dimensions are 2.4mm x 3.7mm, and the power consumption at a 3.3V operating voltage and a 220MHz internal frequency is 85mW. The following measurement results were collected from 5 circuits using a 20MHz crystal as a reference. A photograph of the circuit is presented in Fig. 7. A. Interpolation non-linearity Non-linearity in the interpolator shifts the interpolation slots from their correct time-domain positions and causes error in the digitization of each timing signal. The signal propagation time through identical delay elements, registers and wires varies due to differences in process parameters and the processed layout, non-identical signal routes and systematic supply and bias-voltage interference from the other blocks. The differential and integral non-linearities (DNL and INL) were measured by feeding 10 000 000 asynchronous timing signals to every interpolator and collecting the hit distribution i.e. how many hits were collected by each of the 512 interpolation slots (16 slots in the first interpolation level and 32 slots in each of them due to the second interpolation level). When some slot gathers more than an average value of hits, its size is more than average (positive DNL) and vice versa. The accumulated delay error in every slot (INL) can be solved by summing the DNLs up to that slot. The DNL and INL values in one circuit are presented in Fig. 8. The figures show the non-linearities in the whole ~4.54ns interpolation region with 512 interpolation slots. The delay variation in the elements of the recycling delay line is the predominant source of INL. The largest measurement error due to non-linearity, ~30ps, occurs when one timing signal (start or stop) hits interpolation slot 21 and the other interpolation slot 274, as seen in the lower diagram in Fig. 8, assuming the stop interpolation would show a similar performance. The standard deviations of the INLs in different interpolators and circuits were measured to be varying in the range 4.0ps 6.3ps.

11 B. Temperature drift Temperature changes affect the signal propagation speed in logic elements, registers and wiring in many ways. The delay cells in the TDC are delay-locked to the reference clock cycle time, which minimizes temperature drift in the delay lines. The temperature drift in the interpolation registers should also cancel out, because the start and stop interpolators are identical. Layout and process parameter differences in timing signal paths can cause delay differences, however, and these can drift with temperature. Temperature drift was determined here by measuring constant time intervals from a signal generator between start and three successive stop-pulses (in range 500ns 12µs) and also the corresponding stop pulse widths (in range 12ns 170ns) when the circuit was in a heating chamber. The measurement results drifted by less than 0.5ps/ C, when the temperature was altered from -40 C to +85 C. The reference signal for the TDC (20MHz) was taken from a signal generator, which was in a room temperature, in order to remove the effect of the crystal temperature drift. C. Precision Perhaps the most important parameter when evaluating time-to-digital converters is the precision of the measurements obtained. Interpolation non-linearity, delay line jitter, jitter in the timing signals and quantization noise all create errors in the measurement results, which can fluctuate around the real value when a constant time interval, which is asynchronous with respect to the clock, is measured many times. Thus the precision of the TDC can be revealed by the standard deviation of the measurement results. This standard deviation (or sigma value) also varies with the time interval to be measured, however, mainly because the difference in the INL of the start and stop interpolations depends on the time interval. Thus the best precision can be achieved, for example, when the time interval is a multiple of the interpolation region, because the start and stop signals hit to the same interpolation slot at every individual measurement and the similar INL in the two interpolations cancels out when generating the measurement result.

12 Several time intervals around 400ns were generated with coaxial cables and each was measured 30 000 times in order to resolve the precision. The measurement rate was 35kHz. The precisions obtained with 5 TDCs over the whole interpolation range (~4.54ns) are presented in Fig. 9. The precision with different time intervals varied from 6.1ps to 9.8ps. The RMS value over all measured precision values reveals the performance in the whole interpolation region. In the measured circuits the RMS precision fluctuated in the range 8.0ps 8.6ps. The post processing of the results with an INL look-up-table removes the effect of INL to the measurement results and the RMS precision improved further by 0.5ps 1.0ps in different circuits. The good performance in terms of precision is a result of several design choices. The INL stays good, because the accumulation of time error (DNL) in the delay elements was minimized by using a short delay line (only 8 differential elements) in the recycling delay line and parallel delay line structures in the second interpolation level. High resolution (low quantization noise) results from the second interpolation level, where low mismatch between the time samples was achieved with accurate capacitive load differences. Also periodic jitter removal with the external reference source prevents the jitter from deteriorating the precision. D. Effects of other parameters The effects of changes in operating voltage, reference frequency and internal frequency on the RMS measurement precision are presented in Table I. In measurements 1-4 in this table the operating voltage was changed from 2.7V to 3.6V while the internal frequency was constant at 180MHz. The measurement precision deteriorated slightly as the voltage was raised. An increase in the supply made the structures in the circuit faster, and the biasing voltage in the delay elements decreased in order to keep the element delays constant. Also, delay elements at a lower biasing voltage are more susceptible to noise in the operating and bias voltages, which will similarly detract from the precision.

13 In measurements 5-9 the recycling factor was increased from 8 to 12, which also increased the internal frequency and improved the measurement resolution. This, together with the fact that the bias voltage increase also reduced the variations in the delay elements, led to enhanced precision. In case no. 9 the TDC was unable to reach +85 C with real measurement results because the internal frequency (240MHz) was too high for the circuit. In measurements 10-14 the external reference frequency was increased by using a Tektronix AWG 2021 signal generator as the reference source. The precision improved slightly when the reference frequency was increased and the recycling factor was decreased, respectively. With the higher reference clock the jitter had less time to accumulate in the recycling delay line. The new jitter-free reference signal removed the accumulated jitter more often, which improved the precision. The best possible measurement precision was aimed at in measurements 15-16, where the operating voltage was raised to the highest permissible level (3.6V) and the internal frequency was also close to its maximum. The RMS precision in both cases was below 8ps, even though the TDC was not able to reach the maximum specified operating temperature (+85 C) in case 16. E. Multi-channel measurement One start and three successive stop-pulses with different pulse widths and time intervals over several microseconds were generated with the Tektronix AWG 2021 signal generator. The stoppulse cable was divided to both stop input channels of the TDC so that a longer coaxial cable was in the stop1 input path than in the stop0 input path. The measurements were repeated 100 000 times in the both measurement modes and the distributions of the results with their average values (µ) and standard deviations (σ) are presented in Fig. 10. The measurements were carried out using 3.3V supply, 20MHz crystal as a reference and 220MHz internal frequency (recycling factor 11). The diagram on top of Fig. 10 shows the time intervals between the start and three successive stoppulses and is similar in both measurement modes. The next diagram is collected in Mode 0 and shows the stop-pulse widths. The last diagram describes the operation in Mode 1 and shows the

14 propagation time difference of different length coaxial cables between the two stop input channels. The small offsets in the averaged values in the last diagram result from differences in timing signal detection moments of the interpolators and the offsets stayed constant when different length coaxial cables were measured. The jitter of the signal generator is present in the results. V. CONCLUSIONS This multi-channel time-to-digital converter (TDC) implemented in a 0.35µm CMOS technology presented here is based on a combination of a counter and stabilized two-stage delay line interpolation, which provides for a µs-level linear dynamic range, stable ps-level LSB resolution and good temperature stability. The TDC has autocalibration, i.e. its resolution is locked to the cycle time of the external reference crystal. Thus no additional calibration cycles are needed during measurement. The standard 4-wire SPI interface facilitates the use and simplifies the connection to the device. The multi-channel interpolation architecture makes measurement of the intervals between several timing signals possible in one measurement cycle. This widens the use of TDCs for different applications, especially for pulsed time-of-flight laser range finding, as the multi-channel TDC can not only enable the laser radar system to detect several successive echoes but also take responsibility for the walk error compensation. The timing walk (dependence of the timing moment on the echo amplitude) is the main source of systematic error in pulsed time-of-flight laser radars. These features can be considered as extremely useful in future efforts to realize compact laser scanner based perception systems for automotive and robotic applications, for example. In fact, the accurate multi-channel TDC techniques developed enable one to realize a time-domain RF/highspeed optical pulse detection that makes it possible to detect with picosecond accuracy the time position of the received pulse over a wide dynamic amplitude range exceeding that of the receiver. The measurement results verify the operation of the TDC in different circumstances. Time interval measurement is stable in the face of variations in temperature and operating voltage, and the low

15 internal jitter in the delay lines makes it possible to use a low frequency external crystal as a reference. A measurement precision better than 8ps is achieved over the whole temperature range without recourse to time-consuming post-processing of the results, e.g. by means of look-up INL tables. Table II compares the designed TDC to other integrated TDCs. The first two TDCs, designed mainly for digital phase locked loops (DPLL), reach also better than 10ps measurement precision but in a short measurement range. Small line width technology and separate/missing stabilization decrease the power consumption and lead to smaller gate delays, which simplifies the fine interpolation stage. Integrated and continuous stabilization method, presented here, increases the linear measurement range, simplifies the usage and makes non-stop operation possible. The other TDCs in Table II have enough range to be used in laser TOF distance measurement. The performance of the presented TDC is, however, superior. To our knowledge, the measurement precision of the developed multi-channel TDC is the best achieved to date for a long measurement range integrated TDC circuit, without post-processing of the results.

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20 LIST OF FIGURES Fig. 1. (a) Pulsed laser time-of-flight (TOF) distance measurement and (b) the concept of walk error. Fig. 2. Measurement modes. Fig. 3. Conceptual timing diagram. Fig. 4. The measurement core. Fig. 5. (a) Fine interpolation structure, and (b) capacitor-scaled delay element. Fig. 6. The TDC block diagram. Fig. 7. Photograph of the TDC. Circuit dimensions are 2.4mm 3.7mm. Fig. 8. DNL and INL in the interpolator, 16*32=512 time slots. Fig. 9. Single-shot precision (standard deviation) of 5 different circuits at an internal frequency of 220MHz, precision is shown as a function of remainder Q, where T=N*(1/220MHz) + Q. Fig. 10. Multi-channel measurement in operation modes 0 and 1. LIST OF TABLES Table I. Effects of environment changes to the measurement precision. Table II. Comparison with other TDCs.

21 a. laser transmitter TDC result receiver receiver start stop b. start stop detection threshold R=( T/2) c walk error Fig. 1. (a) Pulsed laser time-of-flight (TOF) distance measurement and (b) the concept of walk error.

Fig. 2. Measurement modes. 22

23 T meas REFCLK DLL(15:0) START STOP CTR ST f ST c SP f SP c 0 1 T meas = 16 32 CTR + 32 (ST c SP c )+ ST f - SP f Fig. 3. Conceptual timing diagram.

Fig. 4. The measurement core. 24

Fig. 5. (a) Fine interpolation structure, and (b) capacitor-scaled delay element. 25

Fig. 6. The TDC block diagram. 26

Fig. 7. Photograph of the TDC. Circuit dimensions are 2.4mm 3.7mm. 27

INL [ps] DNL [ps] 28 8 6 4 2 0-2 -4-6 -8-10 10 1 74 147 220 293 366 439 512 Interpolation Slot 5 0-5 -10-15 -20-25 -30 1 74 147 220 293 366 439 512 Interpolation Slot Fig. 8. DNL and INL in the interpolator, 16*32=512 time slots.

Fig. 9. Single-shot precision (standard deviation) of 5 different circuits at an internal frequency of 220MHz, precision is shown as a function of remainder Q, where T=N*(1/220MHz) + Q. 29

5.131 5.149 5.167 5.185 X 5.167 5.185 5.202 5.22 X 5.158 5.176 5.194 5.211 Number of Hits 4.83 4.847 4.865 4.883 X 15.368 15.385 15.403 15.421 X 67.729 67.747 67.765 67.782 Number of Hits 95.854 95.872 95.89 95.907 X 1614.276 1614.293 1614.311 1614.329 X 4525.524 4525.542 4525.559 4525.577 Number of Hits 30 50000 40000 30000 20000 10000 0 STOP 1 µ=95.886ns σ=9.208ps STOP 2 µ=1614.299ns σ=9.449ps STOP 3 µ=4525.547ns σ=9.361ps Time Between Start and Stops [ns] 50000 40000 30000 20000 10000 0 STOP 1 µ=4.869ns σ=9.041ps STOP 2 µ=15.386ns σ=10.236ps STOP 3 µ=67.753ns σ=9.604ps Stop Pulse Widths [ns] 50000 40000 30000 20000 10000 0 STOP 1 µ=5.158ns σ=9.683ps STOP 2 µ=5.181ns σ=8.588ps STOP 3 µ=5.171ns σ=9.563ps Time Between Stop0 and Stop1 [ns] Fig. 10. Multi-channel measurement in operation modes 0 and 1.

31 # Supply [V] Ext. Ref [MHz] Recyc factor Int. Freq [MHz] RMS σ [ps] 1 2.7 20 9 180 11.2 2 3 20 9 180 11.3 3 3.3 20 9 180 11.7 4 3.6 20 9 180 12.3 5 3.3 20 8 160 12.6 6 3.3 20 9 180 11.7 7 3.3 20 10 200 9.4 8 3.3 20 11 220 8.6 9 3.3 20 12 240 7.7 10 3.3 5 36 180 12.7 11 3.3 10 18 180 12.2 12 3.3 20 9 180 11.9 13 3.3 30 6 180 11.7 14 3.3 45 4 180 10.7 15 3.6 20 12 240 7.7 16 3.6 20 13 260 7.6 Table I. Effects of environment changes to the measurement precision.

32 Ref. Architecture Technology [µm] [27] delay line with resistors [28] delay line and time amplification [29] counter and vernier [30] counter and TAC 0.8 Bi- CMOS [16] counter and RCdelay lines [17] counter and delay lines [31] counter and ring oscillator Ref. clock [MHz] LSB [ps] Precision RMS [ps] Max. range [µs] Chan nels Power [mw] 0.09 CMOS NA 4.7 3.3 0.0006 2 3.6 0.09 CMOS NA 1.25 <1.25(a) 0.0006 2 3 0.8 CMOS 166.66 46.9 40 10 2 NA 100 32 <25 2.5 2 350 0.25 CMOS 320 24.4 22.4 12.8 8 NA 0.6 CMOS 66 29.6 28 16(a) 496 10 50 0.35 CMOS 10 156 79 0.985 2 72 [32] counter and TAC 0.35 CMOS 80 50 NA 0.25 2 0.75 [23] counter and CTDSA 0.35 CMOS 100 1.2 11 3.2(a) This counter and delay lines (a) with look-up tables or result post processing 0.35 CMOS 20 8.88 8.6 8.0(a) 327 2 36 74 7 85 Table II. Comparison with other TDCs.