The MC10 is a dual master slave dc coupled J K flip flop. Asynchro nous set (S) and reset (R) are provided. The set and reset inputs override the clock. A common clock is provided with separate J K inputs. When the clock is static, the J K inputs do not effect the output. The output states of the flip flop change on the positive transition of the clock. P D = 0 mw typ/pkg (No oad) f Tog = 0 Mz typ t pd = ns typ t r, t f =. ns typ (0% 0%) CDIP 16 SUFFIX CASE 60 16 1 MARKING DIAGRAMS MC10 AWYYWW DIP PIN ASSIGNMENT Pin assignment is for Dual in ine Package. For PCC pin assignment, see the Pin Conversion Tables on page 1 of the ON Semiconductor MEC Data Book (D1/D). OGIC DIAGRAM PDIP 16 P SUFFIX CASE 64 PCC 0 FN SUFFIX CASE 77 16 A = Assembly ocation W = Wafer ot YY = Year WW = Work Week ORDERING INFORMATION 1 MC10P AWYYWW 1 10 AWYYWW R S TRUT TABE COCK J K TRUT TABE* R S Q n+1 J K Q n+1 Q n N.D. Q n Q n Device Package Shipping MC10 CDIP 16 Units / Rail MC10P PDIP 16 Units / Rail MC10FN PCC 0 46 Units / Rail N.D. = Not Defined * Output states change on positive transition of clock for J K input condition present. Semiconductor Components Industries, C, 00 January, 00 Rev. 7 1 Publication Order Number: MC10/D
MC10 EECTRICA CARACTERISTICS Characteristic Symbol Test imits Pin Under 0 C + C + C Test Min Max Min Typ Max Min Max Unit Power Supply Drain Current I E 7 4 6 7 madc Input Current I in 6,7,9,10,11 4,,1,1 I in 4,,6,7,9, 10,11,1,1 Output Voltage ogic 1 V O (.) Output Voltage ogic 0 V O (.) Threshold Voltage ogic 1 V OA (4.) Threshold Voltage ogic 0 V OA (4.) Switching Times (0Ω oad) Clock Input Propagation Delay t 9++ t 9+ 0. 0. 1.060 1.060 90 90 1.00 1.00 4 60 0.90 0.90 1.67 1.67 1.6 1.6 0. 0. 0.960 0.960 0 0 0.90 0.90 6 90 0.10 0.10 1.60 1.60 1.60 1.60 0. 0. 0.90 0.90 0.910 0.910 Rise Time (0 to 0%) t +, t +, 1.1 4. 1.1.0 4. 1.1 4.7 Fall Time (0 to 0%) t, t, 1.1 4. 1.1.0 4. 1.1 4.7 4. 4. 6 90 0.700 0.700 1.6 1.6 1.9 1.9 4.6 4.6 µadc µadc Vdc Vdc Vdc Vdc ns Set Input ns Propagation Delay t ++ t 1++ t + t 1+.... Reset Input ns Propagation Delay t 4+ t 4+ t 1+ t 1++.... Setup Time t setup 7.. 1.0. ns old Time t hold 7 1. 1. 1.0. ns Toggle Frequency (Max) f tog 0 Mz 1. Individually test each input; apply V Imax to pin under test.. Individually test each input; apply V Imin to pin under test.. Output level to be measured after a clock pulse has been applied to the C E Input (Pin 6) 4. Output level to be measured after a clock pulse has been applied to the C E Input (Pin 6)
MC10 EECTRICA CARACTERISTICS (continued) TEST VOTAGE VAUES (Volts) Characteristic @ Test Temperature V Imax V Imin V IAmin V IAmax V EE Symbol 0 C 0.90 90 1.0 1.00. + C 0.10 0 1.10 1.47. + C 0.700 1.0 1.440. Pin TEST VOTAGE APPIED TO PINS ISTED BEOW Under (V CC ) Test V Imax V Imin V IAmin V IAmax V EE Gnd Power Supply Drain Current I E Input Current I in 6,7,9,10,11 4,,1,1 I in 4,,6,7,9, 10,11,1,1 Output Voltage ogic 1 V O (.) Output Voltage ogic 0 V O (.) Note 1. Note 1. Threshold Voltage ogic 1 V OA (4.) 6 Threshold Voltage ogic 0 V OA (4.) 6 6 6 Note. Note. Switching Times (0Ω oad) Clock Input Pulse In Pulse Out. V +.0 V Propagation Delay t 9++ t 9+ Rise Time (0 to 0%) t +, t +, 9, Fall Time (0 to 0%) t, t, 9, 9 9 Set Input Propagation Delay t ++ t 1++ t + t 1+ 1 1 Reset Input Propagation Delay t 4+ t 4+ t 1+ t 1++ 4 4 1 1 Setup Time t setup 7 6, 9 old Time t hold 7 6, 9 Toggle Frequency (Max) f tog 9 1. Individually test each input; apply V Imax to pin under test.. Individually test each input; apply V Imin to pin under test.. Output level to be measured after a clock pulse has been applied to the C E Input (Pin 6) 4. Output level to be measured after a clock pulse has been applied to the C E Input (Pin 6) Each MEC 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 00 linear fpm is maintained. Outputs are terminated through a 0 ohm resistor to.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
MC10 PACKAGE DIMENSIONS PCC 0 FN SUFFIX PASTIC PCC PACKAGE CASE 77 0 ISSUE C B N Y BRK U D M Z W D X G1 V VIEW D D Z A R K1 C G G1 E J T VIEW S VIEW S K F 4
MC10 PACKAGE DIMENSIONS T F A E G D 16 P B C N CDIP 16 SUFFIX CERAMIC DIP PACKAGE CASE 60 10 ISSUE T K M J 16 P A G B F C S K D 16 P T PDIP 16 P SUFFIX PASTIC DIP PACKAGE CASE 64 0 ISSUE R J M
MC10 Notes 6
MC10 Notes 7
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