QUA FLIP-FLOP SN54/LS75 The LSTTL /SI SN54 /LS75 is a high speed Quad Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A aster Reset input resets all flip-flops, independent of the lock or inputs, when LOW. The LS75 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all otorola TTL families. Edge-Triggered -Type Inputs Buffered-Positive Edge-Triggered lock lock to Output elays of 30 ns Asynchronous ommon Reset True and omplement Output Input lamp iodes Limit High Speed Termination Effects ONNETION IAGRA IP (TOP VIEW) QUA FLIP-FLOP LOW POWER SHOTTY J SUFFIX ERAI ASE 620-09 NOTE: The Flatpak version has the same pinouts (onnection iagram) as the ual In-Line Package. N SUFFIX PLASTI ASE 648-08 PIN NAES LOAING (Note a) 0 3 P R Q0 Q3 Q0 Q3 ata Inputs lock (Active HIGH Going Edge) Input aster Reset (Active LOW) Input True Outputs (Note b) omplemented Outputs (Note b) HIGH 0 U.L. 0 U.L. LOW 0. U.L. 0. U.L. 0. U.L. 5 (2.5) U.L. 5 (2.5) U.L. NOTES: a. TTL Unit Load (U.L.) = 40 µa HIGH/.6 ma LOW. b. The Output LOW drive factor is 2.5 U.L. for ilitary (54) and 5 U.L. for ommercial () b. Temperature Ranges. LOGI IAGRA ORERING INFORATION SN54LSXXXJ SNLSXXXN SNLSXXX eramic Plastic SOI LOGI SYBOL SUFFIX SOI ASE 75B-03 5-327
SN54/LS75 FUNTIONAL ESRIPTION The LS75 consists of four edge-triggered flip-flops with individual inputs and Q and Q outputs. The lock and aster Reset are common. The four flip-flops will store the state of their individual inputs on the LOW to HIGH lock (P) transition, causing individual Q and Q outputs to follow. A LOW input on the aster Reset (R) will force all Q outputs LOW and Q outputs HIGH independent of lock or ata inputs. The LS75 is useful for general logic applications where a common aster Reset and lock are acceptable. TRUTH TABLE Inputs (t = n, R = H) Outputs (t = n+) Note Q Q L L H H H L Note : t = n + indicates conditions after next clock. GUARANTEE OPERATING RANGES Symbol Parameter in Typ ax Unit V Supply Voltage 54 4.5 4.75 5.0 5.0 5.5 5. V TA Operating Ambient Temperature Range 54 55 0 70 IOH Output urrent High 54, 0.4 ma IOL Output urrent Low 54 4.0 8.0 ma HARATERISTIS OVER OPERATING TEPERATURE RANGE (unless otherwise specified) Symbol Parameter in Typ ax Unit Test onditions VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage 54 0.7 0.8 V Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VI Input lamp iode Voltage 0.65.5 V V = IN, IIN = 8 ma VOH VOL Output HIGH Voltage Output LOW Voltage 54 2.5 3.5 V V = IN, IOH = AX, VIN = VIH 2.7 3.5 V or VIL per Truth Table 54, 0. 0.4 V IOL = 4.0 ma V = V IN, VIN = VIL or VIH 0.35 0.5 V IOL = 8.0 ma per Truth Table IIH Input HIGH urrent 20 µa V = AX, VIN = 2.7 V 0. ma V = AX, VIN = 7.0 V IIL Input LOW urrent 0.4 ma V = AX, VIN = 0.4 V IOS Short ircuit urrent (Note ) 20 00 ma V = AX I Power Supply urrent 8 ma V = AX Note : Not more than one output should be shorted at a time, nor for more than second. 5-328
SN54/LS75 A HARATERISTIS (TA = ) Symbol Parameter in Typ ax Unit Test onditions fax aximum Input lock Frequency 30 40 Hz tplh tphl tplh tphl Propagation elay, R to Output Propagation elay, lock to Output 20 20 3 30 30 ns ns V = 5.0 V L = 5 pf A SETUP REQUIREENTS (TA = ) Symbol Parameter in Typ ax Unit Test onditions tw lock or R Pulse Width 20 ns ts ata Setup Time 20 ns th ata Hold Time 5.0 ns V = 5.0 V trec Recovery Time ns A WAVEFORS *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure. lock to Output elays, lock Pulse Width, Frequency, Setup and Hold Times ata to lock Figure 2. aster Reset to Output elay, aster Reset Pulse Width, and aster Reset Recovery Time EFINITIONS OF TERS SETUP TIE (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOL TIE (th) is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOL TIE indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. REOVERY TIE (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH ata to the Q outputs. 5-329
-A- ase 75B-03 Suffix -Pin Plastic SO- 9 8 -B- P G R X 45 F J -A- ase 648-08 N Suffix -Pin Plastic 8 9 B F S L H G J -A- ase 620-09 J Suffix -Pin eramic ual In-Line 9 -B- 8 L E N F G J 5-330
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