SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

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1 Single own/ Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Optio Include Plastic Small-Outline () Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil IPs description SN4ALS191A...J PACKAGE SN4ALS191A... OR N PACKAGE (TOP VIEW) Q Q A Q C Q GN V CC A C The ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when itructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level traition of the clock () input if the count enable () input is low. A high at inhibits counting. The direction of the count is determined by the level of the down/up () input. When is low, the counter counts up, and when is high, the counter counts down. SN4ALS191A... FK PACKAGE (TOP VIEW) Q A NC Q C Q NC V CC Q GN NC C A NC No internal connection NC These counters feature a fully independent clock circuit. Changes at the control inputs ( and ) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the conditio meeting the stable setup and hold times. These counters are fully programmable. Each output can be preset to either level by placing a low on the input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-n dividers by simply modifying the count length with the preset inputs.,, and are buffered to lower the drive requirement, which significantly reduces the loading on (current required by) clock drivers, for long parallel words. Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PROUCTION ATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1996, Texas Itruments Incorporated POST OFFICE OX 60 ALLAS, TEXAS 26 1

2 description (continued) Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is minimum (0) counting down or maximum (1) counting up. The ripple-clock output () produces a low-level output pulse under those same conditio, but only while the clock input is low. The counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count () output can be used to accomplish look ahead for high-speed operation. The SN4ALS191A is characterized for operation over the full military temperature range of C to 12 C. The SN4ALS191A is characterized for operation from 0 C to 0 C. logic symbol G1 M2 [OWN] M [UP] CTRIV16 1,2 / 1,+ G4 C 2(CT=0)Z6 (CT=1)Z6 6,1, A 1 10 C 9 [1] [2] [4] [8] 2 6 QA Q QC Q This symbol is in accordance with ANSI/IEEE Std and IEC Publication Pin numbers shown are for the, J, and N packages. 2 POST OFFICE OX 60 ALLAS, TEXAS 26

3 logic diagram (positive logic) 12 MAX/ MIN A 1 S C1 1 R QA 1 S C1 1 R 2 Q C 10 S C1 1 R 6 QC 9 S C1 1 R Q Pin numbers shown are for the, J, and N packages. POST OFFICE OX 60 ALLAS, TEXAS 26

4 typical load, count, and inhibit sequences The following sequence is illustrated below: 1. Load (preset) to binary 1 2. Count up to 14, 1 (maximum), 0, 1, and 2. Inhibit 4. Count down to 1, 0 (minimum), 1, 14, and 1 A ata Inputs C QA Q QC Q Count Up Inhibit Count own Load 4 POST OFFICE OX 60 ALLAS, TEXAS 26

5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I V Operating free-air temperature range, T A : SN4ALS191A C to 12 C SN4ALS191A C to 0 C Storage temperature range, T stg C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. recommended operating conditio SN4ALS191A SN4ALS191A UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current ma IOL Low-level output current 4 8 ma fclock Clock frequency MHz tw tsu Pulse duration Setup time high or low low 2 20 ata before 2 20 before 4 20 before 0 20 inactive before ata after th Hold time after 0 0 after 0 0 TA Operating free-air temperature C POST OFFICE OX 60 ALLAS, TEXAS 26

6 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONITIONS SN4ALS191A SN4ALS191A MIN TYP MAX MIN TYP MAX VIK VCC = 4. V, II = 18 ma V VOH VCC = 4. V to. V, IOH = 0.4 ma VCC 2 VCC 2 VOL VCC =4V 4. UNIT IOL = 4 ma V IOL = 8 ma II VCC =. V, VI = V ma IIH VCC =. V, VI = 2. V µa IIL or All others VCC =V. V, VI =04V IO VCC =. V, VO = 2.2 V ma ICC VCC =. V, All inputs at ma All typical values are at VCC = V, TA = 2 C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (OUTPUT) TO (OUTPUT) VCC = 4. V to. V, CL = 0 pf, RL = 00 Ω, TA = MIN to MAX SN4ALS191A SN4ALS191A MIN MAX MIN MAX fmax 20 0 MHz 0 Any Q A,, C, Any Q Any Q For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. ma UNIT 6 POST OFFICE OX 60 ALLAS, TEXAS 26

7 PARAMETER MEASUREMENT INFORMATION SERIES 4ALS/4ALS AN 4AS/4AS EVICES VCC V RL = R1 = R2 S1 RL From Output Under Test CL (see Note A) RL Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R1 R2 Test Point CIRCUIT FOR I-STATE TOTEM-POLE OUTPUTS CIRCUIT FOR OPEN-COLLECTOR OUTPUTS CIRCUIT FOR -STATE OUTPUTS Timing Input High-Level Pulse ata Input tsu th Low-Level Pulse tw VOLTAGE WAVEFORMS SETUP AN HOL TIMES VOLTAGE WAVEFORMS PULSE URATIONS Output Control (low-level enabling) Waveform 1 S1 Closed (see Note ) Waveform 2 S1 Open (see Note ) tpzl tpzh tphz tplz VOL VOH VOLTAGE WAVEFORMS ENALE AN ISALE TIMES, -STATE OUTPUTS 0 V Input In-Phase Output Out-of-Phase Output (see Note C) VOH VOL VOH VOL VOLTAGE WAVEFORMS PROPAGATION ELAY TIMES NOTES: A. CL includes probe and jig capacitance.. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch S1 is open.. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2, duty cycle = 0%. E. The outputs are measured one at a time with one traition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE OX 60 ALLAS, TEXAS 26

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