Chapter 10 CVD and Dielectric Thin Film

Chapter 10 CVD and Dielectric Thin Film 2006/5/23 1 Objectives Identify at least four CVD applications Describe CVD process sequence List the two deposition regimes and describe their relation to temperature List two dielectric thin films 2006/5/23 2 1

CVD Oxide vs. Grown Oxide SiO 2 SiO 2 Si Si Si Grown film Bare silicon Deposited film 2006/5/23 3 CVD Oxide vs. Grown Oxide Growth CVD Oxygen is from gas phase Silicon from substrate Oxide grow into silicon Higher temperature Higher quality Both oxygen and silicon are from gas phase Deposit on substrate surface Lower temperature Higher growth rate 2006/5/23 4 2

CVD - definition Chemical Vapor Deposition (CVD) Chemical gases or vapors react on the surface of solid, produce solid byproduct on the surface in the form of thin film. Other byproducts are volatile and leave the surface. 2006/5/23 5 CVD reaction Gas or vapor phase precursors are introduced into the reactor Precursors across the boundary layer and reach the surface Precursors adsorb on the substrate surface Adsorbed precursors migrate on the substrate surface Chemical reaction on the substrate surface Solid byproducts form nuclei on the substrate surface Nuclei grow into islands Islands merge into the continuous thin film Other gaseous byproducts desorb from the substrate surface Gaseous byproducts diffuse across the boundary layer Gaseous byproducts flow out of the reactor. 2006/5/23 6 3

Figure 10.3 Precursors Showerhead Byproducts Reactants Forced convection region (Laminar flow) Boundary layer Wafer Pedestal 2006/5/23 7 Deposition Process Precursor arrives surface Migrate on the surface React on the surface Nucleation: Island formation 2006/5/23 8 4

Deposition Process Islands grow Islands grow, cross-section Islands merge Continuous thin film 2006/5/23 9 CVD Processes APCVD Low-Pressure CVD Plasma-Enhanced CVD Thin films to be deposited : SiO 2 (USG, PSG, BPSG etc) Si 3 N 4 2006/5/23 10 5

LPCVD Longer MFP Good step coverage & uniformity Operates at low pressure (0.1 ~ 1 Torr) Fewer particles and increased productivity Less dependence on gas flow Vertical and horizontal furnace Runs at temperatures higher than 650ºC 2006/5/23 11 Horizontal Conduction- Convection-heated LPCVD Adaptation of horizontal tube furnace Low pressure: from 0.1 to 1 Torr Used mainly for polysilicon, silicon dioxide and silicon nitride films Can process 200 wafers per batch 2006/5/23 12 6

LPCVD System Pressure Sensor Wafers Loading Door Heating Coils To Pump Process Gas Inlet Temperature Wafer Boat Center Zone Flat Zone Quartz Tube Distance 2006/5/23 13 PECVD Developed when silicon nitride replaced silicon dioxide for passivation layer. Operational pressure from 1 to 10 Torr High deposition rate at relatively low temp. RF induces plasma field in deposition gas Stress control by RF Chamber plasma clean. 2006/5/23 14 7

Plasma Enhanced CVD System Process gases Process chamber Wafer Plasma RF power By-products to the pump Heated plate 2006/5/23 15 Step Coverage A measurement of the deposited film featuring the slope of a step on the substrate surface One of the most important specifications Sidewall step coverage Bottom step coverage Conformality Overhang 2006/5/23 16 8

Step Coverage and Conformity CVD thin film c a Structure h d b Substrate w Sidewall step coverage = b/a Conformity = b/c Bottom step coverage = d/a Overhang = (c - b)/b Aspect ratio = h/w 2006/5/23 17 Factors to impact step coverage Arriving angle of gas precursor Surface mobility of adsorbed precursor 2006/5/23 18 9

Arriving Angle Corner A: 270, corner C: 90 More precursors at corner A Larger the angle, more deposition Thus form the overhang Overhang can cause voids or keyholes 180 B A 270 90 2006/5/23 19 C Void Formation Process overhang Metal Dielectric Metal Dielectric Void Metal Dielectric 2006/5/23 20 10

Arriving Angles, Contact Holes Larger arriving angle Smaller arriving angle PSG Silicon Nitride 2006/5/23 21 Control of Arriving Angle Reducing process pressure Tapering opening 2006/5/23 22 11

Step Coverage, Pressure and Surface Mobility APCVD No mobility LPCVD No mobility High mobility 2006/5/23 23 Gap Fill Fill a gap without voids Voids: cause defect and reliability problems Deposition/Etchback/Deposition Silane and PE-TEOS film Conformal deposition O 3 -TEOS and tungsten CVD High density plasma CVD 2006/5/23 24 12

Gap Fill PMD: zero tolerance voids Tungsten can be deposited into these voids Causing shorts IMD: voids below metal may be tolerable reducing process gas could come out later and cause reliability problem 2006/5/23 25 Top view Void in PMD Void Before W CVD Silicide Silicide Sidewall spacers Contact 2006/5/23 26 13

Unwanted W Line Between Gates Top view Tungsten After W CVD Silicide Silicide Sidewall spacers W plug 2006/5/23 27 Deposition/Etchback/Deposition Ar sputtering Dep. USG Al Cu Etch USG Al Cu Dep. USG Al Cu 2006/5/23 28 14

Conformal Deposition Gap Fill 2006/5/23 29 Conformal Deposition Gap Fill 2006/5/23 30 15

Conformal Deposition Gap Fill 2006/5/23 31 HDP CVD Gap Fill Metal Metal Metal Metal Metal Metal Metal Metal Metal 2006/5/23 32 16

Surface Adsorption Determine precursors surface mobility Affect step coverage and gap fill Two mechanisms: Physical adsorption (physisorption) Chemical adsorption (chemisorption) 2006/5/23 33 Chemisorption Actual chemical bonds between surface atom and the adsorbed precursor molecule Bonding energy usually exceeding 2 ev Low surface mobility Ion bombardment with10 to 20 ev energy in PECVD processes can cause some surface migration of chemisorbed precursors 2006/5/23 34 17

Physisorption Weak bond between surface and precursor Bonding energy usually less than 0.5 ev Dipole-dipole force (hydrogen bonding) Van der Waals forces Ion bombardment and thermal energy at 400 C can cause migration of physisorbed precursors High surface mobility 2006/5/23 35 Bonding energy Adsorptions Distance from surface Physisorbed precursor Chemisorbed precursor Substrate Surface 2006/5/23 36 18

CVD Applications FILMS PRECURSORS Si (poly) SiH 4 (silane) Semiconductor SiCl 2H 2 (DCS) Si (epi) SiCl 3H (TCS) SiCl 4 (Siltet) LPCVD SiH 4, O 2 SiO 2 (glass) PECVD SiH 4, N 2O Dielectrics PECVD Si(OC 2H 5) 4 (TEOS), O 2 LPCVD APCVD&SACVD TM TEOS Oxynitride SiH 4, N 2O, N 2, NH 3 TEOS, O 3 (ozone) PECVD SiH 4, N 2, NH 3 Si 3N 4 LPCVD SiH 4, N 2, NH 3 LPCVD C 8H 22N 2Si (BTBAS) W (Tungsten) WF 6 (Tungsten hexafluoride), SiH 4, H 2 WSi 2 WF 6 (Tungsten hexafluoride), SiH 4, H 2 Conductors TiN Ti[N (CH 3) 2] 4 (TDMAT) Ti TiCl 4 Cu 2006/5/23 37 Dielectric Thin Film Applications Multi-level metal interconnection CVD and SOG plus CVD dielectrics Shallow trench isolation (STI) Sidewall spacer for salicide, LDD, and the source/drain diffusion buffer The passivation dielectric (PD) Dielectric ARC for feature size < 0.25 m 2006/5/23 38 19

Dielectric Thin Film Applications Inter layer dielectric, or ILD, include PMD and IMD Pre-metal dielectric: PMD normally PSG or BPSG Temperature limited by thermal budget Inter-metal dielectric: IMD USG or FSG Normally deposited around 400 C 2006/5/23 39 CMOS example Nitride Oxide PD2 ARC PMD or ILD1 Metal 2, Al Cu W W USG Al Cu Metal 1, Al Cu BPSG PD1 IMD or ILD2 WCVD Sidewall spacer STI n+ n+ USG P-well P-epi P-wafer p+ p+ N-well STI TiN CVD 2006/5/23 40 20

Step Coverage of TEOS and Silane Oxide TEOS Silane 2006/5/23 41 Applications of Dielectric Thin film Shallow trench isolation (STI, USG) Sidewall Spacer (USG) Pre-metal dielectric (PMD, PSG or BPSG) Inter-metal dielectric (IMD, USG or FSG) Anti-reflection coating (ARC, SiON) Passivation dielectric (PD, Oxide/Nitride) 2006/5/23 42 21

Dielectric CVD, Oxide and Nitride Oxide (SiO 2 ) Nitride (Si 3 N 4 ) Similar dielectric strength, > 1 10 7 V/cm Similar dielectric strength, > 1 10 7 V/cm Lower dielectric constant, = 3.9 Higher dielectric constant, = 7.0 Not a good barrier for moisture and mobile ion (Na + ) Transparent to UV Good barrier for moisture and mobile ion (Na + ) Conventional nitride opaque to UV Can be doped with P and B 2006/5/23 43 Shallow Trench Isolation (STI) Grow pad oxide Deposition nitride Etch nitride, oxide and silicon Grow barrier oxide CVD USG trench fill CMP USG Anneal USG Strip nitride and oxide USG USG USG Si Si Si Si Si 2006/5/23 44 22

Shallow Trench Isolation (STI) 2006/5/23 45 PMD Doped oxide PSG or BPSG Phosphorus: gettering sodium and reduce flow temperature. Boron: further reduces flow temperature without excessive phosphorus 2006/5/23 46 23

Sodium Ion Turn-on the MOSFET V G = 0 V D Sodium ions Electron flow V G = 0 V D > 0 Metal Gate Metal Gate SiO 2 n + n + p-si Source Drain Thin oxide + + + + + + + + n + n + p-si Source Drain Normal off Electrons Turn on by Na + 2006/5/23 47 PMD More phosphorus, lower reflow temperature >7wt% phosphorus, hygroscope P 2 O 5 + 3H 2 O 2H 3 PO 4 H 3 PO 4 etches aluminum causes metal corrosion Too much boron will cause crystallization of boric acid. H 3 BO 3. Limit, P% + B% < 10% 2006/5/23 48 24

Question Silicon nitride is a better sodium barrier layer than silicon oxide. Why don t people just use nitride for PMD layer? 2006/5/23 49 Answer Silicon nitride has higher dielectric constant Using nitride can cause longer RC time delay and reduce circuit speed A thin layer of nitride (~ 200 Å) is commonly used as a diffusion barrier layer in the PMD application Prevent diffusion of phosphorus and boron from BPSG diffusing into source/drain 2006/5/23 50 25

PSG Reflow at 1100 C, N 2, 20 min. 0% 2.2% 4.6% 7.2% Source: VLSI Technology, by S.M. Sze 2006/5/23 51 4 4 BPSG Reflow at 850 C, 30 Minutes in N 2 Ambient 2006/5/23 52 26

Development of PMD Processes Dimension PMD Planarization Reflow temperature > 2 m PSG Reflow 1100 C 2-0.35 m BPSG Reflow 850-900 C 0.25 m BPSG Reflow + CMP 750 C 0.18 m PSG CMP - 2006/5/23 53 PMD Applications Roadmap Feature Size ( m) Year Wafer Size (mm) 0.8 0.5 0.35 0.25 0.18 1989 1992 1995 1998 2000 150 200 300 O 3 -TEOS BPSG Thermal Flow or RTP/CMP APCVD Silane BPSG PE-TEOS BPSG LPCVD BPSG Thermal Flow O 3 -TEOS PSG + PE-PSG CMP HDP PSG + PE-PSG CMP Low-k Dielectric CMP 2006/5/23 54 27

IMD Inter-metal dielectric Undoped silicate glass (USG) or FSG Spin-on-glass (SOG) Gap fill and planarization Temperature limited by metal melting Normally 400 C PE-TEOS, O 3 -TEOS, and HDP 2006/5/23 55 TEOS H Tetraethyloxysilane, Si(OC 2 H 5 ) 4 Liquid silicon source H H H H C C O H H H H Commonly used for SiO 2 deposition H C C O Si O C C H H O H H H Good step coverage and gap fill H H C C H H H 2006/5/23 56 28

PE-TEOS Plasma-enhanced TEOS CVD processes TEOS and O 2 Most commonly used dielectric CVD process Deposit USG at ~400 C Mainly for IMD 2006/5/23 57 Spin-on Glass Process Steps PECVD USG barrier layer Spin-on glass SOG cure SOG etchback PECVD USG cap 2006/5/23 58 29

Spin-on Glass (SOG) Processes METAL 4 IMD 3 METAL 3 IMD 2 2006/5/23 59 PE-TEOS PE-TEOS Photo courtesy: Applied Materials Sputtering etchback PE-TEOS 2006/5/23 60 30

TEOS and Ozone O 3 -TEOS O 3 O 2 + O (half-life time: 86 hours at 22 C, < 1ms at 400 C) O + TEOS USG + other volatile byproducts Excellent step coverage and gap fill. Applied for IMD and PMD 2006/5/23 61 O 3 -TEOS vs PE-TEOS PE-TEOS Ozone-TEOS Step coverage: 50% Step coverage: 90% Conformality: 87.5% Conformality: 100% 2006/5/23 62 31

Dielectric Thin Film Characteristics Refractive index Thickness Uniformity Stress Particles 2006/5/23 63 Refractive Index Refractive index, n = Speed of light in vacuum Speed of light in the film 2006/5/23 64 32

Incident light Refractive Index Vacuum n 1 n 1 sin 1 = n 2 sin 2 Film n 2 Refractive light 2006/5/23 65 Film Information from R.I. Refractive index Oxygen rich Nitrogen rich 4.0 Polysilicon Oxygen rich Nitrogen rich Oxygen rich 2.01 1.46 Si 3 N 4 Oxynitride SiO 2 Silicon rich Nitrogen rich Silicon rich 2006/5/23 66 33

Ellipsometry R.I. Measurement Linearly Polarized Incident Light Elliptically Polarized Reflected Light s p n 1, k 1, t 1 n 2, k 2 2006/5/23 67 Thickness Measurement One of the most important measurements for dielectric thin film processes. Determines Film deposition rate Wet etch rate Shrinkage 2006/5/23 68 34

Dielectric Thin Film Thickness Measurement Incident light 1 2 Human eye or photodetector t Dielectric film, n( ) Substrate 2006/5/23 69 Dielectric Thin Film Thickness Measurement Different thickness has different color Tilting wafer also changes the color 2006/5/23 70 35

Question 1 If you see some beautiful color rings on a wafer with a CVD dielectric layer, what is your conclusion? 2006/5/23 71 Answer Color change indicates the dielectric thin film thickness change, thus we know the film with the color rings must have problem with thickness uniformity, which is most likely caused by a non-uniform thin film deposition process. 2006/5/23 72 36

Question 2 Why does the thin film color change when one look at the wafer from different angle? 2006/5/23 73 Answer When one looking at wafer from a different angle, phase shift will change, thus wavelength for constructive interference will change, which causes color change It is important to hold the wafer straight when using the color chart to measure film thickness Tilt wafer makes the film thickness thicker than it actually is 2006/5/23 74 37

Deposition Rate Deposition Rate = Thickness of deposited film Deposition time 2006/5/23 75 Wet Etch Rate Wet Etch Rate = Thickness change after etch Etch time Wet etch rate ratio = Thickness change of the CVD film Thickness change of the thermal oxide film 2006/5/23 76 38

Uniformity Multi-point measurement Definition x1 x Average: x Standard deviation: 2 x 3 N x N ( x 1 x ) 2 ( x 2 x ) 2 ( x 3 N 1 x ) 2 ( x N x ) 2 Standard deviation non-uniformity: /x 2006/5/23 77 Film Stress Mismatch between different materials Two kinds of stresses : intrinsic and extrinsic Intrinsic stress develops during the film nucleation and growth process. The extrinsic stress results from differences in the coefficients of thermal expansion Tensile stress: cracking film if too high (e.g. nitride film) Compressive stress: hillock if too strong (e.g. oxide film) 2006/5/23 78 39

Film Stress Bare Wafer After Thin Film Deposition Substrate Substrate Compressive Stress Negative curvature Substrate Tensile Stress Positive curvature 2006/5/23 79 Illustration of Thermal Stress SiO 2 Si At 400 C L SiO 2 Si At Room Temperature L = T L L 2006/5/23 80 40

Coefficients of Thermal Expansion (SiO 2 ) = 0.5 10 6 C 1 (Si) = 2.5 10 6 C 1 (Si 3 N 4 ) = 2.8 10 6 C 1 (W) = 4.5 10 6 C 1 (Al) = 23.2 10 6 C 1 2006/5/23 81 Stress Measurement 2 E h 1 1 ( ) 1 6t R2 R1 Wafer curvature changes before and after thin film deposition Laser beam scans wafer surface, reflection light indicates the wafer curvature 2006/5/23 82 41

Stress Measurement Laser Mirror Detector 2006/5/23 83 Future Trends HDP-CVD USG for STI Nitride or O 3 -TEOS oxide for sidewall spacer PECVD or RPCVD for PMD barrier nitride HDP-CVD PSG for PMD CMP for planarization Low- dielectric for IMD Silicon oxide/nitride as passivation dielectric 2006/5/23 84 42

Future Trends High- gate dielectric Possible candidates: TiO 2, Ta 2 O 5, and HfO 2 CVD and RTA 2006/5/23 85 Future Trends: Low- Dielectrics Need to reduce RC time delay low- reduces C and copper reduces R Require high thermal stability, high thermal conductivity, and process integration capability CVD CSG (C x Si y O, ~ 2.5-3.0) and -CF (C x F y, ~ 2.5 2.7) Spin-on dielectrics (SOD) Hydrogen silsequioxane (HSQ, ~ 3.0), Porous SOD such as xerogels ( ~ 2.0-2.5) 2006/5/23 86 43

Future Trends: Low- Dielectrics Damascene process Copper metallization No gap fill, no planarization problem Main challenge: Integrate low- with copper metallization 2006/5/23 87 Interconnection Processes Dielectric deposition/planarization Dielectric deposition/planarization Via etch Via etch 2006/5/23 88 44

Interconnection Processes Via fill and polish Trench etch Metal deposition Metal deposition 2006/5/23 89 Interconnection Processes Metal etch Metal polish 2006/5/23 90 45

Summary Applications of dielectric thin film are STI, sidewall spacer, PMD, IMD and PD, in which IMD application is the dominant one Silicon oxide and silicon nitride are the two most commonly used dielectric materials 2006/5/23 91 Summary Basic CVD process sequence: introducing precursor, precursor diffusion and adsorption, chemical reaction, gaseous byproducts desorption and diffusion PMD uses PSG or BPSG, temperature are limited by thermal budget IMD mainly uses USG or FSG, temperature is limited by aluminum melting point PD usually uses both oxide and nitride 2006/5/23 92 46

Summary Silane and TEOS are the two silicon sources for dielectric CVD processes O 2, N 2 O, and O 3 are main oxygen precursors NH 3 and N 2 are the main nitrogen sources Fluorine chemistry is commonly used for dielectric CVD chamber dry clean CF 4, C 2 F 6, C 3 F 8 and NF 3 are the most commonly used fluorine source gases 2006/5/23 93 Summary Argon sputtering process is used for dep/etch/dep gap fill application Compressive stress (~100 MPa) is favored for the dielectric thin film 2006/5/23 94 47