DSLP/LPS Low Power MicroMonitor Chip www.dalsemi.com FEATURES Super-low power version of DS 50 µa quiescent current Halts and restarts an out-of-control microprocessor Automatically restarts microprocessor after power failure Monitors pushbutton for external override Accurate 5% or 0% microprocessor power supply monitoring 8-pin DIP, 8-pin SOIC or space saving µ-sop package available Optional 6-pin SOIC package available Industrial temperature -0 C to +85 C available, designated N PIN ASSIGNMENT PB DSLP 8-Pin DIP (00-mil) PB 8 7 6 5 8 7 6 5 DSLPµ (8-mil µ-sop) PB 5 6 7 8 6 5 0 9 VCC DSLPS 6-Pin SOIC (00-mil) PB 8 VCC 7 6 5 DSLPS- 8-Pin SOIC (50-mil) PIN DESCRIPTION PB - Pushbutton Reset Input - Time Delay Set - Selects 5% or 0% Detect - Ground - Reset Output (Active High) - Reset Output (Active Low, open drain) - Strobe Input - +5 Volt Power DESCRIPTION The DSLP/LPS Low Power MicroMonitor Chip monitors three vital conditions for a microprocessor: power supply, software execution, and external over-ride. First, a precision temperaturecompensated reference and comparator circuit monitors the status of. When an out-of-tolerance condition occurs, an internal power-fail signal is generated which forces reset to the active state. When returns to an in-tolerance condition, the reset signals are kept in the active state for a minimum of 50 ms to allow the power supply and processor to stabilize. of 7 899
DSLP/LPS The second function the DSLP/LPS performs is pushbutton reset control. The DSLP/LPS debounces the pushbutton input and guarantees an active reset pulse width of 50 ms minimum. The third function is a watchdog timer. The DSLP/LPS has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to timeout. The watchdog timer function can be set to operate on timeout settings of approximately 50 ms, 600 ms, and. seconds. OPERATION - POWER MONITOR The DSLP/LPS detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When falls below a preset level as defined by, the comparator outputs the signals and. When is connected to ground, the and signals become active as falls below.75 volts. When is connected to, the and signals become active as falls below.5 volts. The and are excellent control signals for a microprocessor, as processing is stopped at the last possible moments of valid. On power-up, and are kept active for a minimum of 50 ms to allow the power supply and processor to stabilize. OPERATION - PUSHBUTTON RESET The DSLP/LPS provides an input pin for direct connection to a pushbutton (Figure ). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that and signals of at least 50 ms minimum are generated. The 50 ms delay starts as the pushbutton reset input is released from low level. OPERATION - WATCHDOG TIMER The watchdog timer function forces and signals to the active state when the input is not stimulated for a predetermined time period. The time period is set by the input to be typically 50 ms with connected to ground, 600 ms with left unconnected, and. seconds with connected to. The watchdog timer starts timing out from the set time period as soon as and are inactive. If a high-to-low transition occurs on the input pin prior to timeout, the watchdog timer is reset and begins to timeout again. If the watchdog timer is allowed to timeout, then the and signals are driven to the active state for 50 ms minimum. The input can be derived from microprocessor address signals, data signals, and/or control signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. To guarantee that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum shown in Table. A typical circuit example is shown in Figure. of 7
MICROMONITOR BLOCK DIAGRAM DSLP/LPS PUSHBUTTON RESET Figure WATCHDOG TIMER Figure of 7
TIMING DIAGRAM: PUSHBUTTON RESET Figure DSLP/LPS TIMING DIAGRAM: ROBE INPUT Figure WATCHDOG TIME-OUTS Table TIME-OUT MIN TYP MAX 6.5 ms 50 ms 50 ms Float 50 ms 600 ms 000 ms 500 ms 00 ms 000 ms of 7
TIMING DIAGRAM: POWER-DOWN Figure 5 DSLP/LPS TIMING DIAGRAM: POWER-UP Figure 6 5 of 7
ABSOLUTE MAXIMUM RATINGS* Voltage on Pin Relative to Ground -0.5V to +7.0V Voltage on I/O Relative to Ground -0.5V to + 0.5V Operating Temperature 0 C to 70 C Operating Temperature (Industrial Version) -0 C to +85 C Storage Temperature -55 C to +5 C Soldering Temperature 60 C for 0 seconds DSLP/LPS * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0 C to 70 C) Supply Voltage.5 5.0 5.5 V and PB Input High Level V IH.0 +0. V and PB Input Low Level V IL -0. +0.8 V DC ELECTRICAL CHARACTERIICS (0 C to 70 C; =.5 to 5.5V) Input Leakage I IL -.0 +.0 µa Output Current @.V I OH -8-0 ma 5 Output Current @ 0.V I OL 0 ma Low Level @ V OL 0. V Output Voltage @ -500 ua V OH -0.5V -0.V V, 7 Output Current (CMOS) I CC 50 µa Operating Current (TTL) I CC 00 500 µa 8 Trip Point (=) TP.50.6.7 V Trip Point (= ) TP.5.7.9 V CAPACITAE (t A =5 C) Input Capacitance C IN 5 pf Output Capacitance C OUT 7 pf 6 of 7
DSLP/LPS AC ELECTRICAL CHARACTERIICS (0 C to 70 C; =5V ± 0%) PB = V IL t PB 0 ms RESET Active Time t 50 60 000 ms Pulse Width t 0 ns 6, 9 Fail Detect to and t RPD 50 75 µs Slew Rate.75V to.5v t F 00 µs Detect to and Inactive t RPU 50 60 000 ms Slew Rate.5V to.75v t R 0 ns PB Stable Low to and t PDLY 0 ms NOTES:. All voltages referenced to ground.. Measured with outputs open and and PB within 0.5V of supply rails.. PB is internally pulled up to with an internal impedance of 0k typical.. t R = 5 µs. 5. is an open-drain output. 6. Must not exceed t minimum. See Table. 7. remains within 0.5V of on power-down until drops below.0v. remains within 0.5V of on power-down until drops below.0v. 8. Measured with outputs open and and PB at TTL levels. 9. Watchdog can not be disabled. It must be strobed to avoid resets. MARKING INFORMATION: 8-pin DIP - DSL 6-pin SOIC - DSL 8-pin SOIC - DSL 8-pin µ-sop - 7 of 7