Towards Integrated AlGaN/GaN Based X-Band High-Power Amplifiers

Towards Integrated AlGaN/GaN Based X-Band High-Power Amplifiers PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de Rector Magnificus, prof.dr. R.A. van Santen, voor een commissie aangewezen door het College voor Promoties in het openbaar te verdedigen op maandag 5 juli 2004 om 16.00 uur door Bart Jacobs geboren te Valkenswaard

Dit proefschrift is goedgekeurd door de promotoren: prof.dr.-ing. L.M.F. Kaufmann en prof.dr.-ing. E. Kohn copromotor: dr. F. Karouta Druk: Universiteitsdrukkerij Technische Universiteit Eindhoven Ontwerp omslag: Paul Verspaget CIP-DATA LIBRARY TECHNISCHE UNIVERSITEIT EINDHOVEN Jacobs, Bart Towards integrated AlGaN/GaN based X-band high-power amplifiers / by Bart Jacobs. - Eindhoven : Technische Universiteit Eindhoven, 2004. - Proefschrift. - ISBN 90-386-1593-0 NUR 959 Trefw.: galliumnitridehalfgeleiders / veldeffecttransistoren / passieve elektronische componenten / 3-5 verbindingen. Subject headings: wide band gap semiconductors / high electron mobility transistors / coplanar waveguides / III-V semiconductors.

Aan mijn ouders

Contents 1 Introduction 1 1.1 Advantages of the Gallium Nitride Material System............. 1 1.2 Applications................................... 1 1.3 Class A Amplifier Example........................... 4 1.4 Objectives and Outline of this Thesis..................... 7 2 The Gallium Nitride Material System 11 2.1 Crystal Structure and Material Properties.................. 11 2.2 Material Growth................................ 12 2.2.1 Substrates................................ 14 2.3 Polarization Effects............................... 16 2.3.1 Undoped AlGaN/GaN HEMT Structures............... 17 2.4 Summary.................................... 18 3 Reactive Ion Etching of GaN-Based Materials 21 3.1 Introduction................................... 21 3.2 Reactive Ion Etching Setup and Working Principles............. 21 3.3 Etching of GaN................................. 23 3.3.1 Description of Plasma Behavior Based on the DC Bias....... 25 3.4 Etching of AlGaN................................ 27 4 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures 31 4.1 Introduction................................... 31 4.2 Metal-Semiconductor Contacts......................... 32 4.2.1 Fermi Level Pinning.......................... 33 4.2.2 Barrier Formation............................ 33 4.2.3 Metal-Induced Gap States....................... 36 4.2.4 Origin of the 2DEG in AlGaN/GaN Structures........... 37 4.2.5 Experimental Approach........................ 40 4.3 Ohmic Contacts................................. 41 4.3.1 Metallization Scheme and Epitaxial Structure............ 41 4.3.2 The Transfer Length Method..................... 43 4.3.3 Optimization of the Ohmic Contact.................. 46 4.3.4 Measurement Accuracy, Reproducibility, Line Definition and Morphology................................. 48 i

ii CONTENTS 4.3.5 Concluding Remarks.......................... 50 4.4 Schottky Contacts on AlGaN/GaN FET Structures............. 50 4.4.1 Schottky Metallization......................... 50 4.4.2 Wafer Description and Schottky Layout................ 51 4.4.3 Reference Tests............................. 52 4.4.4 Forward and Reverse Characteristics................. 53 4.4.5 Optimization of Pre-Metallization Treatments............ 55 4.4.6 Discussion................................ 58 5 AlGaN/GaN High Electron Mobility Transistors 61 5.1 Introduction................................... 61 5.2 Principles of Operation of the HEMT..................... 62 5.2.1 Breakdown............................... 64 5.2.2 High-Frequency Operation....................... 66 5.3 Dispersion Phenomena in AlGaN/GaN HEMTs............... 68 5.3.1 Drain Lag and Buffer-Related Current Collapse........... 68 5.3.2 Surface-Related Gate Lag and Transient Response.......... 70 5.4 Optimization of AlGaN/GaN HEMT Processing............... 73 5.4.1 Process Optimization.......................... 74 5.5 Submicron HEMTs............................... 82 5.6 Summary and Discussion............................ 84 6 Passive Components on AlN 89 6.1 Introduction................................... 89 6.2 Matching Networks............................... 89 6.2.1 Quarter-Wavelength Transformer................... 90 6.2.2 L-type Matching Networks....................... 90 6.3 Microstrip and Coplanar Waveguide Technology............... 93 6.4 Substrate Material and Integration Technique................ 94 6.5 Constructing a CPW Library......................... 95 7 Coplanar Transmission Lines 99 7.1 Introduction................................... 99 7.2 Geometrical Quasi-TEM Range........................ 100 7.2.1 Quasi-TEM Approximation...................... 100 7.2.2 Non-CPW Modes............................ 100 7.3 Quasi-TEM Behavior of CPW Lines...................... 102 7.3.1 Transmission Line Model........................ 102 7.3.2 Conformal Mapping Results...................... 103 7.4 Assessment of the Quasi-TEM Range..................... 106 7.5 De-embedding Algorithm for CPW Lines................... 109 7.5.1 The Modified TRL Approach..................... 109 7.5.2 Summary of the Algorithm....................... 112 7.5.3 Comparison with Algorithm Based on Power Waves......... 113 7.6 Quasi-TEM Coplanar Lines on AlN...................... 114

CONTENTS iii 7.6.1 Scalable Model for the Line Capacitance............... 115 7.6.2 Scalable Model for the Propagation Constant............ 116 7.6.3 Influence of the Measurement Setup.................. 118 7.6.4 Scalable Model for the Adaptor.................... 119 7.6.5 Design Considerations......................... 119 7.7 Summary.................................... 121 8 Orthogonal Elements 123 8.1 Introduction................................... 123 8.2 Coplanar Bend................................. 125 8.2.1 Calibration............................... 125 8.2.2 Development of a Scalable Model................... 126 8.2.3 Properties of Coplanar Bends..................... 127 8.3 Coplanar T-junctions and Crosses....................... 128 8.3.1 Measurements on Multi-Ports..................... 128 8.3.2 Development of a Scalable Model................... 130 8.3.3 Results.................................. 132 8.4 Summary.................................... 133 9 Capacitors and Resistors 135 9.1 Introduction................................... 135 9.2 Tapers...................................... 137 9.3 Capacitors.................................... 139 9.3.1 Breakdown Mechanisms........................ 142 9.4 Resistors..................................... 143 9.4.1 Series Resistor.............................. 143 9.4.2 Resistor to Ground........................... 146 9.4.3 Model Accuracy and Discussion.................... 147 9.5 Summary.................................... 147 10 Application Examples: Matching Networks 149 10.1 Introduction................................... 149 10.2 Stub-Tuning................................... 149 10.3 35-50 Ohm Matching Network......................... 153 10.4 2-to-1 Combiner................................. 154 10.5 Conclusions................................... 157 11 Conclusions 159 11.1 HEMTs on AlGaN/GaN Heterostructures.................. 159 11.2 Passive Components on AlN.......................... 161 11.3 Concluding Remarks.............................. 162 A Waveguide Circuit Theory 163 A.1 Introduction................................... 163 A.2 Waveguide Voltage, Current and Characteristic Impedance......... 164 A.3 The Scattering Matrix............................. 166

iv CONTENTS A.3.1 Travelling Waves............................ 166 A.3.2 Power Waves.............................. 167 A.4 The Transmission Line Model......................... 168 B Processing of CPW Elements on AlN 171 B.1 Properties of Ceramic AlN........................... 171 B.2 Process Flow.................................. 171 C Scalable Models 175 C.1 Functions for the Adaptor........................... 175 C.2 Functions for the Bend............................. 175 C.3 Functions for the Taper............................. 175 C.4 Functions for the Capacitor.......................... 175 C.5 Functions for the Resistor........................... 176 C.6 Finding a Suitable Multi-Variable Function.................. 177 C.6.1 Functions for T-junctions and Crosses................ 177 List of Symbols 181 List of Acronyms 187 Summary 191 Samenvatting 193 Dankwoord 195 Curriculum Vitae 196

Chapter 1 Introduction 1.1 Advantages of the Gallium Nitride Material System For a new semiconductor material system to become successful, it must have clear advantages over current solutions. Often the new material system must outperform other materials, enable new applications, or promise significant cost reductions. Table 1.1 shows some important properties for the most common semiconductors today (Si, gallium arsenide (GaAs) and indium phosphide (InP)) and the recently emerging wide bandgap semiconductors (WBGS) silicon carbide (SiC) and gallium nitride (GaN). For electronic applications, the added value of WBGS can be found in the combination of a high breakdown voltage with a high electron velocity. This promises the realization of high-frequency, high-power applications that cannot be realized in the other material systems. Another advantage is related to the bandgap itself. A wide bandgap implicates strong bindings in the material making it less susceptible to chemicals and temperature variations. Devices made using these materials can therefore be used in harsh environments. In addition, WBGS can be used to fabricate light emitting devices in the blue to ultraviolet range. Clearly WBGS have advantages, but applications must be found that commercially justify the development of these materials into mature technologies. Some of these applications will be discussed in the next section. 1.2 Applications Almost all of the early research done on WBGS was directed towards optoelectronic applications. This was due to the fact that blue was the only color missing on the commercial light emitting diode (LED) market. Before GaN became available, SiC was used but its indirect bandgap resulted in rather poor efficiencies. Using the indium gallium aluminum nitride (InGaAlN) alloy system, highly efficient LEDs with wavelengths ranging from ultraviolet to blue/green can be realized. GaN-based LEDs can be used in conjunction with yellow and orange LEDs, made using the aluminum gallium indium phosphide (AlGaInP) material system, to realize full- 1

2 Introduction Table 1.1: Material properties for various semiconductors at 300K taken from [1] unless otherwise stated. Property Si GaAs InP 4H SiC GaN AlGaAs/ InAlAs/ AlGaN/ InGaAs InGaAs GaN Bandgap (ev) 1.1 1.42 1.35 3.26 3.44 Electron mobility 1500 8500 5400 700 900 (cm 2 /Vs) 10000 a 10000 b 2000 c Saturated (peak) 1.0 1.0 1.0 2.0 1.5 electron velocity (1.0) (2.1) (2.3) (2.0) (2.7) (x 10 7 cm/s) 2DEG sheet electron N.A. < 4 10 12 < 4 10 12 N.A. 2 10 13 density (cm 2 ) Critical breakdown 0.3 0.4 0.5 2.0 3.3 field (MV/cm) Therm. conductivity 1.5 0.5 0.7 4.5 2.1 [2] (W/cmK) 3.3 s a,b,c parameters for the corresponding heterostructures (aluminum gallium arsenide (AlGaAs)/indium gallium arsenide (InGaAs), indium aluminum arsenide (In- AlAs)/InGaAs and aluminum gallium nitride (AlGaN)/GaN), respectively. s thermal conductivity of semi-insulating SiC. color LED television. Numerous other applications are possible including traffic lighting, automotive lighting, and possibly general lighting. White LEDs have been made by coating the inside of the ultraviolet LED with phosphorus. Like with tubular lighting (TL), this will convert the ultraviolet photon into visible light. Blue lasers were first demonstrated by Nakamura et al. from Nichia at the end of 1995 [3]. These devices could result in a four- to eightfold increase in optical storage capacity. In 1998, the same authors demonstrated room-temperature continuous wave (CW) operation with a lifetime of more than 10000 hours [4]. GaN optoelectronic devices represent a multi-billion dollar market but several issues still remain. The most important ones are related to the p-type doping of the material and obtaining high reflectivity mirror cavities. Low p-type doping leads to high contact resistances and problems with current spreading [5]. This process is difficult because the dopants, mostly Mg, have a high activation energy. In addition, during growth interstitial hydrogen forms a Mg:H complex that passivates the acceptor. To activate the Mg, a hightemperature annealing step is needed. Most of the development of WBGS for electronic applications is directed towards high-power, high-frequency devices. Impressive power data on the order of 4-6W/mm at 4GHz for SiC metal-semiconductor field-effect transistors (MESFETs) and 10-11W/mm at 10GHz for AlGaN/GaN high electron mobility transistors (HEMTs) has been demon-

1.2 Applications 3 strated 1. GaN-based HEMTs usually show a better high-frequency performance because of the large mobilities that can be achieved in these structures. Both SiC and GaN offer the advantage of a high power density and good thermal properties, which can result in smaller power modules with fewer cooling requirements. In addition, if higher supply voltages are used, the input and output impedances become much higher, which reduces the complexity of the impedance matching problem. Recently, Cree has announced SiC MESFETs capable of producing 10W at 1dB compression at 2.4GHz with 13dB gain 2, while RF Micro Devices is sampling customer evaluation samples of their GaN-based HEMTs delivering 20W CW designed for universal mobile telecommunications system (UMTS) applications 3. For now, both companies are focused on the basestation market where they have to compete with the much cheaper but less performing (1W/mm) Si laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) technology. Realizing heterojunction bipolar transistors (HBTs) in GaN is difficult due to problems with achieving sufficiently high p-type doping in the base. Furthermore, the current in these devices flows in parallel with the dislocations in the material. This could cause difficulties with parallel conduction paths and reliability. A large portion of the research on WBGS for electronic applications is related to military industry. In the United States, the office of naval research (ONR) is actively involved in coordinating and financing research programs carried out at several universities. One of the target applications is a broadband amplifier for a multi-function radar [1]. Such a system would lower the total area of radar arrays to be exploited by adversaries, avoid possible electromagnetic conflict between different arrays and reduce overall costs. Another example is a low-noise amplifier (LNA), which is more robust due to the high breakdown field and good thermal conductivity. Noise figures of 0.6dB at 10GHz [7] and third-order-intermodulation intercept points 10dB higher than those of GaAs-based amplifiers [8] have been published. Another application area is high-temperature electronics. Usually, electronic systems that control and monitor high-temperature devices, like a jet engine, are located in cooler areas. This requires wiring between the electronic system and the sensors. If these systems could be placed in the high-temperature area, the total amount of wiring could be reduced. Degraded wiring has been the cause of major airplane tragedies like TWA flight 800 (near Long Island NY in 1996) and SwissAir flight 111 (near Nova Scotia in 1998) [9]. WBGS have to compete with low-power Si and Si on insulator (SoI) technologies that are used today for applications up to 300 0 C. The added value for WBGS therefore lies in the 300 600 0 C range. Issues for this market are related to reliable contact technology and the development of new packaging technologies that can withstand these temperatures and the associated oxidation. The total market for high-temperature electronics is expected to reach $ 900 million by the year 2008. It is difficult to predict the market share of WBGS compared to Si or SoI. Strategies Unlimited have estimated the total GaN electronic device market to reach $ 500 million by the end of this decade. However, economies of scale in the optoelectronic market, as well as improvements in material and substrate growth in this area, could accelerate industrialization of GaN-based electronic devices. 1 See [6] for a comparison between SiC and GaN devices. 2 Part number CRF-24010: Product sheet available on the internet. 3 Press release in compound semiconductor.net 3 march 2003.

C I @ 4 4 Introduction 8 @? 1 @ I? D A 1 @? 1 @ I = N 1 @? = @ E A 4 I F A + @? 8 E 8 @? 8 @ I = N 8 =? 8 E 1 @ I 1 =? 8 C I 8 8 F 8 @ I J E A J E A ) * Figure 1.1: Class A amplifier circuit (A) and current-voltage characteristics (B). 1.3 Class A Amplifier Example This thesis investigates the use of GaN for high-frequency, high-power amplifiers. To demonstrate the most important issues for these amplifiers we will use an example of a class A amplifier as illustrated in Figure 1.1. The gate of the FET, e.g. an AlGaN/GaN HEMT, is connected to an AC voltage source (V ac ) that has a DC offset of V in. In a first approximation, the FET acts as a voltage-controlled current source that can be described by the transconductance (g m ): g m = I ds V gs (1.1) where I ds is the drain-source current and V gs the gate-source voltage. Applying a sinusoidal voltage to the gate will result in a sinusoidal drain-source current (I ac ). The total drainsource current can then be written as: I ds (t) = I ac (t) + I dc (1.2) where I dc is the DC component corresponding to the operating bias point as indicated by the black dots in the figure. For the drain-source voltage (V ds ) we can write: V ds (t) = V dc I ac (t)r = V dc + I dc R I ds (t)r (1.3) where V dc is the drain-source DC operating bias point and R the load resistor. This relation describes the so-called loadline in the (I ds,v ds ) plane. Voltage and current move along this line in the time-domain 4. As illustrated in Figure 1.1, the maximum AC power that can be delivered to the load without waveform clipping equals: P out = (V ds,max V k )I ds,max 8 4 Any reactive elements in the FET itself are neglected. (1.4)

1.3 Class A Amplifier Example 5 where V k is the knee voltage and V ds,max and I ds,max are the maximum drain-source voltage and current, respectively. The power added efficiency (PAE) of the class A amplifier can be found using: P AE = P out P in = P out (1 1/G p ) (1.5) P dc P dc where G p is the power gain and P in and P dc are the AC and DC power supplied to FET, respectively. Assuming an infinite gain, we find: P AE = V ds,max V k 2(V ds,max + V k ) (1.6) Hence, for an ideal FET, which has V k = 0, the maximum efficiency equals 0.5 or 50%. Power added efficiency is a figure of merit that indicates how much of the supplied DC power is converted into AC power. Applying biasing strategies other than class A and/or using waveshaping techniques, efficiencies well above 50% can be obtained. As mentioned above, the gain of the amplifier also determines the PAE. Generally speaking, if the gain drops below 10dB, it has a deteriorating effect on efficiency. There are limits up to which frequency the amplifier can be used efficiently. Several figure of merits exist that describe the high-frequency limits of a device. Here we will use the cut-off frequency f t, which is the frequency at which the short-circuit current gain equals unity. For a HEMT, f t can be calculated using: f t g m (1.7) 2πC gs where C gs is the gate-source capacitance. Because it mainly depends on intrinsic material properties, this figure of merit is particularly useful to discriminate between different semiconductor technologies. This feature can be exposed by re-writing the drain-source current in saturation as: I ds = qσ 2 W g v sat (1.8) where qσ 2 is the charge density in the channel of the HEMT, v sat the saturated electron velocity, and W g the gate width. Applying Eq. (1.1) gives: C gs qσ 2 g m = W g v sat = W g v sat = v satc gs (1.9) V gs L g W g L g with L g the gate length. Inserting this in Eq. (1.7) yields: f t v sat 2πL g (1.10) Hence, f t is inversely proportional to L g /v sat, which is the transit time of electrons under the gate. The cut-off frequency and power gain are closely related. This will be demonstrated using the simple equivalent circuit illustrated in Figure 1.2. In this figure R in and R ds represent the input and output resistance of the device, respectively. The current (I) through the load resistor can be computed using: I = g m V gs R ds V ac R ds + R = g R ds m 1 + jωc gs R in R ds + R (1.11)

6 Introduction 8 =? 4 E 8 C I C 8 C I + C I 4 @ I 4 Figure 1.2: Simple equivalent circuit for a FET. where ω is the angular frequency. For high frequencies (ωc gs R in 1), the power delivered to the load is given by: P out = I 2 R 2 = V 2 ac 2R 2 in ( ) 2 ( ) 2 ft Rds R (1.12) f R ds + R where f is the frequency. At high frequencies the power delivered to the FET simply equals Vac/2R 2 in. The gain is therefore given by: G p = P out P in = 1 R in ( ) 2 ( ) 2 ft Rds R (1.13) f R ds + R This relation clearly illustrates the need for high f t devices. Based on the equations derived above, we can now understand why GaN-based HEMTs are indeed excellent candidates for high-power, high-frequency power amplifiers (see table 1.1): A high saturated electron velocity enables high f t devices and increases maximum current and therefore power. High electron sheet densities in the channel allow large current swings, again increasing power output. High breakdown fields allow large voltage swings, which also increase output power. The high electron mobility in the HEMT structure reduces the knee voltage, thereby increasing efficiency and power output. A wide bandgap increases the maximum thermal dissipation in the FET. In the discussion above we tacitly assumed that the impedance of the load can be chosen to optimize output power. Most radio frequency (RF) systems however, have a 50Ω input and output. We therefore need matching networks to transform the 50Ω to the desired impedance levels. These networks are usually a combination of inductors and capacitors. Especially at high frequencies, losses in these networks tend to increase due to the skin effect and substrate losses. As an example, consider a HEMT that has a power gain G p and dissipates P dc, which is connected to both an input and output matching network. The losses in these networks are

1.4 Objectives and Outline of this Thesis 7 P loss,in and P loss,out, respectively. The efficiency of this combined circuit can be computed from: P AE = P in (P loss,in G p P loss,out 1) P dc = P AE HEMT P loss,out G p 1/P loss,in G p 1 (1.14) where P AE HEMT is the efficiency of the HEMT alone: P AE HEMT = P inp loss,in G p P loss,in P in P dc (1.15) Losses in the output matching network are more critical for efficiency than losses in the input matching network due to the multiplication with G p. As a numerical example we take a HEMT with G p = 15dB and 50% efficiency. Losses in the output network as low as 0.5dB already reduce the total efficiency by 5%. 1.4 Objectives and Outline of this Thesis This project was started in 1998 as a cooperation between the Eindhoven University of Technology (TUE) and TNO Physics and Electronics Laboratory (TNO-FEL) in The Hague. The main drive for this research was to evaluate the use of AlGaN/GaN based HEMTs for X-band (8-12GHz) high-power amplifiers (HPAs) and, by developing a GaN technology base, get a clear understanding of the drawbacks and advantages involved with this new material system both from a theoretical and practical perspective. The main goal of this thesis is to develop the technologies needed in a high-power amplifier based on AlGaN/GaN HEMTs. As mentioned in the previous section, this not only involves the active devices, but also includes passive devices needed for impedance matching and biasing. These two different aspects of the power amplifier are reflected in the outline of this thesis. The first part of this thesis describes the development of a GaN technology base for the fabrication of AlGaN/GaN HEMTs. It consists of the following chapters: Chapter 2 presents a general overview of the GaN material system. We will look at how the material is grown, discuss the crystal structure and how this affects the properties of the AlGaN/GaN epitaxial layer structure. Mesa etching is needed to electrically isolate adjacent devices. Any damage introduced to the etched surface could lead to surface conduction and should therefore be avoided. A suitable etch process is described in chapter 3 Ohmic and Schottky contacts will be described in chapter 4. The drain and source of a FET are examples of ohmic contacts. The resistance of these contacts should be as low as possible. Gate contacts are Schottky contacts. Key parameters of these contacts are the reverse current and the breakdown voltage. The latter is related to the maximum voltage swing that can be applied to the FET.

8 REFERENCES In chapter 5 we will combine all the process steps described above into a HEMT process flow. As we will see, merely combining process steps results in devices that are useless at both DC and RF frequencies. First of all, the leakage currents are too high. Secondly, the devices show a severe amount of frequency dispersion, which means that the available current swing at high frequencies is considerably lower than at DC. To solve these problems the entire HEMT process needs to be optimized. The second part of this thesis describes the construction of a library with passive components. These devices are of the coplanar type using ceramic aluminum nitride (AlN) as substrate material. The reasons for choosing this technology instead of e.g. microstrip are given in Chapter 6. At the start of this project, there was little experience with coplanar elements nor was there a process flow available. As a result, all of the elements needed for impedance matching and interconnect in the power amplifier had to be fabricated, measured and modelled. It is important that all these elements have a high current carrying and thermal capability. Furthermore, they should be low-loss and dispersion-free, i.e. their behavior should not depend on frequency. The work on passive components is spread out over several chapters: Chapter 7 deals with coplanar transmission lines. Characteristic impedance and propagation constant are measured and compared to an analytical model based on conformal mapping. To connect different pieces of transmission line or to make turns in circuits, one can use bends, T-junctions or crosses. These elements are presented in chapter 8. To complete the component library, nickel chromium (NiCr) resistors and silicon nitride (SiNx) metal-insulator-metal capacitors (MIMCAPs) will be discussed in chapter 9. It is important to check the breakdown voltage of the SiNx used in the capacitors. This should be well above the maximum voltage occurring in the circuit. In chapter 10, the accuracy of the models for the various passive components will be demonstrated using two examples of a matching network. In chapter 11, we will briefly review the most important conclusions that can be drawn from the work described in this thesis and how these findings can be translated in future prospects for the GaN material system in electronic applications. References [1] R.T. Kemerlay, H.B. Wallace, and M.N. Yoder, Impact of Wide Bandgap Microwave Devices on DoD systems, Proceedings of the IEEE, vol. 90, no. 6, p. 1059, 2002. [2] L. Liu and J.H. Edgar, Substrates for Gallium Nitride Epitaxy, Material Science and Engineering Reports, vol. 37, no. 3, p. 61, 2002. [3] S. Nakamura, M. Senoh, S. Nagahama, N. Iwasa, T. Yamada, T. Matsushita, H. Kiyoku, and Y. Sugimoto, InGaN-Based Multi-Quantum-Well-Structure Laser Diodes, Japanese Journal of Applied Physics Letters, vol. 35 part2, no. 1B, p. L74, 1996.

REFERENCES 9 [4] S. Nakamura, M. Senoh, S. Nagahama, N. Iwasa, T. Yamada, T. Matsushita, H. Kiyoku, Y. Sugimoto, T. Kozaki, H. Umemoto, M. Sano, and K. Chocho, Continuous- Wave Operation of InGaN/GaN/AlGaN-Based Laser Diodes Grown on GaN Substrates, Applied Physics Letters, vol. 72, no. 16, p. 2014, 1998. [5] S.P. DenBaars, Gallium-Nitride-Based Materials for Blue to Ultraviolet Optoelectronic Devices, Proceedings of the IEEE, vol. 85, no. 11, p. 1740, 1997. [6] R.J. Trew, SiC and GaN Transistors- Is There One Winner for Microwave Power Applications?, Proceedings of the IEEE, vol. 90, no. 6, p. 1032, 2002. [7] N.X. Nguyen, M. Micovic, W.S. Wong, P. Hashimoto, P. Janke, D. Harvey, and C. Nguyen, Robust Low Microwave Noise GaN MODFET with 0.6dB Noise Figure at 10GHz, Electronics Letters, vol. 36, no. 5, p. 469, 2000. [8] T. Jenkins, L. Kehias, P. Parikh, Y.F. Wu, P. Chavarkar, M. Moore, and U. Mishra, Linearity of High Al-Content AlGaN/GaN HEMT s, Device Research Conference Digest, p. 201, 2001. [9] P.G. Neudeck, R.S. Okojie, and L.Y. Chen, High-Temperature Electronics- A Role for Wide Bandgap Semiconductors?, Proceedings of the IEEE, vol. 90, no. 6, p. 1065, 2002.

10 REFERENCES

Chapter 2 The Gallium Nitride Material System Several aspects make the GaN material system totally different from conventional semiconductors like Si or GaAs. First of all, there is the material growth itself, which is mostly heteroepitaxial. Because GaN substrates are not readily available, growth on different materials like sapphire or SiC is required. The lattice mismatch that exists between these materials and GaN results in dislocation densities on the order of 10 8-10 10 /cm 2. Despite these large densities, e.g. GaAs has typical dislocation densities of 10 2-10 4 /cm 2, excellent device performance has been achieved. A second difference is the large piezoelectric and spontaneous polarization fields that exist in this material system. At interfaces within the epitaxial structure, the polarization changes abruptly. According to Gauss law, this will give rise to electric fields. Electrons and holes present in the material will try to re-arrange themselves to cancel these fields. This property is used to achieve high sheet carrier densities in HEMT structures that are free of doping. This chapter presents a brief overview of the GaN material system. We will especially focuss on the two topics mentioned above for several reasons. First of all, the choice of substrate not only determines the properties of the HEMT, but it also influences integration possibilities. Secondly, a good description of the polarization effects is very important for understanding the operation of AlGaN/GaN HEMTs. 2.1 Crystal Structure and Material Properties Usually, GaN has a wurzite structure that consists of alternating biatomic closely-packed planes of Ga and N pairs stacked in an ABAB sequence, see Figure 2.1. Adjusting substrate and growth conditions can however result in metastable zincblende structures. Due to difficulties with the growth of these crystals, most device research is however done using wurzite crystals. Almost all GaN work is done on crystals grown along the c-axis ([0001] direction). Crystals with this orientation have the so-called Ga-face polarity, crystals grown in the [000 1] direction possess N-face polarity. The definition of polarity is related to the Ga-N 11

12 The Gallium Nitride Material System? = N E I / =? F = A? = Figure 2.1: GaN wurzite crystal structure (Ga-face polarity). bonds parallel to the c-axis. In Ga-face crystals, the Ga atom is below the N atom, for N-face crystals we have the opposite. This distinction is important because most GaN structures are grown on a foreign substrate. If we were to have pure GaN crystals, the polarity could be changed by flipping the crystal. In addition, crystals with different polarities also behave differently. For instance, N-face crystals have lower dislocation densities and can be etched chemically [1] whereas Ga-face crystals have smoother surfaces, have a lower background concentration and are chemically inert. Almost all HEMT structures are based on Ga-face crystals due to better electron transport properties [2]. For completeness, the most important material properties of GaN are given in table 2.1. 2.2 Material Growth The best substrate for GaN growth, is GaN itself. Conventional bulk material growth techniques from a melt, like Czochralski or Bridgman, are not possible due to the high melting point of 2573K [6]. Furthermore, to prevent decomposition, high N 2 pressures have to be applied (60kbar at the melting point) [6]. Still, two techniques have been developed that have produced crystals large enough for homoepitaxy: hydride vaporphase epitaxy (HVPE) and high-pressure growth. The best structural properties for GaN substrates have been achieved using the high nitrogen pressure solution growth (HNPSG) approach [7]. These substrates are made from a gallium melt saturated with 1 atomic percent nitrogen at temperatures up to 1700 0 C obtained by nitrogen pressures of 20kbar. Dislocation densities for these crystals can be as low as 10/cm 2 [8]. However, the high oxygen concentration in these crystals results in electron concentrations on the order of 10 19 /cm 3. Mg doping can be used to obtain semi-insulating properties [8]. To date, crystals are about 1cm 2 but due to the extreme conditions necessary for growth, it is difficult to scale them up to larger sizes. HVPE can be used to produce thick (> 300µm) free-standing epitaxial GaN layers. The basic mechanism is the reaction between gallium monochloride (GaCl) and ammonia (NH 3 ) at 900-1100 0 C to form GaN. The GaCl is formed within the reactor vessel by

2.2 Material Growth 13 Table 2.1: GaN material properties at 300K or otherwise stated [3]. electron mobility 900 cm 2 /Vs [4] saturated electron velocity 1.5 10 7 cm/s [5] hole mobility 13 cm 2 /Vs breakdown field 3.3 10 6 V/cm [4] thermal conductivity 2.1 W/cmK heat capacity 35.3 J/molK dielectric constant 9.5 electron mass 0.22 m 0 bandgap 3.44 ev melting point > 2573 K (at 60 kbar) lattice constants a 0 = a (300K) 0.3188 nm c 0 = c (300K) 0.5185 nm a a 0 /a 0 (1400K) 0.5749 c c 0 /c 0 (1400K) 0.5032 flowing hydrochloric acid (HCl) gas over liquid Ga. The growth rates for this process are on the order of 100µm/hr, which is comparable to the high-pressure process. HVPE is typically done using foreign substrates like sapphire, Si, GaAs or SiC, which can be removed after growth. Typical dislocation densities that can be obtained using this technique are therefore higher than the homoepitaxial high-pressure process (10 6 /cm 2 [9]). However, it gives a lower unintentional n-type doping (typically on the order of 10 16 /cm 3 ) and the quality of the film improves with thickness [10]. Furthermore, the grown GaN substrate can be used as seed material in subsequent growth runs. Semiinsulating behavior can be obtained by Zn doping. Although both techniques are promising, GaN substrates are not readily commercially available. Most of the work on GaN is therefore conducted on heteroepitaxial material. This approach poses two problems, notably the mismatch in crystal symmetry and the mismatch in lattice constants between GaN and the substrate. The general approach is to use a thin (10-100nm) AlN or GaN nucleation layer 1 grown at a low temperature (400-600 0 C), which forms a transition between the substrate and the actual GaN film. By optimizing the growth parameters for this layer, e.g. growth temperature and thickness, high-quality films can be obtained. Treating the substrate prior to growth, e.g. nitridation of sapphire substrates, also influences the final quality of the GaN films. Metal-organic vapor-phase epitaxy (MOVPE) and molecular beam epitaxy (MBE) are the common methods used for GaN heteroepitaxy. Trimethylaluminum, trimethylgallium, and ammonia are the precursors for the MOVPE growth of Al x Ga 1 x N. Both hydrogen and nitrogen can be used as a carrier gas. The deposition temperature varies between 1 This layer is sometimes called the buffer layer. We will use the term nucleation layer to differentiate between this layer and the undoped GaN layer present in HEMT structures.

14 The Gallium Nitride Material System Table 2.2: Properties of various substrates used for GaN heteroepitaxy at room temperature taken from [3] unless otherwise indicated. Data for GaN is included for reference. Property GaN AlN Si 6H-SiC Sapphire Crystal symmetry wurz. wurz. cubic hex. hex. Lattice constants a 0 = a (300K) (nm) 0.3188 0.3111 0.5431 0.3081 0.4765 c 0 = c (300K) (nm) 0.5185 0.4980 N.A. 1.5117 1.2982 Lattice constants a (1400K) (nm) 0.5021 0.5106 0.7601 0.4553 0.8720 c (1400K) (nm) 0.7794 0.7644 N.A. 2.2640 2.4562 Thermal conductivity (W/cmK) 2.1 3-3.4 [11] 1.5 [4] 3.8 0.23 Lattice mismatch with GaN(%) 0 2.4 17 3.4 13.9 1000 and 1200 0 C, which is considerably larger than for MBE (600 to 800 0 C). In MBE, a solid source is used for Ga, while RF or electron cyclotron resonance (ECR) plasma sources are used to create atomic nitrogen. MOVPE and MBE show comparable growth rates of about 1µm/hr. 2.2.1 Substrates Table 2.2 presents some properties for the substrates that are most frequently used for heteroepitaxy: sapphire, SiC, Si and AlN. Each of these substrates will be discussed next. Sapphire Sapphire, single-crystal aluminum oxide, is the most frequently used substrate for the growth of GaN. Like Si, it can be grown using the Czochralski method. Sapphire is electrically isolating but has a poor thermal conductivity, which limits the power handling capability of devices. Furthermore, it has a large lattice mismatch with GaN resulting in high dislocation densities (10 10 /cm 2 ) in the epitaxial film [12]. Usually, GaN is grown on the c-plane of sapphire. This results in c-plane oriented films but with the [0001] plane of GaN rotated by 30 0 with respect to the sapphire. This rotation reduces the lattice mismatch from 30% to 13.9%. Due to this rotation, the cleavage planes of both materials are not aligned. Obtaining smooth cleaved surfaces, e.g. needed for laser fabrication, is therefore very difficult. Due to the large lattice mismatch at growth temperature, GaN films cannot be grown strained to lattice match the sapphire. One would expect the film to deposit fully relaxed. Because the thermal expansion coefficients of sapphire are larger than those of GaN, compressive strain is induced upon cooling down. Usually, a compressive strain of 0.7GPa

2.2 Material Growth 15 remains at room temperature for films of 1-3µm thick [3]. Both doping and nucleation layer thickness are known to influence the stress. Sapphire is a non-polar substrate. Films deposited by MOVPE on c-plane sapphire are normally Ga-face regardless of the nucleation layer. With MBE the polarity can be chosen. An AlN nucleation layer will give Ga-face polarity whereas a GaN layer will result in N-face polarity. However, without a proper nucleation layer and/or substrate treatment, epitaxial films of mixed polarity may be deposited. For the work described in this thesis, MOVPE-grown Ga-face epitaxial structures have been used. SiC There are over 250 different polytypes of SiC. These polytypes reflect one-dimensional variations of the stacking sequence of closely-packed biatomic planes. For epitaxial growth of GaN, the 4H and 6H polytypes are commonly used. H stands for hexagonal crystal symmetry and the numbers refer to the number of layers of Si and C atoms before the atomic arrangement repeats. SiC is mostly grown using sublimation techniques like the modified Lely process [13]. SiC is a polar material and it is available in both polarities. Generally speaking, Siterminated SiC results in Ga-face polarity of the GaN film and C-terminated SiC gives N-face polarity [14]. Although the lattice mismatch is only 3%, it is still large enough to cause high dislocation densities on the order of 10 9 10 10 /cm 2, similar to GaN films grown on sapphire. Reasons for this are the roughness of the SiC substrates (1nm root mean square (RMS) compared to 0.1nm for sapphire) and the damage introduced during the polishing process, e.g. etching remnants and scratches. Different pre-treatments like wet/dry etching or annealing can be used to alleviate these effects. Furthermore, GaN and AlN nucleation layers are used to improve the quality of the epitaxial film. Because the thermal expansion coefficients of SiC are smaller than those of GaN, most epitaxial films will be under tensile strain. However, the amount of strain and sometimes even its sign, can strongly be influenced by adjusting the nucleation layer. One advantage of SiC is its high thermal conductivity. This makes SiC an excellent choice for high-power applications. It does however come with a high price. Semiinsulating, n- and p-type substrates are available. Si The reasons for trying Si as a substrate are obvious. Si substrates are cheap, have a high degree in crystal perfection and are available in very large sizes. It also introduces the possibility of combining GaN and Si devices on the same wafer. However, the lattice and thermal mismatch is very large. To date, decent performance can be obtained with devices on Si(1 1 1) [15] but more work is needed to approach the results obtained on sapphire or SiC. If the growth problems can be overcome, Si is a very attractive candidate. Due to its moderate thermal conductivity of 1.5W/cmK, devices on Si will not likely achieve the same power densities as devices on SiC. Furthermore, obtaining low background doping in Si substrates is rather difficult. However, the low costs of using Si substrates may prevail.

16 The Gallium Nitride Material System AlN From all of the substrates mentioned sofar, AlN is the best match to GaN. Not only do the lattice constants match at room temperature, they are also matched at the growth temperature of GaN. Epitaxial layers of GaN grown on AlN substrates have shown low defect densities on the order of 10 4 10 5 /cm 2, which is about four orders of magnitude smaller than layers grown on SiC [11]. In addition, the thermal conductivity of AlN approaches that of SiC making it an excellent substrate for power devices. Apart from being a prime candidate for GaN heteroepitaxy, AlN could be used for optoelectronic devices. Its bandgap of 6.2eV promises the development of deep-uv light sources. AlN is usually grown by sublimation techniques using 6H-SiC as a seed material or not using a seed at all (self-seeding). Due to the high temperatures involved (2300K) and the highly reactive Al species, designing a durable reactor is complicated. Cracking induced by the difference in thermal expansion coefficients between AlN and the SiC, or the crucible in case of self-seeding, can be significant [16]. A high-pressure approach, in which AlN is grown from a solution of atomic nitrogen in liquid aluminum, is also pursued [17]. Crystal-IS 2, an incubator of the Rensselaer Polytechnic Institute, is currently the only company industrializing the (sublimation) growth of bulk AlN. Substrates as large as 1cm 2 are available at the time of writing this thesis. Defect densities on the order of 500/cm 2 have been demonstrated. It needs no explanation that the availability of lowcost AlN substrates could accelerate the development of the III-nitride material system. However, obtaining a low background doping may prove to be difficult due to the high reactivity of aluminum with oxygen. 2.3 Polarization Effects Due to lack of crystal symmetry, the center points of the positive and negative charge in GaN films do not coincide. This gives rise to large polarization fields (P ) within the material. Polarization that exists in fully relaxed films (zero strain), is referred to as spontaneous polarization (P SP ), whereas polarization induced by strain is referred to as piezoelectric polarization (P P E ). Both polarization fields are parallel to the c-axis and are usually described as vectors pointing from the Ga towards the N atom. The piezoelectric polarization can be computed from [18]: ( ) ( ) c c 0 a a 0 P P E = e 33 ɛ z + e 31 (ɛ x + ɛ y ) = e 33 + 2e 31 (2.1) c 0 a 0 where a and c are the lattice constants of the strained layer, a 0 and c 0 the relaxed values for this layer (see Figure 2.1), e 33 and e 31 the piezoelectric constants of the material (see table 2.3), and ɛ i the strain in direction i with the z direction parallel to the c-axis. The strain within the c-plane is assumed isotropic (ɛ x = ɛ y ). The deformation in the c-plane is related to the change in lattice constant c 0 by the elasticity tensor. For GaN-based materials we have [18]: 2 See www.crystal-is.com. c c 0 c 0 = 2 C 13 C 33 a a 0 a 0 (2.2)

2.3 Polarization Effects 17 Wurzite AlN GaN P SP (C/m 2 ) -0.081-0.029 e 31 (C/m 2 ) -0.60-0.49 e 33 (C/m 2 ) 1.46 0.73 C 13 (GPa) [18] 108 103 C 33 (GPa) [18] 373 405 ) / = / = 5 = F F D E H A 2 5 2 2 5 2 2 2 -, - / G I 2 G I 2 G I 2! Table 2.3: Polarization and elasticity constants from [19] unless otherwise stated. Figure 2.2: The various polarization fields for Ga-face material. where C 13 and C 33 are the elasticity constants of the layer. Combining Eq. (2.1) with Eq. (2.2) gives: P P E = 2 a ( ) a 0 C 13 e 31 e 33 (2.3) a 0 C 33 2.3.1 Undoped AlGaN/GaN HEMT Structures Consider the undoped AlGaN/GaN heterostructure illustrated in Figure 2.2. The AlGaN layer is so thin that it adjusts its lattice to the underlying GaN layer. The polarization in the AlGaN layer will therefore contain a piezoelectric component 3. Both the piezoelectric and spontaneous polarization are negative, meaning that they point towards the substrate. The impact of these fields can be shown by Gauss law: ɛ s E = P + ρ (2.4) where ɛ s is the dielectric constant of the corresponding layer, E the electric field and ρ the net free charge, which is zero for an ideal undoped structure. This equation shows that a gradient in the polarization field is equivalent to free charge. At the different interfaces in the structure, the polarization fields change abruptly. For instance, if we look at the AlGaN/GaN interface, we can introduce an equivalent polarization charge carrier density (σ P 2 ) by using the integral form of Eq. (2.4): ɛ s E nda = P nda = A (Ptot,GaN P tot,algan ) = qaσ P 2 (2.5) where da is a surface element of the total integration surface (A), n the corresponding normal vector, q the elementary charge, and P tot = P SP + P P E the total amount of polarization. For charge neutrality, similar carrier densities must be introduced at the Air/AlGaN (σ P 1 ) and GaN/sapphire (σ P 3 ) interfaces, see Figure 2.2. To compute the values of these densities, Eq. (2.3) must be used in combination with the values for the spontaneous polarization. Figure 2.3 presents the results of these calculations as a 3 The reader might notice the absence of the piezoelectric component in the GaN layer, although it was stated in the previous section that residual stress is present after growth. This component is assumed to be included in the spontaneous polarization of the GaN layer.

18 The Gallium Nitride Material System Figure 2.3: Equivalent polarization charge carrier density at the three interfaces for a Ga-face AlGaN/GaN structure on sapphire as a function of Al content. Negative values correspond to negative charges. function of Al content. For these calculations, Vegard s law was used to calculate the lattice parameters and the polarization and elasticity constants needed in Eq. (2.3). As a result of the electric field setup by the equivalent polarization charges, electrons in the AlGaN will try to cancel this field by moving towards the AlGaN/GaN interface thereby forming a two-dimensional electron gas (2DEG). Even for undoped structures, high sheet carrier densities (10 13 /cm 2 ) have been achieved [18]. This is somewhat surprising as the entire structure is undoped. But as we will see in chapter 4, the electrons in the 2DEG may stem from interface states at the AlGaN surface [20]. Despite the advantages of using undoped structures, like increased breakdown voltage or reduced gate leakage, there are some drawbacks related to the trapping and de-trapping time constants of the surface states. These drawbacks will be discussed extensively in chapter 5. In chapter 4, it will be shown that the 2DEG concentration is an increasing function of AlGaN thickness. High sheet carrier densities can be obtained by choosing a high Al content (increase in conduction band discontinuity and piezoelectric polarization) and growing relatively thick AlGaN layers. However, one should be careful not to exceed the critical thickness. This will result in relaxation thereby lowering the piezoelectric field and sheet carrier concentration. Also, for high Al content, electron mobility will decrease due to increased surface roughness scattering [21]. For these reasons, the AlGaN thickness for most HEMT structures is between 20 and 30nm with an Al content ranging from 25-35%. 2.4 Summary GaN-based HEMTs offer the possibility to combine high voltages and currents at high frequencies. Despite this potential, early development in this material system was hampered by the unavailability of a suitable substrate. Currently, SiC, Si and sapphire are the most frequently used substrates for heteroepitaxy. Due to the lattice mismatch with these substrates, pure monocrystalline GaN films cannot be grown without the use of an intermediate layer. Although the defect densities obtained in these films are several or-

REFERENCES 19 ders of magnitude larger than those typically found in GaAs, excellent device results have been obtained. At the time of writing this thesis, the most impressive power densities are reported for AlGaN/GaN HEMTs on SiC. It is the high thermal conductivity of SiC that makes this material an excellent substrate for power devices. To avoid the high costs of SiC, much effort is being spent in developing Si as substrate material. The advantages of using Si include large wafer sizes and increased integration possibilities. Another substrate candidate is monocrystalline AlN. These crystals present a very low lattice mismatch to GaN and have a thermal conductivity similar to that of SiC. Furthermore, the very wide bandgap of this material presents new opportunities for optoelectronic devices. However, much like Si, it will be difficult to obtain semi-insulating material. Homoepitaxy on GaN substrates should offer the highest crystal quality possible. Commercial availability of these substrates is still limited, but this will most likely change in the future. Obtaining low background doping levels is crucial if these substrates are to be used in electronic devices. References [1] J.L. Weyher, P.D. Brown, A.R.A. Zauner, S. Müller, C.B. Boothroyd, D.T. Ford, P.R. Hageman, C.J. Humphreys, P.K. Larsen, I. Grzegory, and S. Porowski, Morphological and Structural Characteristics of Homoepitaxial GaN Grown by Metalorganic Chemical Vapour Deposition (MOCVD), Journal of Crystal Growth, vol. 204, no. 4, p. 419, 1999. [2] O. Ambacher, J. Smart, J.R. Shealy, N.G. Weimann, K. Chu, M. Murphy, W.J. Schaff, L.F. Eastman, R. Dimitrov, L. Wittmer, M. Stutzmann, W. Rieger, and J. Hilsenbeck, Two-Dimensional Electron Gases Induced by Spontaneous and Piezoelectric Polarization Charges in N- and Ga-face AlGaN/GaN Heterostructures, Journal of Applied Physics, vol. 85, no. 6, p. 3222, 1999. [3] L. Liu and J.H. Edgar, Substrates for Gallium Nitride Epitaxy, Material Science and Engineering Reports, vol. 37, no. 3, p. 61, 2002. [4] R.T. Kemerlay, H.B. Wallace, and M.N. Yoder, Impact of Wide Bandgap Microwave Devices on DoD systems, Proceedings of the IEEE, vol. 90, no. 6, p. 1059, 2002. [5] B. Gelmont, K. Kim, and M. Shur, Monte Carlo Simulation of Electron Transport in Gallium Nitride, Journal of Applied Physics, vol. 74, no. 3, p. 1818, 1993. [6] J. Karpinski, J. Jun, and S. Porowski, Equilibrium Pressure of N 2 over GaN and High Pressure Solution Growth of GaN, Journal of Crystal Growth, vol. 66, no. 1, p. 1, 1984. [7] S. Porowski, High Pressure Growth of GaN: New Prospects for Blue Lasers, Journal of Crystal Growth, vol. 166, no. 1, p. 583, 1996. [8] K. Saarinen, J. Nissilä, P. Hautojärvi, J. Likonen, T. Suski, I. Grzegory, B. Lucznik, and S. Porowski, The Influence of Mg Doping on the Formation of Ga Vacancies and Negative Ions in GaN Bulk Crystals, Applied Physics Letters, vol. 75, no. 16, p. 1276, 1999.

20 REFERENCES [9] P. Visconti, K.M. Jones, M.A. Reschchikov, F. Yun, R. Cingolani, H. Morkoç, S.S. Park, and K.Y. Lee, Characteristics of Free-Standing Hydride-Vapor-Phase- Epitaxy-Grown GaN with Very Low Defect Concentration, Applied Physics Letters, vol. 77, no. 23, p. 3743, 2000. [10] L. Chernyak, A. Osinky, G. Nootz, A. Schulte, J. Jasinski, M. Benamara, Z. Liliental- Weber, D.C. Look, and R.J. Molnar, Electron Beam and Optical Depth Profiling of Quasibulk GaN, Applied Physics Letters, vol. 77, no. 17, p. 2695, 2000. [11] X. Hu, J. Deng, N. Pala, R. Gaska, M.S. Shur, C.Q. Chen, J. Yang, G. Simin, M.A. Khan, J.C. Rojo, and L.J. Schowalter, AlGaN/GaN Heterostructure Field-Effect Transistors on Single-Crystal bulk AlN, Applied Physics Letters, vol. 82, no. 8, p. 1299, 2003. [12] F.A. Ponce, Group III Nitride Semiconductor Compounds, p. 123, Oxford University Press, 1998. [13] Yu.M. Tairov, and V.F. Tsvetkov, Investigation of Growth Processes of Ingots of Silicon Carbide Single Crystals, Journal of Crystal Growth, vol. 43, no. 2, p. 209, 1978. [14] E.S. Hellman, The Polarity of GaN: A Critical Review, MRS Internet Journal on Nitride Semiconductor Research, vol. 3, no. 11, 1998. [15] P. Javorka, A. Alam, M. Wolter, A. Fox, M. Marso, M. Heuken, H. Lüth, and P. Kordo s, AlGaN/GaN HEMTs on (111) Silicon Substrates, IEEE Electron Device Letters, vol. 23, no. 1, p. 4, 2002. [16] J.H. Edgar, L. Liu, B. Liu, D. Zhuang, J. Chaudhuri, M. Kuball, and S. Rajasingam, Bulk AlN Crystal Growth: Self-Seeding and Seeding on 6H-SiC Substrates, Journal of Crystal Growth, vol. 246, p. 187, 2002. [17] M. Bockowski, M. Wroblewski, B. Lucznik, and I. Grzegory, Crystal Growth of Aluminum Nitride under High Pressure of Nitrogen, Materials Science in Semiconductor Processing, vol. 4, p. 543, 2001. [18] O. Ambacher, B. Foutz, J. Smart, J.R. Shealy, N.G. Weimann, K. Chu, M. Murphy, A.J. Sierakowski, W.J. Schaff, R. Dimitrov, A. Mitchell, M. Stutzmann, and L.F. Eastmann, Two Dimensional Electron Gases Induced by Spontaneous and Piezoelectric Polarization in Undoped and Doped AlGaN/GaN Heterostructures, Journal of Applied Physics, vol. 87, no. 1, p. 334, 2000. [19] F. Bernardini, V. Fiorentini, and D. Vanderbilt, Spontaneous Polarization and Piezoelectric Constants of III-V Nitrides, Physics Review B, vol. 56, no. 16, p. 10024, 1997. [20] J.P. Ibbetson, P.T. Fini, K.D. Ness, S.P. DenBaars, J.S. Speck, and U.K. Mishra, Polarization Effects, Surface States, and the Source of Electrons in AlGaN/GaN Heterostructure Field Effect Transistors, Applied Physics Letters, vol. 77, no. 2, p. 250, 2000. [21] S. Keller, Y.F. Wu, G. Parish, N. Zhang, J.J. Xu, B.P. Keller, S.P. DenBaars, and U.K. Mishra, Gallium Nitride Based High Power Heterojunction Field Effect Transistors: Process Development and Present Status at UCSB, IEEE Transactions on Electron Devices, vol. 48, no. 3, p. 552, 2001.

Chapter 3 Reactive Ion Etching of GaN-Based Materials 3.1 Introduction Etching of semiconductor material is an essential part of device fabrication. It is used to electrically isolate devices by removing the conductive layer between them. Furthermore, etching can be used to improve device performance. An example is gate recessing in which the highly doped contact layer, used for obtaining low contact resistances, is removed prior to the deposition of the gate metal [1, 2]. Dry etching has also been used to improve ohmic contacts [3]. Due to the strong ionic bonds, GaN is resistant to most acids and bases. This makes wet-chemical etching very difficult [4]. Photochemical etching, in which an ultraviolet light source is used in combination with potassium hydroxide (KOH), provides reasonable etch rates but uniformity is poor due to the non-homogenous light distribution [5]. However, plasma etching techniques like reactive ion etching (RIE) [6], inductively coupled plasma (ICP) [7] and ECR [8] have shown suitable etch rates of 0.2µm/min, 0.6µm/min and 1.3µm/min, respectively, for etching GaN. In this chapter, we will discuss reactive ion etching of the AlGaN/GaN material system using a mixture of Ar, silicon tetrachloride (SiCl 4 ) and sulfur hexafluoride (SF 6 ). The main objective is to develop a low-damage smooth mesa etching process for use on AlGaN/GaN epitaxial HEMT structures. For effective isolation we have to etch through the AlGaN layer, which is typically 30nm, and part of the GaN layer. It is therefore obvious that both the etching of GaN and AlGaN have to be investigated. 3.2 Reactive Ion Etching Setup and Working Principles All etching experiments were done using an Oxford Plasma System 100 equipped with a load-lock. Figure 3.1 presents a schematic layout of this machine showing the RF (13.56MHz) driven electrode and the large grounded chamber, which acts as the other electrode. The samples are placed on a quartz plate, which is then transferred from 21

22 Reactive Ion Etching of GaN-Based Materials C H K @ A @ A J =? D = > A H L = L A B A A @ C = I I = F A F K F G K = H J F = J A E I K = J H A A? J H @ A A A? J H @ A? K F E C? = F =? E J H 4. C A A H = J H Figure 3.1: Oxford System 100 schematic layout. F = I = I D A = J D I D A = J D Figure 3.2: Parallel-plate geometry showing the plasma between two sheaths. the load-lock into the process chamber. The mass flow controllers of the individual feed gases determine the gas composition inside the chamber whereas a valve controls the overall pressure. A heater/chiller is attached to the RF electrode to maintain a constant temperature of the sample. We will use the parallel-plate geometry depicted in Figure 3.2 to explain the working principles of the etching process. First consider the case where a plasma is present between two grounded electrodes. These electrodes are subjected to collisions from both electrons and ions. Because the electrons are much more mobile, the electron flux will be higher than the ion flux resulting in a negatively charged surface. This charging will continue until an equilibrium has been established between both fluxes. The electrodes are surrounded by sheaths, a small (dark) region in which the electron density (n e ) is much lower than the positive-ion density (n + i ). The potential difference over this sheath, (V sh ), typically a few kt e (k is Boltzmann s constant and T e the electron temperature), causes a steady ion current (I i ) that is balanced by those electrons that can cross the potential barrier (I e ). Applying an RF voltage (V rf ) will increase the electron flux towards the electrodes. Figure 3.3A illustrates the RF voltage and electron current towards the driven electrode before an equilibrium has been established. Due to their large mass, ions cannot respond to the RF signal leaving only the electrons to charge the electrode. Again, an equilibrium is achieved between electron and ion current but now at a much higher time-averaged sheath voltage than for the grounded electrodes. The electron and ion currents and timeaveraged densities for this situation are illustrated in Figures 3.3B and C, respectively. The sheaths act like capacitors allowing displacement currents to flow that are much larger than the ion currents. In the bulk plasma, the electron densities are high enough to support a conduction current. Usually, the voltage drop in the bulk plasma can be neglected compared to the time-averaged sheath voltage. The time-averaged potential in the plasma is depicted in Figure 3.3D. For a symmetric layout, with both electrodes of equal size, the time-averaged sheath voltage is the same at both electrodes. For an asymmetric layout, like the Oxford System 100, the situation is different. Roughly speaking, the displacement current through both sheaths must be equal. The smaller electrode has a smaller capacitance, so its RF voltage drop must be higher. Because the time-averaged sheath voltage is proportional to the RF voltage over

A A 3.3 Etching of GaN 23 1 A ) E + 8 H B A J? D = H C E C J E A 8 H B * 8 I D I O A J H E?, 1 E 1 A? D = H C E C > = =? A J E = I O A J H E? 8 * 1 ) 5 Figure 3.3: RF voltage, electron current and ion current before (A) and after equilibrium (B); time-averaged electron and positive-ion densities within a symmetric plasma (C); time-averaged potential distribution in a symmetric and asymmetric system (D). the sheath [9], the smaller electrode must have a higher time-averaged sheath voltage. As a result, a DC potential difference exists between both electrodes, which is called the self-bias or DC bias (V BIAS ) 1, see Figure 3.3D. Because the grounded electrode is normally much larger than the driven electrode we can neglect the sheath voltage of the grounded electrode. The DC bias is therefore almost equal to the sheath voltage of the driven electrode. This bias is important because it determines the energy of the ions that bombard the sample. The influence of the DC bias on the etch rate depends on the nature of the etching process. Etching can be purely physical (sputtering), purely chemical or a combination of both (ion energy-driven etching). As the gallium nitride material system is chemically inert, a purely chemical etching process is very unlikely and ion bombardment will therefore always play an important role. We can however change the chemical component by choosing a suitable gas mixture. 3.3 Etching of GaN For the etching experiments in this work we have used a combination of Ar, SiCl 4 and SF 6. Chamber pressure, power and gas flows were varied with the temperature of the heater/chiller set to 20 0 C. All experiments were done on pieces belonging to the same 2 wafer that contained 2µm of intrinsic GaN on sapphire. For masking we used large blocks of SiNx (> 100µm 2 ), which were obtained using photolithography and a subsequent Ar:SF 6 etch. The etch rate was determined using a Tencor Alpha Step 100. The starting point of the etching experiments was a 40mTorr Ar:SiCl 4 plasma at 105W. Figure 3.4 presents the etch rate of this plasma as a function of RF power, together with two similar plasmas that contained small amounts of SF 6. As can be seen in the figure, 1 In the remainder of this report, we will use positive numbers for the (negative) V BIAS.

24 Reactive Ion Etching of GaN-Based Materials Figure 3.4: Influence of the SF 6 flow; pressure=40mtorr, Ar:SiCl 4 =10:10. Figure 3.5: Etch rate for different chamber pressures. Power=105W, Ar:SiCl 4 = 10:10. Figure 3.6: Etch rate as a function of SF 6 flow. Power=105W, Ar:SiCl 4 =10:10, pressure=40mtorr. Figure 3.7: Etch rate for different SiCl 4 and Ar flows. SF 6 =3sccm, power=105w, pressure=40mtorr. addition of SF 6 dramatically increases the etch rate. This is probably related to the fact that instead of a N-Cl bond, a N-F bond can be formed, which is a more volatile reaction product 2. It is therefore assumed that the removal of the N-Cl containing species limits the etch rate in a pure Ar:SiCl 4 plasma. Figure 3.5 illustrates the etch rate for the same plasmas as a function of pressure. Despite differences in gas composition, the plasmas show the same decreasing trend. Further investigations into the role of SF 6, illustrated in Figure 3.6, show that an optimum exists at 3sccm. The change in DC bias over this flow range alone cannot explain the reduction in etch rate for flow rates higher than 3sccm. A possible explanation could be that the density of SF 6 -related ions has decreased. Using the best etching process derived in the previous steps, the influence of the Ar and SiCl 4 flow was determined, see Figure 3.7. Changing the SiCl 4 flow shows a behavior 2 For comparison: The boiling points of NF 3 and NCl 3 are -127 0 C and 71 0 C, respectively.

3.3 Etching of GaN 25 Figure 3.8: SEM image of a SiCl 4 :Ar:SF 6 = 10:10:2 etch. Process settings: power=105w, pressure=40mtorr and t=5min. Figure 3.9: SEM image of a SiCl 4 :Ar:SF 6 = 10:10:0 etch. Process settings: power=105w, pressure=40mtorr and t=10min. similar to that when changing the SF 6 flow, in both cases an optimum can be found. Increasing the Ar flow causes the etch rate to increase. Scanning electron microscopy (SEM) was used to investigate the surface morphology after etching. Figures 3.8 and 3.9 demonstrate the smoothness of the etched surface for an Ar:SiCl 4 :SF 6 and Ar:SiCl 4 plasma, respectively. In both cases, the etching process reduces the surface roughness. Atomic force microscopy (AFM) measurements on etched GaN single-crystals have demonstrated the possible use of the Ar:SiCl 4 :SF 6 etching process to improve homoepitaxial growth [10]. 3.3.1 Description of Plasma Behavior Based on the DC Bias In the discussion above we merely stated the etching results in terms of etch rate, we did not discuss the properties of the plasma itself. However, knowing properties like ion density and electron temperature allows us to build a qualitative picture of the actual process. Unfortunately, no characterization tools were available for analysis of the plasma. We will therefore try to explain the properties of the plasma using the DC bias, which in a first approximation is related to the dissipated power (P d ) by: P d = V BIAS I i = V BIAS qn + i A e u b = V BIAS qn + i A e kte M (3.1) where A e is the surface of the driven electrode, n + i the density of the positive ions at the sheath-bulk plasma interface, M the mass of these ions, and u b the Bohm velocity. As will be shown next, this relation can be used to provide insight in the properties of the plasma.

26 Reactive Ion Etching of GaN-Based Materials Figure 3.10: Influence of the SiCl 4 /Ar ratio on the DC bias. SF 6 =0sccm, pressure=40mtorr and power=105w. We start by investigating Figure 3.10, which presents the DC bias in an Ar:SiCl 4 plasma with varying composition at constant RF power and pressure. The decrease in DC bias with SiCl 4 flow is related to the increasing electronegativity of the plasma. SiCl 4 and SF 6 to a larger extent, are electronegative species, i.e. they attract low-energy electrons to form negative ions. Due to the loss of low-energy electrons, the average electron energy, which can be described by the electron temperature, increases but the electron density decreases. Despite this decrease, the positive-ion density could increase because it depends exponentially on the electron temperature [11]. Looking back at Eq. (3.1), we can confirm that this indeed results in a lowering of the DC bias. This also explains the drop in DC bias in Figure 3.6. Increasing chamber pressure results in more electron-atom collisions. For electropositive plasmas this leads to a higher positive-ion density and due to charge neutrality, a higher electron density. Electron temperature will most likely decrease. For electronegative plasmas, more electrons are attached to the electronegative species resulting in an increase in negative ions and electron temperature as described before. Similarly, the latter will cause the positive-ion density to increase. We can conclude that for both electropositive and electronegative plasmas the DC bias will decrease with pressure as was illustrated in Figure 3.5. Increasing power allows for higher ionization rates resulting in increasing positive-ion and electron densities for both electropositive and electronegative plasmas. The increase in electron density combined with a higher RF voltage results in a higher electron flux. The DC bias has to rise to reach a new equilibrium between ion and electron current. According to Eq. (3.1), the decreasing DC bias in Figure 3.6 must be accompanied by an increasing n + i kte product. To correlate the optimum found for the etch rate in this figure to this product and the DC bias alone would be an oversimplification of the problem. For instance, n + i represents the overall positive-ion density, it does not give information on the species actually responsible for the etching. This particular concentration may drop due to a change in composition of the different species inside the plasma caused by an increase in electron temperature. Furthermore, it is possible that the kinetic energy of

3.4 Etching of AlGaN 27 Table 3.1: Etch rates of AlGaN/GaN for two mesa etch processes. The third process demonstrates the adverse effect of SF 6. The gas flows are in sccm, pressure in mtorr, power in Watt, DC bias (V BIAS ) in Volt and the etch rates for GaN and AlGaN in nm/min. gases flows pressure power V BIAS GaN AlGaN Ar:SiCl 4 10:10 40 105 350 25 20 Ar:SiCl 4 10:10 40 70 288 6 5 Ar:SiCl 4 :SF 6 10:10:3 40 105 322 120 12 the ions plays a role in the formation of the reaction product. To gain more insight into the etching process, which probably involves several species in different steps, (optical) characterization of the plasma is necessary. But even then, a full description of the process would be difficult to obtain [9]. For smooth etching, a high positive-ion density is required. To limit the damage introduced by the ion bombardment, this has to be accompanied by a low DC bias. According to the discussion above, this means that we must not use low-pressure plasmas at high powers. These two requirements also indicate the major drawback of RIE systems as opposed to other techniques like ECR or ICP, in that ion density and DC bias cannot be chosen independently [9]. A significant increase in ion density can only be achieved by increasing power, which in turn increases the DC bias. Therefore, a trade-off has to be made between etch rate, surface morphology and surface damage. 3.4 Etching of AlGaN To study the etching of AlGaN we have used pieces of various wafers that more or less had the same structure (from bottom to top): a sapphire substrate (0.35mm), a thin GaN nucleation layer ( 30nm), an undoped GaN layer (2µm) and an undoped AlGaN layer (20-30nm, Al content 30 percent). As described in the previous section, the addition of SF 6 to the Ar:SiCl 4 mixture greatly enhanced the etching process. However, when etching AlGaN this addition may cause the opposite effect. The fluorine in the plasma can react with Al causing the formation of a highly stable and non-volatile Al-F species. It is therefore expected that the fluorine-free Ar:SiCl 4 mixture will produce the best results. A problem with determining the etch rate of AlGaN is caused by the thickness of this layer, typically 30 nm, which approaches the roughness of the wafer itself. To circumvent this problem, the AlGaN layer was completely etched as well as a portion of the GaN layer. Using the total depth of the etch combined with the known etch rate of GaN for this process, the etch rate of AlGaN could be computed. Another problem is related to chamber conditioning. Both SiCl 4 and SF 6 are species known to exhibit memory effects. The chamber therefore needs to be properly conditioned before etching AlGaN to ensure that residual SF 6 has disappeared. Another option is to avoid the use of SF 6 altogether

28 REFERENCES Figure 3.11: Ohmic contacts and submicron gate over a 150nm mesa etched using a SiCl 4 :Ar plasma (70W). but this was not an option as the same machine was used for SiNx etching using an Ar:SF 6 plasma. Table 3.1 presents the data of two Ar:SiCl 4 processes used for etching mesas. Also included is a SF 6 containing plasma that demonstrates the dramatic reduction in AlGaN etch rate if fluorine containing species are present in the chamber 3. In fact, poor chamber conditioning can result in more than 50 percent reduction in etch rate of AlGaN. Therefore, prior to the actual etch, a dummy run without sample should be performed using the same parameters as the mesa etch process. The etch rate of GaN for the fluorine-free processes is somewhat higher than that of AlGaN. This trend corresponds to results published by Pearton et al. [12], who found etch rates of GaN twice that of AlN using an ECR boron trichloride (BCl 3 ):Ar plasma. Figure 3.11 illustrates the morphology of the etched surface using the 70W Ar:SiCl 4 process. Although it yields a better surface morphology than the 105W process, etch pits can be seen in the exposed GaN layer. Like in wet-chemical etching [13], these pits are probably related to dislocations. The 70W process will be used for etching mesas needed for the fabrication of HEMTs in chapter 5. However, surface morphology was not the only factor that determined which etch process to use. In the same chapter, we will see how electrical damage introduced by the plasma prohibited the use of high-power (> 70W) etching processes. References [1] V. Kumar, W. Lu, F.A. Khan, R. Schwindt, E. Piner, and I. Adesida, Recessed 0.25µm Gate AlGaN/GaN HEMTs on SiC with High Gate-Drain Breakdown Voltage Using ICP-RIE, Electronics Letters, vol. 37, no. 24, p. 1483, 2001. 3 The selectivity of the Ar:SiCl 4 :SF 6 plasma to etch GaN faster than AlGaN, which is about 10:1, could be used to develop a gate-recess technology.

REFERENCES 29 [2] D. Buttari, A Chini, G. Meneghesso, E. Zanoni, P. Chavarkar, R. Coffie, N.Q. Zhang, S. Heikman, L. Shen, H. Xing, C. Zheng, and U.K. Mishra, Systematic Characterization of Cl 2 Reactive Ion Etching for Gate Recessing in AlGaN/GaN HEMTs, IEEE Electron Device Letters, vol. 23, no. 3, p. 118, 2002. [3] D. Buttari, A Chini, G. Meneghesso, E. Zanoni, B. Moran, S. Heikman, N.Q. Zhang, L. Shen, R. Coffie, S.P. DenBaars, and U.K. Mishra, Systematic Characterization of Cl 2 Reactive Ion Etching for Improved Ohmics in AlGaN/GaN HEMTs, IEEE Electron Device Letters, vol. 23, no. 2, p. 76, 2002. [4] D.A. Stocker and E.F. Schubert, Crystallographic Wet Chemical Etching of GaN, Applied Physics Letters, vol. 73, no. 18, p. 2654, 1998. [5] M.S. Minsky, M. White, and E.L. Hu, Room-Temperature Photoenhanced Wet Etching of GaN, Applied Physics Letters, vol. 68, no. 11, p. 1531, 1996. [6] M.S. Feng. J.D. Guo, Y.M. Lu, and E.Y. Chang, Reactive Ion Etching of GaN with BCl 3 /SF 6 Plasmas, Materials, Chemistry and Physics, vol. 45, no. 1, p. 80, 1996. [7] R.J. Shul, G.B. McCellan, S.J. Pearton, C.R. Abernathy, C. Constantine, and C. Barratt, Comparison of Dry Etch Techniques for GaN, Electronics Letters, vol. 32, no. 15, p. 1408, 1996. [8] C.B. Vartuli, S.J. Pearton, J.W. Lee, J. Hong, J.D. Mackenzie, C.R. Abernathy, and S.J. Shul, ICl/Ar Electron Cyclotron Resonance Plasma Etching of III-V Nitrides, Applied Physics Letters, vol. 69, no. 10, p. 1426, 1996. [9] M.A. Lieberman and A.J. Lichtenberg, Principles of Plasma Discharges and Materials Processing. Wiley-Interscience, 1994. [10] F. Karouta, J.L. Weyher, B. Jacobs, G. Nowak, A. Presz, I. Grzegory, and L.M.F. Kaufmann, Final Polishing of Ga-polar GaN Substrates using Reactive Ion Etching, Journal of Electronic Materials, vol. 28, no. 12, p. 1448, 1999. [11] G.M.W. Kroessen Private communication, 2002. [12] S.J. Pearton, C.R. Abernathy, F. Ren, J.R. Lothian, P.W. Wisk, and A. Katz, Dry and Wet Etching Characteristics of InN, AlN, and GaN Deposited by Electron Cyclotron Resonance Metalorganic Molecular Beam Epitaxy, Journal of Vacuum Science and Technology A, vol. 11, no. 4, p. 1772, 1993. [13] T. Kozawa, T. Kachi, T. Ohwaki, Y. Taga, N. Koide, and M. Koike, Dislocation Etch Pits in GaN Epitaxial Layers Grown on Sapphire Substrates, Journal of the Electrochemical Society, vol. 143, no. 1, p. L17, 1996.

30 REFERENCES

Chapter 4 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures 4.1 Introduction Generally, there are two types of metal-semiconductor contacts, (rectifying) Schottky contacts and ohmic contacts. An example of a Schottky contact is the gate of a HEMT. The drain and source of these devices are ohmic contacts. Metal-semiconductor contacts are usually characterized by the barrier height, i.e. the energy difference between the metal Fermi level and the conduction band edge of the semiconductor at the surface. The design strategy to obtain decent ohmic or Schottky contacts is quite different. For ohmic contacts, the barrier height should be minimized to achieve a low-resistance connection, whereas for Schottky contacts, it should be maximized to get proper current rectification. To determine how a metal-semiconductor barrier is formed, we first need to know about the properties of the semiconductor itself. As we will see in section 4.2.1, the GaN material system behaves quite differently compared to more conventional semiconductors like Si or GaAs due to the high polarization fields that exist in these materials. Expressions for the barrier height as a function of bias, including the influence of surface states and polarization fields, will be derived in 4.2.2. We will also briefly review the metal-induced gap state theory, which presents a different view on how metalsemiconductor barriers are formed. According to this theory, the barrier height is determined by surface states, which are an inevitable consequence of the fact that at the boundaries of the semiconductor the periodicity of the crystal stops. These states, which have energy levels in the bandgap, are therefore present even if the surface is perfectly clean and non-reconstructed. The optimization of the ohmic and Schottky contacts, presented in sections 4.3 and 4.4, respectively, was done using AlGaN/GaN structures similar to those used for the fabrication of HEMTs in chapter 5. Although this choice provides the best information on how these contacts perform in a HEMT, it does have some important consequences for the way the barrier is formed, and how the results should be interpreted. Most of the theoretical relations developed for contacts on single-layer semiconductor material do not apply for materials containing heterojunctions. Section 4.2.4 therefore presents an 31

32 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures I 5 5. + I 2. +, -? I 2 - B M @ / = I / 5 = F F D E H A Figure 4.1: Energy band diagram for a GaN layer showing the presence and screening of the polarization charges. extension of these relations for AlGaN/GaN structures. These relations will clarify the origin of the 2DEG and will also help to understand gate lag, which is currently one of the most important factors that limits output power in AlGaN/GaN HEMTs. The target specifications for ohmic and Schottky contacts are quite different. For ohmic contacts, the resistance should be as low as possible. For HEMTs, too high a resistance could limit the maximum drain-source current. It also degrades the extrinsic transconductance of the HEMT as shown by: g m,extr g m 1 + g m R s (4.1) where g m,extr is the transconductance of the device including all parasitics and g m the intrinsic transconductance. Typical AlGaN/GaN HEMTs have an intrinsic transconductance of about 250mS/mm. If we allow a degradation of 10%, the source resistance should not exceed 0.44Ωmm. This requirement becomes more stringent for hightransconductance devices. It should be noted that achieving these results presents a major challenge for most institutes. Schottky contacts must have low reverse currents to avoid excess losses. In addition, they should be able to withstand the high reverse voltages that occur during device operation. A high breakdown voltage is crucial to achieve large voltage swings in power amplifiers. The work on Schottky contacts described in this chapter was aimed at the reduction of reverse currents. These currents consist of an intrinsic part, which is related to the barrier height, and an extrinsic part caused by non-idealities like defects in the material. The latter is usually described by a resistor parallel to the ideal diode. Although breakdown voltages were measured, it was not a parameter that was optimized. It has to be noted, that excessive reverse currents are mostly indicative of premature breakdown. They must never be a significant part of the maximum drain-source current. 4.2 Metal-Semiconductor Contacts Consider the band diagram of a semi-insulating (background n-type donor concentration=n D ) GaN layer illustrated in Figure 4.1. Following the analysis of Karrer et al. [1], we will assume that the electric field in the GaN bulk is zero. As discussed in chapter 2,

4.2 Metal-Semiconductor Contacts 33 large polarization fields exist within the GaN layer, which can be described by equivalent polarization charges that reside at the different interfaces within the structure. Looking at Figure 4.1, we can see two equivalent polarization charge densities (±qσ P ), one at each interface. These charges setup an electric field that attracts electrons in the GaN layer towards the GaN/sapphire interface. Values for σ P are on the order of 10 13 /cm 2, which means that in typical 2µm semi-insulating buffer layers (N d = 10 16 /cm 3 ) there are not enough electrons to completely shield this field. However, complete shielding can be obtained by electrons that were released from surface states. 4.2.1 Fermi Level Pinning Surface states can be the result of fabrication-induced non-idealities like surface contamination or defects caused by etching. Also, the growth process itself, lack of stoichiometry, and the abrupt change in crystal structure, can cause surface states. Regarding the behavior of these states, we make the following assumptions: Surface states are characterized by a charge neutrality level (Φ CNL ). States above/ below this point behave like acceptor/donor states, i.e. they are negatively/positively charged if they are occupied/empty. Another definition of the charge neutrality level is referenced to the conduction band edge at the surface: Φ CNL = E c Φ CNL. Occupation of these states is determined by the Fermi level (E f ). The density of states function (D s ) is constant and to determine the electron distribution over these states, a zero Kelvin approximation can be used. The latter means that states above/below the Fermi level are empty/filled. Using these assumptions we can calculate the surface charge density from: qσ SS = qd s (Φ CNL E f ) (4.2) where negative values correspond to negative charges. If the density of surface states becomes very large, the position of the Fermi level will be close to Φ CNL. In that case, the Fermi level is said to be pinned. Because we assumed that the electric field is zero in the GaN bulk, we must have complete shielding of the polarization charges. This is partly caused by the emptied positively charged surface states. At the air/gan interface, qσ P is shielded by the net positive charge density in the surface states (qσ SS ) and the ionized donor atoms in the adjacent depletion region (qn D w d, assuming complete ionization in the depletion region). At the GaN/sapphire interface, accumulated electrons ( qσ G ) shield the polarization charge density (qσ P ). Charge conservation dictates that some of these electrons (notably σ P N D w d ), originate from surface states. Next, we will see how these different charges influence barrier formation. 4.2.2 Barrier Formation Figure 4.2 presents the energy band diagram of a typical metal-gan contact under flatband conditions. The GaN is assumed to be semi-insulating and an interfacial layer of

N N 34 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures - L =? G, E - L =? G, E. I K H B =? A I J = J A I? I - L =?. I K H B =? A I J = J A I? I - L =?. *. + -?. *. + G 8 @ - B G 8 = - B - B G 8 = -? - L - B - L @ A J = I A E? @ K? J H @ A J = I A E? @ K? J H Figure 4.2: Energy band diagram for flatband conditions. Figure 4.3: Energy band diagram for an arbitrary applied bias V a. thickness δ is present between the metal and GaN together with interface states that have their energies inside the bandgap 1. The objective of this analysis is to find an expression for the barrier height (Φ B ) measured between the metal Fermi level (E fm ) and the conduction band edge (E c ) of the semiconductor at the surface. Under flat-band conditions, no net charge is stored in the bulk semiconductor. Because the contact as a whole is electrically neutral, the amount of charge stored in the semiconductor and the metal must be equal, but opposite in sign. Again, we will assume that the bulk material is field-free implicating full shielding of the polarization charges. Under flat-band conditions, charge neutrality gives: σ M + σ G = σ SS (4.3) where σ G = σ P again is the electron sheet density near the GaN/sapphire interface and σ M the electron sheet density in the metal. According to Figure 4.2, the flat-band barrier height (Φ 0 B) can be computed from 2 : Φ 0 B = Φ m q 0 i χ s (4.4) where Φ m is the metal workfunction, χ s the electron affinity of the semiconductor, and i 0 the voltage drop over the interfacial layer. Usually, the interfacial layer is thin enough to allow electron tunneling between the metal and the surface states. As a result, the occupation of these states is not determined by E f, like in Eq. (4.2), but by E fm [2]. This allows 0 i to be computed according to: 0 i = qδσ M ɛ int = qδ(σ SS σ P ) ɛ int = qδd s(φ 0 B Φ CNL) ɛ int 1 It is assumed that no surface states exist at the GaN/sapphire interface. 2 The superscript 0 indicates quantities under flat-band condition. qδσ P ɛ int (4.5)

4.2 Metal-Semiconductor Contacts 35 where ɛ int is the dielectric constant of the interfacial layer. Combining this with Eq. (4.4) gives: Φ 0 B = γ i (Φ m χ s ) + (1 γ i )Φ CNL + γ iq 2 δσ p ɛ int (4.6) where γ i = ɛ int /(ɛ int + q 2 δd s ). Applying a bias other than the flat-band bias, or even not applying a bias at all, will cause band bending as illustrated in Figure 4.3. The condition of charge neutrality now has to include the charge stored in the semiconductor. Assuming complete ionization we have: σ M + σ G = σ SS + N D w d (4.7) The charge stored in the semiconductor will cause an additional voltage drop over the interfacial layer. According to Eq. (4.4) and Figure 4.3, this increase equals the decrease in barrier height, i.e.: Φ B Φ 0 B = q 0 i q i (4.8) The last term on the right can be calculated using the electric field in the semiconductor at the surface (E max ) caused by the ionized donors in the semiconductor (compare with Eq. (4.5)): i = qδd s(φ B Φ CNL) ɛ int + δɛ se max ɛ int qδσ P ɛ int (4.9) where ɛ s is dielectric constant of the semiconductor. Substituting this in Eq. (4.8) gives: Φ B = Φ 0 B αe max (4.10) where α = qδɛ s /(ɛ int + q 2 δd s ). Hence, the barrier height is a decreasing function of the positive charge stored in the semiconductor. This charge can be computed from the diffusion voltage V d = 1/q(Φ B ξ) V a according to [3]: Combining with Eq. (4.10) yields: ( [ 2qND E max = V d kt ]) 1/2 (4.11) q ɛ s Φ B = Φ 0 B + Φ [ ( 1 2 Φ 1 Φ 0 B + Φ )] 1/2 1 4 qv a ξ kt (4.12) where Φ 1 = 2α 2 N D /ɛ s. The important consequence of this relation is that for reverse bias conditions (V a < 0), the barrier height is lowered resulting in higher reverse currents. If there are no surface states (D s = 0) and there is no interfacial layer (δ = 0), Eq. (4.12) reduces to the Schottky-Mott rule: Φ B = Φ 0 B = Φ m χ s (4.13) whereas if the density of surfaces states is infinitely large we have the Bardeen limit: Φ B = Φ 0 B = Φ CNL (4.14)

36 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures These two limits represent the cases in which the influence of the metal workfunction on the barrier height is maximal and minimal, respectively. Practical contacts will show intermediate behavior. According to Eq. (4.6), the barrier height depends on the polarization charge. This has been confirmed by measurements on N- and Ga-polar material [1, 4]. Pt contacts on Ga-polar material, for which σ P near the GaN/sapphire interface is positive, showed higher barrier heights than contacts on N-polar material, which has a negative σ P. Reconstruction of the Ga surface can however cause deviations from the theory outlined above [5]. A more fundamental interpretation of the origin of the interfacial layer and interface states is possible. It is based on the intrinsic states that are present in the bandgap even if the semiconductor is perfectly clean. This theory will be discussed next. 4.2.3 Metal-Induced Gap States Most of the semiconductor properties are calculated using the assumption that the potential is a function reflecting the periodicity of the crystal. Using Bloch s theorem, it can be shown that the solutions of the Schrödinger equation must be of the form: Ψ( r) = e i k r u( r) (4.15) where k is a real wavevector, r the position vector, and u a function with the same periodicity as the crystal. Solutions with complex wavevectors do not fulfill this condition and, assuming that the semiconductor extends into infinity, cannot be normalized. However, near the boundaries of the semiconductor, solutions can be found that decay exponentially in the semiconductor. They are derived from wavefunctions belonging to the bulk bands and this determines their character. Wavefunctions with energies above the so-called branch point are predominantly conduction band-like, which means that if these states are occupied they are negatively charged much like an acceptor state. Below the branch point these states act like donor states. These intrinsic states can also be described in terms of dangling bonds at the surface. Such a bond can accept an electron (acceptor-like) or release an electron (donor-like). If the vacuum is replaced by a metal, similar solutions can be found. For the energy region where the metal conduction band overlaps the bandgap of the semiconductor, wavefunctions of metal electrons penetrate the semiconductor where they decay exponentially. This results in a continuum of states, called metal-induced gap states (MIGS) [6, 7] with energies inside the bandgap. These states are related to the states for finite semiconductors mentioned above. The branch point of the MIGS is referred to as the charge neutrality level (Φ CNL ) as discussed in the previous section. Depositing metal on top of the semiconductor will cause a charge transfer between the MIGS and the metal. Essentially, a thin layer of thickness δ is formed at the surface that does not contain conduction electrons. This layer however, is thin enough to allow electron tunneling. As a result, we can use the analysis of the previous section. Mönch modified this theory by stating that the charge in the semiconductor can be neglected compared to the charge stored in the metal and MIGS, which is valid for most semiconductors [8]. This is the same as setting N D to zero in Eq. (4.12), i.e. Φ B = Φ 0 B. In

4.2 Metal-Semiconductor Contacts 37 another paper [9], he derives an expression for the semiconductor dielectric workfunction Φ sd = χ s + Φ CNL. For metals, it has been shown that the metal workfunction, the energy needed to free an electron, is proportional to the electronegativity X m of the metal [10]. Mönch assumes that a similar relation exists between Φ sd and the electronegativity of the semiconductor (X s ): Φ m = A X X m + B X (4.16) Φ sd = A X X s + B X (4.17) where A X equals 0.86eV/Miedema-unit and B X = 0.59eV. The Miedema scale for electronegativities is related to the Pauling scale according to X Miedema = 1.93 X P auling +0.87. The electronegativity of the semiconductor is computed using the geometric mean of the atomic values of its constituents. For example, a binary compound AB has an electronegativity of X AB = (X A X B ) 1/2. For most semiconductors, this procedure results in values close to 4.7 on the Miedema scale. Using the relations from above and neglecting the charge stored in the semiconductor we can write Eq. (4.6) as: Φ B = Φ CNL + S X (X m X s ) + γ iq 2 δσ p ɛ int (4.18) where S X = A X γ i in which γ i now contains D MIGS instead of D s. In [11] it is shown, using theoretical calculations of D MIGS, that the slope parameter (S X ) can be approximated by: A X /S X 1 0.1( hω p /E gap ) 4 (4.19) where E gap is the bandgap energy and hω p the energy of the valence-electron plasmon, which for most semiconductors approaches (16.5±0.5)eV [12]. The barrier heights on wide bandgap semiconductors, like GaN, should therefore be more sensitive to the workfunction of the applied metal than the barrier heights on Si or GaAs. This has been confirmed by experiments that showed slope parameters of 0.08 and 0.29eV/Miedema-unit for GaAs and GaN, respectively [8]. The advantage of the MIGS theory is that it can predict the barrier height for different metals and semiconductors because δ and D MIGS can be computed from first principles. This can however prove to be difficult because the surface can be reconstructed, i.e. changed its chemical composition compared to the bulk, or relaxed, i.e. changed its lattice parameters compared to the bulk. Nevertheless, this theory has been successfully used to describe the barrier height for various semiconductors [8]. Most of the theory outlined so far dealt with contacts on GaN layers. But, as mentioned in the introduction of this chapter, we will use AlGaN/GaN structures to optimize the Schottky and ohmic contacts. An important question is therefore how this choice affects the behavior of the metal-semiconductor contact. To answer this question, we will have to look at how the band diagram is shaped in these structures. 4.2.4 Origin of the 2DEG in AlGaN/GaN Structures Consider the band diagram corresponding to a Schottky contact on an undoped Al- GaN/GaN heterostructure as depicted in Figure 4.4. To analyze this structure we again

@ @ I 38 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures - L =? G, E I 5 5? I.. *. + G, = I 2 I 2! - B G 8 = -? I I /, -? I - B I 2 A J = ) / = / = A J = ) / = / = 5 = F F D E H A Figure 4.4: Band diagram representing a Schottky contact on AlGaN/GaN (left). The figure on the right displays the various charges in the system. assume that the GaN buffer layer is field-free and that there are no surface states at the GaN/sapphire interface. In this system there are three interfaces where the polarization changes. Like in section 4.2.1, we will use polarization charges, indicated by the arrows in Figure 4.4, to calculate the electric fields in the system. Because the structure is undoped, any electrons in the 2DEG most originate from surface states [13]. This situation resembles that of the GaN buffer discussed in section 4.2.1, where electrons were donated by the surface states to cancel the polarization fields. To derive an expression for the 2DEG concentration (σ 2 ) we will apply charge conservation: σ SS = σ M + σ 2 + σ G = σ M + σ 2 + σ P 3 σ P 1 = σ P 2 + σ P 3 (4.20) (4.21) Replacing σ G by σ P 3 is allowed because we assumed that the buffer layer is field-free. Looking at the band diagram in Figure 4.4 we find: qv a + Φ m = q i + χ s + q a + E c ζ(σ 2 ) (4.22) where E c is the conduction band discontinuity and V a the applied bias, which is negative in this case. The depth of the quantum well with respect to the Fermi level is described by ζ. To proceed, we must calculate i and a. For the latter we find: a = qd(σ P 2 σ 2 ) ɛ AlGaN (4.23) with d and ɛ AlGaN the thickness and dielectric constant of the AlGaN layer, respectively. To determine i, we will combine the following two equations to eliminate σ SS : σ SS = D s (Φ m q i χ s Φ CNL) (4.24)

4.2 Metal-Semiconductor Contacts 39 Solving for σ SS gives: i = i = qδ(σ SS σ 2 σ P 3 ) ɛ int (4.25) qδ ɛ int + q 2 δd s (D s [Φ m χ s Φ CNL] σ 2 σ P 3 ) (4.26) Substituting Eqs. (4.23) and (4.26) into Eq. (4.22) gives: ( qδ qσ 2 + qd ) q 2 δ = qv ɛ int + q 2 a Φ m + δd s ɛ int + q 2 δd s ɛ AlGaN (D s [Φ m χ s Φ CNL] σ P 3 ) + q2 dσ P 2 ɛ AlGaN + E c ζ(σ 2 ) (4.27) Normally, the term containing δ before the equal sign in Eq. (4.27) can be neglected. If we further assume that ζ remains constant, Eq. (4.27) reduces to: qσ 2 = qσ P 2 + ɛ AlGaN V a /d c 1 /d (4.28) with c 1 independent of d. A similar relationship was found by Ibbetson et. al [13]. It shows that the 2DEG concentration (without bias) is an increasing function of the AlGaN thickness with a theoretical limit of σ P 2. However, increasing the thickness beyond the critical thickness (typically 20-30nm for 30 percent Al) reduces the 2DEG due to material relaxation. Moreover, there is a critical thickness for which the 2DEG concentration equals zero. This thickness depends on the Al content (different polarization charges). Once again assuming that the bias dependency of ζ is negligible, we can compute the capacitance density of the Schottky contact using: C 2DEG = qσ 2 V a = 1/ [ δ ɛ int + q 2 δd s + d ɛ AlGaN ] (4.29) This capacitance can be thought of as a series connection of the interfacial layer and AlGaN layer capacitances, respectively. Usually the latter dominates. It has been shown that the density of surface states (D s ), the interfacial layer thickness (δ), and the charge neutrality point (Φ CNL), are important factors that determine barrier height and 2DEG concentration. It is therefore important that we know about the magnitude of these quantities. In [4], Rizzi et al. calculated δ/ɛ int = 0.2nm, Φ CNL = 1.1eV and D s = 5.43 10 13 cm 2 ev 1. Although these values were derived for GaN layers they provide a rough estimate. Using these values we can verify that the term containing δ left to the equal sign in Eq. (4.27) as well as the same term in Eq. (4.29) can indeed be neglected. Following the same analysis as in section 4.2.2, we can compute the zero-bias barrier height from: Φ B0 = γ i (Φ m χ s ) + (1 γ i )Φ CNL + q2 γ i δ ɛ int (σ P 3 + σ 2 ) (4.30) This indicates that the barrier height increases due to shielding of the polarization charges (σ P 2 and σ P 3 ) by electrons in the 2DEG and the electrons near the GaN/sapphire interface. A similar relationship was found in section 4.2.2.

40 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures Having established equations for the barrier height, we are left with the problem of how to determine it experimentally. The choice for using AlGaN/GaN structures enables us to optimize the metal-semiconductor contacts on the same material as we will fabricate the transistors. In the next section, it will be shown that it does however limit the possibilities to determine the barrier height from measurements. 4.2.5 Experimental Approach Several experimental techniques are available with which the barrier height and ideality factor can be determined from measurements: The current-voltage method. Generally, the diode current density for voltages V a > 3kT is written as: ln(j) = ln(j s ) + qv a (4.31) nkt where J s is the reverse saturation current density, T the temperature, and n the ideality factor. The ideality factor can be found using linear interpolation of Eq. (4.31). However, the presence of a large series resistance limits the range in which a linear relationship can be found. The intercept of Eq. (4.31) with the y-axis gives the reverse saturation current density (J s ). If the current is purely due to thermionic emission, this value can be used to compute the zero-bias barrier height (Φ B0 ): ( ) J s = A T 2 ΦB0 exp (4.32) kt where A is the effective Richardson s constant. If other current mechanisms are important this equation does not hold and the resulting barrier height is incorrect. Good Schottky contacts are characterized by a low ideality factor (1 < n < 1.1). Deviations from the ideal value of 1 can be caused by image-force induced barrier lowering (Schottky effect), interface states and/or other current mechanisms like field emission [3]. The capacitance-voltage method. The charging and de-charging of the depletion region in the semiconductor effectively constitutes a capacitance (C). If a thin interfacial layer and surface states are present, it is assumed that the charge transferred from and to these states is supplied by the metal and does therefore not contribute to the overall capacitance [2]. It can be shown that plotting 1/C 2 versus the applied bias should result in a straight line, which has a slope of 2/(qɛ s N D ) and an intercept (V I ) on the x-axis of [3]: V I = Φ B0 /q ξ/q kt q + Φ 1 /q [ V d0 kt q ] + Φ 1 4q (4.33) where V d0 is the zero-bias diffusion voltage. Combining Eqs. (4.10), (4.11) and (4.33) gives: V I + ξ/q + kt/q = Φ0 B q + Φ 1 4q (4.34)

4.3 Ohmic Contacts 41 Usually, Φ 1 is negligible 3. The capacitance method therefore essentially yields the flat-band barrier height. The internal photo-emission method. By illuminating the contact with monochromatic light, electrons in the metal can absorb the photon energy and cross the barrier into the semiconductor causing a photocurrent. By plotting the square root of the photocurrent per photon, which is proportional to (E photon Φ B ) 2, versus the photon energy (E photon ) and extrapolating to zero, the barrier height can be extracted. The I-V techniques mentioned above, all assume that the metal-semiconductor junction controls the current. Within the AlGaN/GaN structure, there are two junctions. This situation can be described by two diodes in series (actually three if one counts the return path of the current as well), which makes it quite impossible to determine the barrier height from I-V measurements. C-V measurements are also inapplicable because the capacitance is dominated by the 2DEG and not by the depletion region of the contact itself. An internal photo-emission setup was unfortunately not available. The remaining option was to optimize the contact with respect to the reverse current, which is partly related to the barrier height. To analyze a Schottky contact, one needs the Schottky contact itself and a lowresistance ohmic contact. It therefore seems natural to start with the discussion on ohmic contacts. As we will see, the approach used to find a good ohmic contact is totally different from finding a good Schottky contact. The metal stack used for ohmic contacts is usually annealed at high temperatures, which causes diffusion and/or reactions between the metals and the semiconductor. A purely theoretical discussion as presented above is most likely not valid in this case. For most contacts however, the general idea is that metal reacts with and/or diffuses into the semiconductor. This results in a highly doped region underneath the contact. Due to this doping, the barrier becomes so thin, that electron tunneling becomes the dominant current mechanism. This way, ohmic I-V characteristics can be obtained. 4.3 Ohmic Contacts 4.3.1 Metallization Scheme and Epitaxial Structure The entire work on ohmic contacts was done on identical 2 MOVPE-grown doped Al- GaN/GaN HEMT structures. Starting at the bottom, these structures had the following epitaxial layer stack: 350µm sapphire substrate, 40nm AlN nucleation layer, 2µm semiinsulating GaN buffer, 3nm non-intentionally doped (n.i.d.) Al 0.25 Ga 0.75 N spacer layer, 15nm Si-doped (10 18 cm 3 ) Al 0.25 Ga 0.75 N donor layer and a 5nm n.i.d. Al 0.25 Ga 0.75 N cap layer. The spacer layer is included to reduce the ionized-impurity scattering that deteriorates electron mobility in the 2DEG. A cap layer is included to enhance performance of the Schottky contacts. 3 Using numerical data from Rizzi et al. [4] presented in the previous section, we find Φ 1 = 0.002eV.

42 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures Most ohmic contacts on AlGaN/GaN heterostructures are based on Ti/Al metallization schemes. The most frequently reported are the Ti/Al/Ti/Au, Ti/Al/Ni/Au and Ti/Al/Pt/Au schemes. Each of the metals in these stacks has its own specific role. Titanium, the first metal in all cases, is believed to: Serve as an adhesion layer to provide good mechanical stability [14]. Dissolve the native oxide on the AlGaN surface [15, 16]. Create nitrogen vacancies by reacting with nitrogen atoms in the AlGaN. This process renders the surface highly doped, which enables electrons to tunnel through the thin barrier [14, 15]. Aluminum supposedly: Reacts with Ti to form an Al 3 Ti layer that prevents the underlaying Ti layer from oxidizing [14, 15]. Serves as a diffusion barrier for the metals on top of Al as they form high Schottky barriers [16]. The Ni and Pt layers should prevent the diffusion of Au to the Al layer. This Au layer is added to improve the conductivity of the metal stack. However, when Au and Al react, they could form the so-called purple plague, a highly resistive layer. One of the most important reasons for adding metals on top of Al is to prevent this layer from smearing out. Usually, the ohmic contacts are annealed at very high temperatures (> 800 0 C), well above the melting point of Al (660 0 C). If no metals are put on top of Al, the line definition of the contact cannot be controlled. Ruvimov et al. [14] propose the following mechanism for ohmic contact formation during the annealing process. First, reactions start between Ti and Al at relatively low temperatures (200 300 0 C) with the formation of an Al 3 Ti phase according to the binary phase diagram. If Al and Ti were the only metals involved, this would require an Al/Ti thickness ratio of 2.82. If this ratio is smaller, there is an excess of Ti available to react with the AlGaN. This reaction probably starts at 400 0 C and involves: The dissolution of the native oxide present at the surface. Subsequent outdiffusion of nitrogen to form nitrogen vacancies. The formation of Ti-Al-N interfacial phases. Decomposition of the AlGaN probably starts at temperatures above 850 0 C causing degradation of the ohmic contact and the crystal structure itself. From the discussion it is clear that several reactions take place at different temperatures. To get reproducible results, it is therefore important to accurately control the heat treatment both in temperature variations and in time. Rapid thermal annealing (RTA) is the technique most suited to meet these requirements and was therefore used for this work.

4 4.3 Ohmic Contacts 43 1 A J = 1 O @ N 1 N @ I A E? @ K? J H @ O 1 N @ N 1 O @ O Figure 4.5: Current distribution underneath an ohmic contact. The resistor (R) models the metal-semiconductor junction. 4.3.2 The Transfer Length Method Ohmic contacts are usually characterized by the contact resistance (R c ) and/or specific contact resistance (ρ c ). These parameters can be determined using the so-called transfer length method (TLM). This method is based on measuring the total resistance between two contacts as a function of the distance between them. If this data is extrapolated to a zero spacing, we essentially obtain the sum of the contact resistances of each contact. The specific contact resistance can also be determined with this technique but this requires additional calculations. To derive these equations, we need to model the current distribution underneath the contact. Such a model is illustrated in Figure 4.5. It represents an infinitesimally small portion of the ohmic contact in which the metal is assumed to be a grounded equipotential plane. The metal-semiconductor junction is represented by a resistor (R) that is related to the specific contact resistance by: Applying current continuity we find: R = ρ c dxdy (4.35) [J x (x + dx) J x (x)] dydz + [J y (y + dy) J y (y)] dxdz = J z dxdy (4.36) We can relate the current densities to the potential in the semiconductor (V (x, y)) using: J z = V (x, y)/ρ c (4.37) J = 1 R sh,c dz 2 V (x, y) (4.38) where R sh,c is the sheet resistance of the semiconductor underneath the contact and 2 = ˆx / x + ŷ / y, with ˆx and ŷ unit vectors in the x and y direction, respectively.

H 44 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures 9 @? O @ I I? H O 6 + 6 Figure 4.6: Examples of a Linear TLM and circular TLM layout. It should be noted that annealing at high temperatures > 700 0 C, may trigger reactions between the metal and the semiconductor. The sheet resistance in uncovered regions, R sh = ρ s /dz with ρ s the specific resistance of the semiconductor, will therefore be different than R sh,c. Combining Eqs. (4.36)-(4.38) we have: 2 2V (x, y) 1 L 2 t V (x, y) = 0 (4.39) where L t is the transfer length that can be computed from: ρc L t = (4.40) R sh,c Given a certain layout, Eq. (4.39) and Eq. (4.38) can be used to calculate the potential and current inside the semiconductor, respectively. This procedure will be demonstrated using a linear and circular layout. Linear TLM (LTLM). In the linear TLM structure of Figure 4.6, all the contacts are on top of a mesa, which is represented by the dotted line. This mesa is needed to restrict the current flow in one direction only. In this case, Eq. (4.39) reduces to a one-dimensional differential equation. Taking I(y=0)=0, I(y=d l )=I 0 and V (y=d l )=V 0 as boundary conditions for the lower contact, this equation can be solved. The contact resistance is defined as the ratio between voltage and current at the edge of the contact (y = d l ) normalized with respect to the contact width W l : ( ) R c = W l V0 dl = R sh,c L t coth (4.41) I 0 Hence, if W l is in millimeters, which is the most common unit, R c represents the resistance of a 1mm wide contact. Note that R c depends on the metal-semiconductor junction, through L t (ρ c ), and the conductivity of the semiconductor underneath the contact. One could therefore argue, that to characterize the metal-semiconductor junction itself, ρ c is the more relevant parameter. L t

4.3 Ohmic Contacts 45 Assuming that the contacts are electrically long, i.e d l L t, square and of equal size, we can compute the total resistance between the two contacts by adding the resistance of the semiconductor region in between them: R tot = 2 Rc W l + R shs l W l = R sh W l ( ) R sh,c 2L t + s l R sh (4.42) Circular TLM (CTLM). In circular contacts, the current flows radially. Using polar coordinates, Eq. (4.39) can be written as a one-dimensional equation. Because this layout does not require a mesa, the complexity of the processing is reduced and problems like current crowding and miss-alignment can be avoided. Using similar boundary conditions and again assuming that the contacts are electrically long, i.e. (d c 2r 2 ) L t and r 1 L t we find: R tot = R shr sh,c 2π [ ( 1 r1 + s c ln R sh,c r 1 ) + L ( t 1 + 1 ) ] (4.43) R sh r1 r 1 + s c where the first term inside the large brackets is related to the resistance between the contacts. The second and third term are related to the resistance of the inner and outer contact, respectively. Using correction factors, this equation can be written in a form similar to Eq. (4.42): R tot = R tot c(r 1, s c ) R ( ) sh R sh,c 2L t + s c 2πr 1 R sh where the correction factors can be computed from: c(r 1, s c ) = r ( ) 1 r1 + s c ln s c r 1 (4.44) (4.45) The error introduced by this correction usually remains under two percent. However, one should be careful using this correction if both s c and L t are comparable to r 1. Extraction of contact parameters from measurement data using CTLM. The common procedure to determine the specific contact resistance is to measure several pairs of identical contacts with different values for s c. According to Eq. (4.44), plotting Rtot versus s c should produce a straight line. Performing a linear fit to Rtot = a + b s c yields: a = 2R sh,cl t W c (4.46) b = R sh W c (4.47) where W c = 2πr 1. Parameter a represents the sum of the individual contact resistances. If both contacts are electrically long, we can simply multiply a by W c /2 to find the contact resistance R c. The value of s c for which the total resistance is zero can be computed from: s c (y = 0) = a b = 2R sh,cl t R sh (4.48)

46 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures This value can be used to compute the specific contact resistance: ( ) 2 sc (y = 0) Rsh 2 ρ c = (4.49) 2 R sh,c Although the sheet resistance of the semiconductor is known from b, the sheet resistance underneath the contact cannot be determined from these measurements alone. Usually, one assumes R sh = R sh,c as a working condition but the validity of this assumption is highly questionable. Another approach is to determine the specific contact resistance using the so-called end-resistance technique [17]. For this research, the circular TLM layout was used to analyze the ohmic contacts using the assumption R sh = R 4 sh,c. The resistance measurements themselves were done using a four-probe approach. 4.3.3 Optimization of the Ohmic Contact Preliminary investigations of ohmic contacts on GaN and AlGaN have shown that treating the surface with chemicals like diluted ammonium hydroxide (NH 4 OH), buffered hydrofluoric acid (BHF) and HCl prior to metal deposition does not influence the contact resistance significantly. Also, contrary to results published in literature [18, 19], we could not see improvements when the surface was subjected to a reactive ion etch prior to deposition. We therefore decided to optimize the metal layer stack itself without using chemical treatments apart from the usual cleaning steps involving acetone and iso-propyl alcohol (IPA). The starting point of the optimization was the contact reported by Cai et al. [20], which consisted of 20nm Ti, 80nm Al, 40nm Ni, and 150nm Au, on a doped AlGaN/GaN structure annealed at 900 0 C for 35s in a nitrogen ambient. The authors reported a contact resistance of 0.04Ωmm and a specific contact resistance of 5.4 10 8 Ωcm 2. Repeating their experiment on our material gave 1.3Ωmm and 2.7 10 5 Ωcm 2, respectively. Optimization of this contact was therefore necessary. For the optimization experiments, we used samples of 1cm 2 that were each given a different e-beam metal evaporation in an AIRCO system operating at a base pressure of 10 7 mbar. After evaporation, the samples were each cleaved into four pieces that were annealed at 700, 800, 900 and 1000 0 C, respectively, for 30s in a nitrogen ambient. To optimize the contact we varied: The Al/Ti thickness ratio, see Figure 4.7. On each sample a metal stack was evaporated with a different Al/Ti thickness ratio. The Ti, Ni and Au layers were kept constant at 20, 40 and 150nm, respectively. Measurements showed that for each metal stack the optimum annealing temperature was 900 0 C and that the best thickness ratio was 6 contrary to the theory described in section 4.3.1. The thickness of the Ti layer for a given Al/Ti ratio, see Figure 4.8. Using the optimum Al/Ti ratio and again setting the Ni and Au layers to 40 and 150nm, respectively, the thickness of the Ti layer itself was varied. An optimum was found at 30nm again for an annealing temperature of 900 0 C. 4 Layout data: 9 contact pairs with r 1 = 50µm, s c = 4, 8, 12, 16, 20, 24, 32, 40, 48µm and d c = 400µm.

4.3 Ohmic Contacts 47 Figure 4.7: Variation of the Al/Ti ratio. Figure 4.8: Variation of the thickness of the Ti layer. Figure 4.9: Variation of the thickness of the Ni layer. Figure 4.10: Contact resistance of the optimized metal stack as a function of annealing temperature and time. The thickness of the Ni layer, see Figure 4.9. Using Ti, Al and Au thicknesses of 30, 180 and 150nm, respectively, the thickness of the Ni layer was varied. A sharp optimum was found at 40nm using an annealing temperature of 900 0 C. The annealing temperature and time, see Figure 4.10. Varying both annealing time and temperature for the optimized metal stack determined in the previous three steps again showed an optimum at 900 0 C for 30s. The resulting metal stack, Ti/Al/Ni/Au=30/180/40/150nm, showed a contact resistance of 0.2Ωmm and a specific contact resistance of 7.3 10 7 Ωcm 2 when annealed at 900 0 C for 30s. Furthermore, the sheet resistance determined using the CTLM method, which was 500 600Ω/sq, corresponded to values supplied by the grower of the HEMT structures.

48 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures Figure 4.11: SEM image showing the surface morphology of a Ti/Al/Ni/Au circular contact. Figure 4.12: Exposing a cross-section of the contact using FIB. Figure 4.13: Magnification of the exposed cross-section. Figure 4.14: Close-up of feature 1 in Figure 4.13. The numbers correspond to EDS analysis spots. 4.3.4 Measurement Accuracy, Reproducibility, Line Definition and Morphology Line definition and morphology are two important aspects of an ohmic contact that influence the remaining part of the process flow. If the line definition is poor, close gate-tosource spacings become impossible. Furthermore, if the extrusions are too pronounced, premature breakdown could occur. Obtaining good contrast for alignment purposes becomes difficult if the surface of the contact is too rough. In addition, subsequent depositions of metals or dielectrics might suffer from bad step coverage due to large height differences. Figure 4.11 shows a SEM image of the optimized Ti/Al/Ni/Au contact. We did not encounter any difficulties with the line definition of this contact. However, measured height differences exceeded 300nm. This is caused by the balling-up of metal. Most likely

4.3 Ohmic Contacts 49 this process is related to Al, which has a melting point of 660 0 C, which is far below the annealing temperature. To investigate this phenomenon, focussed ion beam (FIB) etching was used to expose a cross-section of the contact, see Figure 4.12. This crosssection, enlarged in Figure 4.13, shows several regions in which metal has accumulated. Energy dispersive spectroscopy (EDS) was used to analyze the chemical composition of one of those regions. Analysis done on four spots, shown in Figure 4.14, revealed the presence of the following elements: Spot 1: Mainly Ni and Al, small amounts of O. Spot 2: Mainly Au, small amounts of Al and O. Spot 3: Mainly Au and Al, small amounts of O and Ti. Spot 4: Mainly Au and Al, small amounts of O. This analysis shows that the metal layer stack is not maintained after annealing. Large areas exist that are mostly filled with either Al or Au. Also, certain regions contain both elements. Oxygen, most likely originating from the native oxide, is also present in the layer stack. It should be mentioned that Ga was found in all four spots. However, because this element was used for the FIB etch, it is uncertain whether Ga has diffused out of the AlGaN layer. These tests also do not give information about the diffusion depth of the metals due to the high temperature annealing step. Although the height differences measured on the surface are far from ideal, it was decided to continue with this contact scheme. It should be noted that most of the contacts published in literature have this problem. The use of these contacts as alignment marks for stepper or e-beam lithography is therefore troublesome. The accuracy of the calculated contact resistance heavily depends on the measurement of the spacing (s c ) between the different contacts. For this work we used a Reichert-Jung optical microscope in combination with a Varimet distance analyzer. The values that were found with this setup were confirmed by SEM and AFM analysis. We found that the spacings between fabricated ohmic contacts were typically 0.3 0.8µm larger than the nominal gap spacings on the CTLM mask. This discrepancy is most likely related to the balling-up of metal as described above. Deviations in spacing values were found to be constant across the sample. Furthermore, repetitive measurements showed that the reproducibility of this measurement is around 0.1µm for the smallest spacing value. Measurements of R c and ρ c on different spots on the sample usually are within 20 percent. Variations in contact resistance and specific contact resistance can also be caused by variations in the thickness and Al mole fraction of the AlGaN layer [21]. To exclude these effects, we therefore only compared those values of R c and ρ c that were obtained on samples with comparable sheet resistances. Using the optimized metal stack, we found that the variation in R c and ρ c measured on different samples is comparable to the variation within the sample. An extensive study on the uniformity across different wafers has not been carried out. It is obvious that a good calibration of the evaporator system and very low metal contamination are indispensable for obtaining low contact resistances.

50 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures Table 4.1: Workfunction for various metals [22]. metal workfunction (ev) Ag 4.26 Al 4.28 Ti 4.33 Cr 4.5 W 4.55 Mo 4.6 Au 5.10 Pd 5.12 Ni 5.15 Ir 5.20 Pt 5.65 4.3.5 Concluding Remarks The optimized Ti/Al/Ni/Au contact has a very low contact resistance and specific contact resistance of 0.2Ωmm and 7.3 10 7 Ωcm 2, respectively, and shows acceptable line definition. These results are well within the specified contact resistance of 0.44Ωmm as derived in section 4.1. The Al/Ti ratio found during optimization does not correspond to the models proposed in literature. Also, the Ni thickness proved to be very important. If we would have started with different values for the Ni and Au layer, we probably would have found a different optimum for the Al/Ti ratio and Ti thickness. We therefore believe that in a detailed analysis of the ohmic contact, the role of the Ni and Au layer has to be included. Such an analysis is however beyond the scope of this thesis. A drawback of this contact, or any other contact containing Al, is the rough surface morphology if annealing temperatures above the melting point of Al are required. 4.4 Schottky Contacts on AlGaN/GaN FET Structures 4.4.1 Schottky Metallization As mentioned in section 4.2.3, wide band gap materials like GaN, are more sensitive to the workfunction of the applied metal than small bandgap semiconductors like Si or GaAs. Metals with high workfunctions are therefore the prime candidates for the realization of Schottky contacts. Table 4.1 presents the workfunction for various metals. For Schottky contacts, Au, Pd, Ni, Ir, and Pt are the most suitable metals. However only Au, Pt, and Ni are available in our metal e-beam evaporation systems. Preliminary investigations on Au contacts on GaN have shown that these contacts are inferior to Pt and Ni contacts, an observation that is consistent with results published in literature [23]. The adhesion

4 4.4 Schottky Contacts on AlGaN/GaN FET Structures 51 4 # 9 $ & 9 $! 9 $ " 9 $ & 9 $ ' 4! 9 $ " 9 $ # 4 9 $ ) / = J D E? A I I ' ' 9 $ ' 9 $ 4 $ 9 $ # 9 $ $ 9 $ % 9 $ 9 $ 9 $ 9 $ $ 9 $ % 4 " 9 $ 9 $! $! % Figure 4.15: Wafer mapping of the 1cm 2 test pieces (W6 X) for the Schottky contacts. The AlGaN thickness is more or less constant in the direction of the arrows but varies perpendicular to the major index. properties of the Schottky metal are also an important feature. Preliminary investigations have shown that although Pt contacts are comparable with Ni contacts, they suffer from bad adhesion, which may result in the metal breaking off the surface during the lift-off process. For the reasons mentioned above, we have chosen to focus on Ni contacts only. The metallization scheme described in this section consists of 20nm Ni followed by 200nm of Au to enhance conductivity and to prevent the oxidation of Ni. Because the contacts are not alloyed, the Au layer should not influence the reverse current. It can however play an important role in the thermal stability of the contact. Unlike our approach with the ohmic contacts, which was focused on optimizing the metal stack, we will now try to find suitable pre-treatments to improve the behavior of the contact. 4.4.2 Wafer Description and Schottky Layout All the Schottky contacts were made on 1cm 2 pieces belonging to the same 2 wafer. This MOVPE-grown wafer consisted of a 330µm thick sapphire substrate followed by a thin ( 30nm) proprietary nucleation layer, a 1µm semi-insulating GaN buffer layer, and a non-intentionally doped Al 0.33 Ga 0.67 N layer. The AlGaN thickness varies perpendicular to the major index of the wafer from 20 to 24nm, as illustrated in Figure 4.15. The layout of the Schottky contacts investigated in this chapter is similar to the circular TLM layout in Figure 4.6. First, the ohmic outer contacts are evaporated and annealed. After this, the Ni/Au inner contacts are placed concentric with respect to the ohmic contacts. For our investigations we have used Ni/Au dots with a radius (r 1 ) of 54µm separated from the ohmic contacts by s c = 23µm. The entire Schottky contact had a width (d c ) and height of 1140µm. On a typical 1cm 2 sample, 9 of these contacts are available, the rest of the available space is used by alignment marks, ohmic contacts and Schottky contacts with different dimensions, see section 4.4.5. The I-V characteristics of the contacts are measured using a pico-ampere meter involving two needle probes. The noise margin of the entire setup was about 1pA, which proved to be more than sufficient to characterize the diodes. C-V analysis was performed using an LCR meter at 100kHz.

52 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures Figure 4.16: Reverse and forward currentvoltage characteristics of Schottky contacts on samples W6 1, W6 2 and W6 3. Figure 4.17: Capacitance and current versus bias for sample W6 3. Capacitance data of W6 1 is included to demonstrate the Al- GaN thickness variation. 4.4.3 Reference Tests As a first experiment, Schottky contacts were realized on samples W6 1, W6 2 and W6 3. Samples W6 1 and W6 2 were not treated prior to metallization, whereas sample W6 3 was subjected to a 15s NH 4 OH(40%):DI 5 (1:10) dip. Figures 4.16 and 4.17 are typical examples of the current-voltage and capacitance-voltage behavior, respectively. From Figure 4.16 one could conclude that the NH 4 OH treatment degrades performance. However, sample W6 2, shown in inset, had the same characteristics as sample W6 3. Evidently, the uniformity from sample to sample, as well as the uniformity on the sample itself, is rather poor. The presence of an interfacial layer, e.g. an irregular oxide layer, or the non-uniformity of the wafer itself, could be responsible for this. As was mentioned before, the thickness of the AlGaN layer varies across the wafer. This can be seen from the C-V measurements in Figure 4.17, which show three regions: The pinchoff region (V a < V p ). For voltages below the pinchoff voltage (V p ), which is approximately -8V for W6 3, there are no electrons present in the 2DEG. By plotting 1/C 2 versus bias, information about the doping of the bulk GaN layer can be obtained, see section 4.2.5. The charge-control region (-8V< V a < 1V) [24]. In the charge-control region the gate potential has full control over the 2DEG. In this region the capacitance density can be approximated by Eq. (4.29): C 2DEG = qσ 2 V a = ɛ AlGaN (d + d) (4.50) where d is a correction factor that accounts for the fact that the 2DEG does not exactly reside at the AlGaN/GaN interface. It can be computed using [24]: d = ɛ AlGaNa (4.51) q 5 DI stands for De-Ionized water.

4.4 Schottky Contacts on AlGaN/GaN FET Structures 53 Using a = 0.125 10 16 V/m 2, which is an estimate for GaAs-based HEMTs [25], we find d 6.5nm. Using these values, we find d = 24.6nm and d = 17.2nm for samples W6 3 and W6 1, respectively. These values correspond well to the values indicated by the wafer layout in Figure 4.15. The maximum 2DEG region (V a > 1V). For sufficiently large forward bias, the depletion regions of the Schottky contact and the heterojunction do not overlap. The electron concentration in the 2DEG has reached its maximum value and is now independent of the gate voltage. In theory, the Schottky characteristics can be computed from 1/C 2, as was explained in section 4.2.5. However, this is usually very difficult due to the high currents that flow under these conditions. It should be noted that measurements done at different frequencies ranging from 1kHz to 50MHz all showed the same capacitance values. This indicates that there are no traps present in the AlGaN layer that have time constants corresponding to this frequency region. 4.4.4 Forward and Reverse Characteristics To explain the possible current mechanisms under forward bias we will use Figure 4.18 and 4.19, respectively. The forward characteristics are different than one would expect based on Eq. (4.31). The logarithmic plot shows only a small region in which we can deduce an ideality factor n, which in addition is unrealistically high if only one single diode is involved. The behavior under forward bias can be divided into three regions. A low-bias region (V a < 0.5V) in which leakage currents dominate, a mid-bias region (0.5V< V a < 1V) showing some exponential behavior, and a high-bias region (V a > 1V), which is dominated by the series resistance of the diode. The latter is merely a consequence of the finite conductance of the semiconductor. The mid-bias region is characterized by a high ideality factor, something that has also been observed in AlGaAs/GaAs HEMTs [26]. Electrons in the 2DEG that move towards the gate have to overcome two barriers back to back. The first barrier is caused by the conduction band discontinuity at the heterojunction, the second is the barrier leading up to the Schottky contact, see Figure 4.20. Strictly speaking, the heterojunction under the ohmic contacts also has to be accounted for. Its influence can however be neglected because it is biased in forward direction and because the barrier itself is probably affected (lowered) by the high temperature annealing step during the ohmic contact formation. For sufficiently high forward bias, the heterojunction influences the overall characteristics, because it is reverse biased. The effective barrier height of this junction is relatively small resulting in a high ideality factor 6. The interplay of this diode with the Schottky diode causes the high ideality factor in the overall measurement [26]. In Figure 4.19 the same data is plotted on a linear scale together with a small fraction of the reverse characteristics. A parasitic resistance, which dominates the current between -3V< V a < 0.5V, is present in parallel with the actual diode. It will be shown later on 6 In [8] it is shown that the ideality factor decreases with increasing barrier height.

54 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures Figure 4.18: Forward current-voltage characteristics of W6 3. The inset shows lines corresponding to different n values. Figure 4.19: Calculation of the parasitic resistance for sample W6 3. D E? 5? D J J O D E? Figure 4.20: Location of the three diodes in the heterostructure. Figure 4.21: Reverse current-voltage characteristics of W6 3. that this resistance is independent of the treatment performed prior to metallization, but that it increases with time. The reverse characteristics, shown in Figure 4.21, can also be divided into three regions. A low-bias region (V a > 3V), which is dominated by the parasitic resistance discussed before, a mid-bias region (V p < V a < 3V) that shows signs of thermionic (field) emission, and a high-bias region (V a < V p ), which is also characterized by a parasitic resistance. This resistance, which is approximately the same as the low-bias resistance, is also independent of the treatment performed prior to metallization, and also increases with time. One can notice that the contribution of the thermionic (field) emission saturates at pinchoff. For voltages below pinchoff, the current is not limited by the transport over the barrier, but by the limited amount of electrons in the 2DEG. It is therefore unlikely that the leakage current at high reverse bias, characterized by the 700kΩ resistance, flows

4.4 Schottky Contacts on AlGaN/GaN FET Structures 55 Table 4.2: Overview of pre-treatments. sample solution T( 0 C) t(s) W6 9 NH 4 OH(40%):DI (1:10) 22 60 W6 10 HF:DI (1:10) 22 15 W6 14 NH 4 OH(40%):DI (1:10) 50 60 W6 15 (NH 4 ) 2 S 2 O 8 :KOH (0.08M:0.1M) 22 60 W6 11 (NH 4 ) 2 S 2 O 8 :KOH (0.08M:0.1M) 22 900 W6 16 NH 4 OH(40%):DI (1:10) 22 900 W6 8 RIE SiCl 4 :Ar 22 60 10:10sccm, V BIAS =70V, 15W, 40mTorr NH 4 OH(40%):DI (1:10) 22 900 W6 13 RIE SiCl 4 :Ar 22 60 10:10sccm, V BIAS =70V, 15W, 40mTorr HF:DI (1:10) 22 15 W6 7 RIE O 2 22 60 50sccm, V BIAS =85V, 15W, 100mTorr NH 4 OH(40%):DI (1:10) 22 900 through the 2DEG. This leakage could be related to a parasitic current path through the AlGaN layer, or across its surface. More experiments are needed to verify this. 4.4.5 Optimization of Pre-Metallization Treatments Because it is difficult to extract a value for both the barrier height and the ideality factor from I-V and/or C-V measurements, the contacts were optimized with respect to the reverse current. The optimization itself consisted of trying various cleaning/etching processes, both wet and dry, prior to metallization (but after lithography). Various authors have published results on dry etching techniques like chemically assisted ion beam etching (CAIBE) [23], ICP [27, 28] and RIE [29, 30, 31] with Xe, Ar or Cl 2 :Ar gas mixtures. Mostly, dry etching is followed by a wet etch to remove the damaged top layer or contaminants resulting from the etch. Significant improvements can also be achieved using only wet-chemical cleaning. Wet-chemical cleaning can be done using acids or bases. The most commonly used acids are hydrofluoric acid (HF), both in buffered and diluted form, and HCl. These acids should remove the oxide layer present at the AlGaN surface and possible residues of photoresist that remained after development. It has been reported that HCl can react with Ga to form gallium trichloride (GaCl 3 ) [32]. This, together with disappointing results using HCl in preliminary work, led to the decision not to consider HCl as a possible pretreatment. Cleaning using bases is also widely used. NH 4 OH is very effective in cleaning the surface and reducing any native oxide [33]. KOH in combination with a strong oxidation agent like diammonium peroxodisulphate ((NH 4 ) 2 S 2 O 8 ) has also given good results [34].

56 Metal-Semiconductor Contacts on AlGaN/GaN Heterostructures Figure 4.22: Impact of different treatments on the reverse current. Figure 4.23: Comparison between wet and dry etching/cleaning processes. Because a wet-chemical etch/cleaning step is needed regardless whether a dry etch has been used, these treatments were optimized first. Experiments were carried out using NH 4 OH (W6 9), HF (W6 10) and KOH (W6 15), see Figure 4.22. The process details can be found in table 4.2. Although all three treatments improved the uniformity of the diodes, they differed strongly in reducing the reverse currents. To make the etch more effective, both temperature and duration have to increase. This cannot be done arbitrarily because the photoresist is attacked as well. For NH 4 OH, experiments were carried out using a longer etching time (W6 16) and a higher solution temperature (W6 14). Also the KOH etch was performed using a longer etching time (W6 11). These three experiments represent limiting cases in what the photoresist can endure. The HF experiment (W6 10) from the previous set of experiments was already a limiting case. The results in Figure 4.22 show that only moderate improvement has been achieved by increasing the temperature of the NH 4 OH solution, whereas the longer etching time significantly improved performance. For the KOH solution this was not the case, the reverse current actually increased. Next, two experiments were carried out involving a chlorine-based RIE etching process, which was performed at low power to avoid excessive damage. After etching but prior to metallization, the samples were exposed to the best wet-chemical etchants from the previous sets of experiments. Sample (W6 8) was etched/cleaned using the NH 4 OH solution for 15min. after the RIE etch, sample (W6 13) was exposed to the HF solution for 15s. As shown in Figure 4.22, this reduced the reverse currents even further. A similar test was conducted using an oxygen plasma in combination with the NH 4 OH etch (W6 7). However, this sample was not measured directly after processing like the other samples mentioned up to this point 7, but a few weeks later. To make a good comparison, the other samples had to be measured again. These measurements showed that all diodes had improved with time. However, the order for best treatment remained the same. Figure 4.23 shows the results for the best four treatments after the second measure- 7 Typically, samples were measured within one or two days after processing.

4.4 Schottky Contacts on AlGaN/GaN FET Structures 57 Figure 4.24: Reverse current versus bias for sample W6 9, which had the NH 4 OH treatment for 15min. Figure 4.25: Extraction of the ideality factor for W6 9. Figure 4.26: Reverse current at -20V versus diode area; sample W6 5, spacing = 20µm. Figure 4.27: Capacitance (0V) versus diode area; sample W6 5, spacing = 20µm. ment. The improvement in leakage currents can clearly be seen. Furthermore, the NH 4 OH solution for 15min. appears to be the best option for high-power applications. At low bias, both SiCl 4 :Ar plasma treatments give better results. Careful inspection of Figures 4.22 and 4.23 shows that the aging of the contacts not only led to a reduction in reverse current but also that the current mechanism itself has changed. This is explored further in Figures 4.24 and 4.25 that show the reverse characteristics of sample W6 9, which are typical for all samples but the two chlorinebased RIE etched samples. Figure 4.24 illustrates that the parasitic resistance in the high-bias region mentioned in the previous section essentially has disappeared. For high voltages (> 80V) the current increases exponentially. This could be related to breakdown. Figure 4.25 illustrates that the parasitic resistance in the low-bias region has also disappeared. The behavior in the mid-bias region can be described by an ideality factor of 1.12, which could indicate thermionic (field) emission. It should be noted that the resis-

58 REFERENCES tance in series with this diode, e.g. the resistance of the 2DEG, strongly depends on bias. This effect could increase the effective ideality factor. Furthermore, other mechanisms like generation-recombination current might be involved. To examine the lateral current distribution, diodes were made with varying area (W6 5). This sample was given the 15min. NH 4 OH treatment prior to metal deposition. Figures 4.26 and 4.27 show that both reverse current and capacitance scale with diode area. Edge effects related to field crowding are therefore not visible for these sizes. 4.4.6 Discussion Reverse currents for Schottky diodes on AlGaN/GaN structures strongly depend on time. This corresponds to the behavior of Schottky contacts on different material systems [35]. Diodes measured directly after fabrication, show a parasitic resistance in parallel with the actual diode. Aging reduces this parasitic current path. To accelerate this process, one could use heat treatments at moderate temperatures (< 300 0 C) [35]. Based on the measurements described in this chapter, a conclusive argument for the origin of the leakage current cannot be given. The fact that it does not saturate under reverse bias does however suggest that the current does not flow through the 2DEG, leaving the AlGaN barrier layer and its surface as the remaining possibilities. Experiments employing surface treatments after processing targeted at the region between the ohmic and Schottky contact could provide an answer. For most applications however, the non-stable behavior with time does not pose any problems because the leakage currents themselves are sufficiently low. It is difficult to compare the Schottky contacts developed in this chapter with published work. First of all, most Schottky contacts described in literature were either developed on GaN or on AlGaN. Using a single semiconductor instead of the AlGaN/GaN structure used for this work, eliminates the problem of the diode connection introduced by the heterojunction. Furthermore, reverse currents are not often reported at the same bias values. Also, the difference in material quality makes a fair comparison rather difficult. References [1] U. Karrer, O. Ambacher, and M. Stutzmann, Influence of Crystal Polarity on the Properties of Pt/GaN Schottky Diodes, Applied Physics Letters, vol. 77, no. 13, p. 2012, 2000. [2] A.M. Cowley, Depletion Capacitance and Diffusion Potential of Gallium Phosphide Schottky-Barrier Diodes, Journal of Applied Physics, vol. 37, p. 3024, 1966. [3] E.H. Rhoderick and R.H. Williams, Metal-Semiconductor Contacts. Oxford Science Publications, 1988. [4] A. Rizzi and H. Luth, Comments on Influence on Crystal Polarity on the Properties of Pt/GaN Schottky Diodes, Applied Physics Letters, vol. 80, no. 3, p. 530, 2002. [5] A.R. Smith, R.F. Feenstra, D.W. Greve, M.S. Shin, M. Skowronski, J. Neugebauer, and J.E. Northrup, Reconstructions of GaN(0001) and (0001) Surfaces: Ga-rich Metallic Structures, Journal of Vacuum Science and Technology B, vol. 16, no. 4, p. 2242, 1998.

REFERENCES 59 [6] V. Heine, Theory of Surface States, Physical Review, vol. 138, p. A1689, 1965. [7] J. Tersoff, Schottky Barrier Heights and the Continuum of Gap States, Physical Review Letters, vol. 52, no. 6, p. 465, 1984. [8] W. Mönch, Barrier Heights of Real Schottky Contacts Explained by Metal-Induced Gap States and Lateral Inhomogeneities, Journal of Vacuum Science and Technology B, vol. 17, no. 4, p. 1867, 1999. [9] W. Mönch, Chemical Trends of Barrier Heights in Metal-Semiconductor Contacts: On the Theory of the Slope Parameter, Applied Surface Science, vol. 92, p. 367, 1996. [10] W. Gordy and W.J.O. Thomas, Electronegativities of the Elements, Journal Chemical Physics, vol. 24, p. 439, 1956. [11] W. Mönch, On the Physics of Metal-Semiconductor Interfaces, Reports on Progress in Physics, vol. 53, no. 3, p. 221, 1990. [12] O. Madelung, M. Schulz, and H. Weiss, Landolt-Bornstein Group III (Volume 17, Subvolume B). Springer Verlag, 1982. [13] J.P. Ibbetson, P.T. Fini, K.D. Ness, S.P. DenBaars, J.S. Speck, and U.K. Mishra, Polarization Effects, Surface States, and the Source of Electrons in AlGaN/GaN Heterostructure Field Effect Transistors, Applied Physics Letters, vol. 77, no. 2, p. 250, 2000. [14] S. Ruvimov, Z. Liliental-Weber, J. Washburn, D. Qiao, S.S. Lau, and P.K. Chu, Microstructure of Ti/Al Ohmic Contacts for n-al x Ga 1 x N, Applied Physics Letters, vol. 73, no. 18, p. 2582, 1998. [15] Q.Z. Liu, L.S. Yu, F. Deng, S.S. Lau, Q. Chen, J.W. Yang, and M.A. Khan, Study of Contact Formation in Al x Ga 1 x N/GaN Heterostructures, Applied Physics Letters, vol. 71, no. 12, p. 1658, 1997. [16] Q.Z. Liu and S.S. Lau, A Review of the Metal-GaN Contact Technology, Solid- State Electronics, vol. 42, no. 5, p. 677, 1997. [17] S.S. Cohen and G.SH. Gildenblat, VLSI Electronics. Academic Press, 1986. [18] Z. Fan, S. Noor-Mohammad, K. Wook, O. Aktas, A.E. Botchkarev, and H. Morkoç, Very Low Resistance Multilayer Ohmic Contact to n-gan, Applied Physics Letters, vol. 68, no. 12, p. 1672, 1996. [19] A.T. Ping, Q. Chen, J.W. Yang, M.A. Asif-Khan, and I. Adesida, The Effects of Reactive Ion Etching-induced Damage on the Characteristics of Ohmic Contacts to n-type GaN, Journal of Electronic Materials, vol. 27, no. 4, p. 261, 1998. [20] S.J. Cai, R. Li, Y.L. Chen, L. Wong, W.G. Wu, S.G. Thomas, and K.L. Wang, High Performance Al x Ga 1 x N/GaN HEMT Improved Ohmic Contacts, Electronics Letters, vol. 34, no. 24, p. 2354, 1998. [21] D. Qiao, L.S. Yu, S.S. Lau, G.J. Sullivan, S. Ruvimov, and Z. Liliental-Weber, Contact Issues of GaN Technology, Materials Research Society Symposium Proceedings, vol. 537, p. G1.5, 1999. [22] D.A. Neamen, Semiconductor Physics and Devices. Irwin, 1992. [23] A.C. Schmitz, A.T. Ping, M.A. Khan, and I. Adesida, Schottky Barrier Heights of

60 REFERENCES Ni, Pt, Pd and Au on n-type GaN, GaN and Related Materials Symposium, p. 831, 1996. [24] K. Lee, M.S. Shur, T.J. Drummond, and H. Morkoç, Current-Voltage and Capacitance-Voltage Characteristics of Modulation-Doped Field Effect Transistors, IEEE Transactions on Electron Devices, vol. 30, no. 3, p. 207, 1983. [25] S. Hiyamizu and T. Mimura, MBE-Grown Selectively Doped GaAs/n-AlGaAs Heterostructures and Their Applications to High Electron Mobility Transistors, Semiconductor Technologies, p. 258, 1982. [26] C. Chen, S.M. Baier, D.K. Arch, and M.S. Shur, A New and Simple Model for GaAs Heterojunction FET Gate Characteristics, IEEE Transactions on Electron Devices, vol. 35, no. 5, p. 570, 1988. [27] Q.Z. Liu, L.S. Yu, F. Deng, S.S. Lau, and J.M. Redwing, Ni and Ni Silicide Schottky Contacts on n-gan, Journal of Applied Physics, vol. 84, no. 2, p. 881, 1998. [28] A.C. Schmitz, A.T. Ping, M.A. Khan, Q. Chen, J.W. Yang, and I. Adesida, Schottky Barrier Properties of Various Metals on n-type GaN, Semiconductor Science and Technology, vol. 11, no. 10, p. 1464, 1996. [29] J. Hilsenbeck, E. Nebauer, J. Würfl, G. Trankle, and H. Obloh, Aging behavior of AlGaN/GaN HFETS with Advanced Ohmic and Schottky Contacts, Electronics Letters, vol. 36, no. 11, p. 980, 2000. [30] E.V. Kalinina, N.I. Kuznetsov, V.A. Dmitriev, K.G. Irvine, and C.H. Carter, Schottky Barriers on n-gan Grown on SiC, Journal of Electronic Materials, vol. 25, no. 5, p. 831, 1996. [31] H. Kawai, M. Hara, F. Nakamura, and S. Imanaga, AlN/GaN Insulated Gate Heterostructure FET with Regrown n + -GaN Ohmic Contact, Electronics Letters, vol. 34, no. 6, p. 592, 1998. [32] P. Hacke, T. Detchprohm, K. Hiramatsu, and N. Sawaki, Schottky Barrier on n-type GaN Grown by Hydride Vapor Phase Epitaxy, Journal of Applied Physics, vol. 63, no. 19, p. 2676, 1993. [33] K. Prabhakaran, T.G. Andersson, and K. Nozawa, Nature of Native Oxide on GaN Surface and its Reaction with Al, Applied Physics Letters, vol. 69, no. 21, p. 3212, 1996. [34] J.A. Bardwell, I. Foulds, B. Lamontagne, H. Tang, J.B. Webb, P. Marshall, S.J. Rolfe, and J. Stapledon, Fabrication of High Performance GaN Modulation Doped Field Effect Transistors, Journal of Vacuum Science and Technology A, vol. 18, no. 2, p. 750, 2000. [35] M.J. Turner and E.H. Rhoderick, Metal-Silicon Schottky Barriers, Solid-State Electronics, vol. 11, no. 3, p. 291, 1968.

Chapter 5 AlGaN/GaN High Electron Mobility Transistors 5.1 Introduction AlGaN/GaN HEMTs have a strong potential for high-power, high-frequency applications. However, several frequency dispersion phenomena can severely limit output power at high frequencies and/or cause undesirable transients that have a wide range of time constants. The objective of the research described in this chapter was to fabricate and characterize AlGaN/GaN HEMTs and to see if these dispersion phenomena could be minimized by adjusting device fabrication. Section 5.3 presents a review of published research on dispersion phenomena in GaNbased FETs. Most of the results indicate charge trapping in the GaN buffer layer and/or at the surface of the device. Both trapping processes cause a significant degradation in RF I-V characteristics when compared to the corresponding DC characteristics. In section 5.4, an optimization of the HEMT processing scheme is presented. The main objective here was to reduce the leakage currents and the amount of dispersion. Compared to the original process, which consisted of the process steps described in the previous chapters, settings had to be changed, steps were added, and the sequential order was modified. The optimized process was used for the fabrication of submicron transistors. Measurement results of these devices are presented in section 5.5. By comparing power data and DC I-V characteristics, it will be shown that, under the used measurement conditions, these devices do not suffer from dispersion. But first we will discuss the principles of operation of a HEMT. In addition to DC performance, we will look at breakdown and high-frequency behavior. Furthermore, this analysis will identify two aspect ratios that are important for obtaining high-performance devices. 61

62 AlGaN/GaN High Electron Mobility Transistors I K H? A C = J A @ H E B J H A C E @ H = E N N C @ H E B J @ A B B + C I 4 I 4 @ + @ C 8 C I ) / =? D = A J, - / 4 @ I / = Figure 5.1: Schematic layout of an AlGaN/GaN HEMT. 5.2 Principles of Operation of the HEMT Consider the AlGaN/GaN HEMT layout in Figure 5.1. The HEMT transistor is formed by applying the ohmic drain and source contacts and the Schottky gate. The analysis of the I-V characteristics will be split into two parts. The first part follows a gradual-channel approach and describes the behavior of the transistor up to saturation [1]. Beyond this point, we will use a drift-region approach, to illustrate the importance of the gate-drain region [2, 3]. The functionality of the transistor is based on controlling the 2DEG. In chapter 4, we have seen that the Schottky gate and 2DEG form a capacitor. Its capacitance density can be computed using: C 2DEG = qσ 2 V a = ɛ AlGaN d eff (5.1) where d eff = d+ d is the effective gate-to-channel separation, which is assumed constant for this analysis. Integrating Eq. (5.1) yields the 2DEG concentration in the chargecontrol regime: qσ 2 = ɛ AlGaN [V GT V x ] = C 2DEG [V GT V x ] d eff (5.2) where V GT = V gs V p, with V gs the gate-source voltage, and V p the pinchoff voltage. The channel voltage (V x ) reflects the voltage in the channel due to the applied drain-source voltage. It causes σ 2 to be dependent on the position along the gate. Near the source, V x will be lower and consequently σ 2 will be higher. Near the drain the opposite holds. Because current transport is mainly due to drift, current continuity requires that the electron velocity (v e ) increases moving from source to drain (σ 2 v e =constant). The electrons experience an electric field that can be found from E x = V x / x 1. The velocity of the electrons is computed using a two-region approach [1], which does not include velocity overshoot effects. For E x 2E s electrons travel at their saturated velocity (v sat ), and for E x < 2E s we have: v e = µ e E x 1 + E x /2E s (5.3) 1 Taking the absolute value here will simplify the equations that will follow.

5.2 Principles of Operation of the HEMT 63 where µ e is the low-field electron mobility and E s = v sat /µ e. Neglecting the drain and source resistances R d and R s, respectively, we can use this model to compute the drainsource current (I ds ) in the linear region for a transistor of length L g and width W g (note that σ 2 v e is constant): I ds = W g L g Lg 0 qσ 2 v e dx = W g L g Lg 0 C 2DEG [V GT V x ] V µ x e x 1 + Vx /2E dx x s = 1 R n 2V GT V ds V 2 ds V ds + 2V L (5.4) where R n = (W g C 2DEG v sat ) 1, V ds the drain-source voltage, and V L = E s L g. Increasing V ds will at some point cause the electrons at the drain-side edge of the channel to reach v sat. The drain-source voltage that marks this point, V ds = V dsat, can be found by combining Eqs. (5.2) and (5.4): From this we find: and I dsat = C 2DEG [V GT V dsat ] W g v sat = 1 R n 2V GT V dsat V 2 dsat V dsat + 2V L (5.5) V dsat = 2V GT V L V GT + 2V L (5.6) V 2 GT V GT + 2V L (5.7) I dsat = 1 R n As mentioned before, the electron density decreases moving from source to drain. When the transistor is in saturation, electrons near the drain-side edge of the channel have very high velocities. The electron density will therefore be relatively low. When the electrons move past the gate, their velocity and density do not instantaneously return to the low-electric field values found in the region between gate and source. Instead, a drift region is formed, denoted by L drift in Figure 5.1, which is characterized by high electric fields, high electron velocities and relatively low electron densities. For GaAs MESFETs, where similar regions develop when the device is in saturation, it has been shown that the behavior of this region is governed by large vertical and horizontal fields [4]. In Figure 5.1, the current through the drift region is characterized by the voltagecontrolled current source 2 (g m V gs). In addition, electrons can be de-confined from the quantum well and effectively bypass the drift region. This process is described by the output resistance (R ds ). Because of high fields in the drift region, most of the applied drain-source voltage beyond saturation will drop over this region. Various techniques like gate recessing, insulated gates and field plates have been used to increase the length of the drift region, which would enhance the breakdown voltage [5]. The drift region also influences high-frequency behavior. For GaAs and InP HEMTs, the following feedback correlation has been determined from experiments [2, 3]: 2 V gs is the voltage over C gs. C gs C gd = 1 + κg m R ds (5.8)

64 AlGaN/GaN High Electron Mobility Transistors where C gd and C gs = W g L g C 2DEG are the gate-drain and gate-source capacitances, respectively, and κ a fitting parameter, which was found to be equal to 0.3 for both technologies. Dividing Eq. (5.8) by C gs exposes the drift capacitance C d : 1 = 1 + κg mr ds C gd C gs C gs (5.9) 1 = 1 + 1 C gd C gs C d (5.10) In Figure 5.1, C d can be interpreted as that part of C gd, which is related to charge storage in the drift region. The last term in Eq. (5.9) can be re-written as: Using a parallel-plate approximation for C d [2]: g m R ds = C gs κc d (5.11) C d = ɛ AlGaNd eff W g L drift (5.12) we find the following scaling rule 3 : g m R ds = 1 κ ( Lg ) ( ) Ldrift d eff d eff (5.13) This relation illustrates the trade-off between gain and high-frequency operation. To obtain a high f t device, the gate length should be minimized. This will not have a deteriorating effect on voltage gain, which at low frequencies is proportional to g m R ds, if the drift region is sufficiently long. A long drift region will also lower the total gate-drain capacitance, which in turn increases f max (see section 5.2.2). 5.2.1 Breakdown One of the most important features of a HEMT is its breakdown voltage. We can distinguish between off-state and on-state breakdown as well as three- or two-terminal breakdown. The two mechanisms responsible for breakdown are thermionic field emission/tunneling of electrons from the gate and impact ionization in the channel. Which of these two dominates depends on the bias conditions and epitaxial structure. Generally, off-state breakdown is dominated by electron tunneling from the gate whereas impact ionization dominates when the device carries a considerable amount of current [6]. To explain the breakdown due to electron tunneling we will use Figure 5.2. It represents a uniformly doped (N D ) AlGaN/GaN HEMT in the off-state (V gs < V p ) with an applied gate-drain voltage V gd1. The channel is depleted as indicated by the grey color. Essentially all electrons under the gate have been swept away by the gate voltage. As a result, a negative mirror charge is formed in the gate metal near the metal-semiconductor junction. If the gate-drain bias is increased to V gd2, the depletion region in the channel 3 Please note that C gs = W g L g C 2DEG = W g L g ɛ AlGaN /d eff.

@ @ 5.2 Principles of Operation of the HEMT 65 I K H? A C = J A @ H = E ) / =, N @, 1 J A C H = J E F = J D / = - C = J A 8 C @ 8 C @ N @ J, - / I F I F I - C = J A #, C = J A -, ) * Figure 5.2: Breakdown due to tunneling: (A) Epitaxial structure showing the location of the depletion region (grey) under pinchoff. (B) The magnitude of the electric field along the integration path, which goes from the gate directly down to the channel and then laterally towards the drain. The two lines relate to two structures with different doping densities. The arrow represents the total charge on the metal gate electrode. The depletion region (x d ) stretches out to the point where E is zero. In this figure, the depletion region corresponds to the lowest doping density (N D ). expands laterally towards the drain. A large portion of these electrons is mirrored in the gate metal, which increases the electric field directly under the gate. This charge distribution is such that the electric field peaks near the drain-side edge. We will follow the analysis by Somerville et al. [7] to analyze the field distribution in the structure. For now, the influence of surface states is not included. The electric field is split in a vertical part under the gate and a lateral part in the channel. The magnitude of the electric field going from gate to drain using this path is illustrated in Figure 5.2B. This figure illustrates the electric field for two different doping densities both having the same electric field directly under the gate (E gate ). The larger density shows a steeper profile 4, which means that less voltage is built up between gate and drain compared to the lower density. The off-state breakdown voltage (V break,off ) is usually defined as the voltage at which a specific gate current, e.g. 1mA/mm, flows. Because the gate current is a strongly increasing function of E gate, the larger density profile will show a smaller breakdown voltage [7]. This analysis has neglected the influence of the source. Using three-terminal simulations and measurements, it has been shown that the electrostatic interaction between source and gate decreases the breakdown voltage [8]. This effect decreases with increasing gate length to x d ratio. Two- and three-terminal breakdown measurements for devices with small gate lengths in combination with low doping densities will therefore show large discrepancies. 4 The gradient in the electric field is proportional to the net charge. Usually, d and t 2DEG are much smaller than x d so that the channel and the AlGaN layer can be considered as one thin strip [7].

66 AlGaN/GaN High Electron Mobility Transistors C = J A 4 C + C @ @ H = E C I 8 C I + C I + @ I 4 @ @ I 4 @ I 4 E C A M J 8 C I 4 I I I K H? A Figure 5.3: HEMT small-signal equivalent circuit. On-state breakdown is usually dominated by impact ionization. It is based on the fact that for electric fields above the critical electric field, electrons gain enough energy to ionize atoms within the channel causing electron-hole generation. This sets up an avalanche effect causing the drain-source current to rise sharply. The holes that are generated in the channel can flow towards the gate causing a negative gate current. The discussion so far did not include surface states. However, they have shown to play a crucial role in the breakdown behavior of AlGaN/GaN HEMTs. Let us return to Figure 5.2, but now omitting the doping in the structure. In chapter 4, it was shown that for undoped structures, a 2DEG can be formed by surface states releasing electrons to cancel the polarization fields. If such a structure is subjected to reverse bias, electrons will again be mirrored in the gate metal. However, in this case they are assumed to tunnel into the surface states in the gate-drain region, as indicated by the arrow in the figure [9]. Because the total amount of charge in the gate is lowered, the electrical field will decrease. As a result, the breakdown voltage will be much higher. This phenomenon is closely related to the virtual gate concept, which will be discussed in section 5.3.2. The extension of the depletion region in AlGaN/GaN HEMTs can be very large resulting in breakdown voltages of about 100V per µm gate-drain separation [10]. Moderately changing the gate-drain separation (from 0.5 to 2µm) to increase the breakdown voltage does not seem to degrade high-frequency performance [11] but could present a significant improvement in output power. 5.2.2 High-Frequency Operation Figure 5.3 illustrates a small-signal model of a HEMT [12]. In this model, C gs describes the charge modulation in the channel due to the gate-source voltage and C gd the feedback. The transconductance (g m = I ds / V gs ) and drain-source resistance (R ds = I ds / V ds ), represent the linearization of I ds whereas τ models the transit time of the electrons under the gate, which in combination with the frequency of the signal (ω), introduces a phase

5.2 Principles of Operation of the HEMT 67 shift in the effective transconductance. The components R s, R g, R d and L s, L gs, L ds, model the contact and metal track resistance and inductive effects of the source, gate and drain, respectively. C ds is a geometric capacitance between source and drain and is often assumed bias independent. The charging resistance (R i ) is related to the channel resistance. Together with C gs it models the distributed gate-source input network. This model can also be used to describe large-signal behavior. But then, each component needs to be determined and modelled for each bias point. Also, extra components are needed to model breakdown behavior. Several parameters can be computed to characterize the high-frequency performance of a device. The cut-off frequency (f t ) marks the frequency at which the short-circuit current gain becomes one. This frequency is sometimes also referred to as transit frequency or gain-bandwidth product. For the circuit in Figure 5.3 we find [13]: g m,extr f t = h 21 Vds =0 = 0 f t = (5.14) 2π(C gs + C gd ) where g m,extr represents the extrinsic transconductance, which is related to the intrinsic transconductance (g m ) by [14]: g m = g m,extr [1 + (R s + R d )/R ds ] 1 R s g m,extr (5.15) If C gd is negligible compared to C gs and the impact of the source and drain resistances is minimal, we can write: f t = g m (5.16) 2πC gs Combining Eq. (5.16) with the transconductance computed using Eq. (5.7), we find for a transistor with a long gate (V L = E s L g V GT ): f t = g m 2πC gs = µ ev GT 2πL 2 g whereas for a short gate (V L = E s L g V GT ) we have: (5.17) f t = v sat 2πL g (5.18) The cut-off frequency determines the maximum switching frequency and is therefore especially important for digital applications. Its value is mainly determined by the intrinsic properties of the device making it a good indicator for material quality. However, for power applications we need to include the effects of the parasitics and the load as well. The maximum frequency of oscillation (f max ) is defined as the frequency at which Mason s unilateral gain [15] equals one. It can be computed using the S-parameters according to: U pg = 1 where K is the Rollet stability factor [16] given by: (S 21 /S 12 ) 1 2 2K S 21 /S 12 2Re (S 21 /S 12 ) = 1 (5.19) K = 1 S 11 2 S 22 2 + S 11 S 22 S 12 S 21 2 2 S 12 S 21 (5.20)

68 AlGaN/GaN High Electron Mobility Transistors For K > 1 the transistor is unconditionally stable 5. This means that the transistor cannot oscillate irrespective of the passive terminations on both input and output. Mason s unilateral gain expresses power gain in a conjugately matched feedback amplifier whose reverse gain has been adjusted to zero by a lossless reciprocal feedback network. The maximum frequency of oscillation represents the highest frequency at which a device can be used for power gain and serve as an active element in an oscillator. Based on the equivalent circuit in Figure 5.3, we can approximate f max by [18]: f max = f t 2 R gs,tot /R ds + 2πf t R g C gd (5.21) where R gs,tot = R g + R i + R s. The ratio f max /f t, which is typically about 2 or higher for AlGaN/GaN HEMTs, gives information about the influence of the output conductance, feedback and parasitics on high-frequency performance. Without the feedback circuit, the maximum available gain (G max ) from an unconditionally stable device can be obtained by conjugately matching both the input and output. It can be approximated by [19]: G max R ds (f t /f) 2 4(R gs,tot + ω t L s /2) + 2ω t C gd R ds (R gs,tot + R g + ωl s ) (5.22) where ω t = 2πf t. This equation shows the 20dB/decade roll-off with frequency. Naturally, to optimize G max we must reduce the parasitics in the device. Especially L s and C gd are important due to the multiplication with ω t. This once again illustrates the importance of the drift region (through C gd ), as discussed in section 5.2. To reduce L s, several advanced fabrication techniques like via-holes or flip-chip mounting can be employed. 5.3 Dispersion Phenomena in AlGaN/GaN HEMTs In chapter 4, the origin of the 2DEG electrons was related to the presence of surface states. These states, as well as other traps inside the structure, can cause dispersive behavior. In this section, we will look at the different dispersion phenomena encountered in GaN-based FETs and how they affect device performance. All the effects mentioned in this section occur in devices irrespective of the substrate material used (sapphire or SiC). During the next discussion we will use the nomenclature as proposed by Binari et al. [20]. 5.3.1 Drain Lag and Buffer-Related Current Collapse As early as 1994, Khan et al. [21] reported on current collapse in an AlGaN/GaN HEMT. Current collapse refers to the strong reduction in current for a given bias condition after a high drain-source bias has been applied. If one would for instance measure I ds at V ds = 1V before and after applying a high drain-source bias, a strong reduction in current could 5 Strictly speaking, this condition is not sufficient but will suffice in most cases. For a more detailed analysis on stability the reader is referred to [17].

5.3 Dispersion Phenomena in AlGaN/GaN HEMTs 69 be seen. As was reported, the current collapse could be minimized by performing the measurement under illumination. Binari et al. [22] showed that the same phenomenon occurs in GaN MESFETs. In addition to illumination, performing the measurements at elevated temperatures also decreased the current collapse. The origin of this effect was thought to be hot-electron trapping in the GaN buffer layer. Klein et al. [23] used a spectroscopic technique to determine the properties of the traps responsible for current collapse in GaN MESFETs. They measured the drainsource current in the dark (I dark ) and under illumination by monochromatic light (I(λ)) and calculated the response function: S(λ) = 1 I(λ) I dark (5.23) Φ(λ) t I dark where Φ(λ) t is the total number of photons incident on the sample per unit area during time t. In [24], the same authors show that this response function is proportional to the photoionization cross-section of the trap if the transistor is operated in the linear regime and the amount of photons that hit a single trap is much smaller than one. By also measuring the current difference as a function of light intensity, two distinctive traps (1.8eV and 2.85eV below the conduction band) could be isolated in the GaN buffer. Similar trap levels were also found by Meneghesso et al. [25]. Using the photoionization technique, it was shown that the traps causing the current collapse in AlGaN/GaN HEMTs had the same energy levels as those in GaN MESFETs [26]. This further indicates that these traps were located in the buffer layer. Current collapse measurements on AlGaN/GaN HEMTs revealed that the effect was more pronounced in devices that had a semi-insulating buffer instead of a conductive one [27]. In addition, surface treatments, e.g. passivation with SiNx, did not influence the current collapse. It was argued that the highly resistive nature of the buffer layer could be caused by traps that are also responsible for the current collapse. In a later publication, Klein et al. [28] showed the correlation between the growth pressure of the buffer layer, carbon incorporation and the density of the deepest trap (2.85eV). Growing the buffer layer at relatively low pressures (< 50Torr) increased carbon incorporation. Preliminary work by Neugebauer et al. shows that carbon may act as a deep acceptor and could consequently compensate donors in n-type material [29]. Secondary ion mass spectroscopy (SIMS) measurements indicated a strong correlation between the concentration of the deepest trap (2.85eV) and the carbon concentration in the buffer layer. The concentration of the lowest trap (1.8eV) increased more gradually with lower growth pressures. This was believed to be related to the higher dislocation densities that occur at lower growth pressures [28]. In AlGaAs/GaAs HEMTs, current collapse is often observed at low temperatures. This effect is attributed to electron trapping in DX-centers in the Si-doped AlGaAs layer [30]. In AlGaN/GaN HEMTs, oxygen is know to cause DX-center-like defects in the AlGaN layer [31]. Using deep-level transient spectroscopy (DLTS), Nozaki et al. [32] found traps in AlGaN/GaN structures with an activation energy of 0.28eV. However, the authors concluded that this value is too small to explain the current collapse phenomenon.

70 AlGaN/GaN High Electron Mobility Transistors Figure 5.4: Current collapse in a 2 40µm AlGaN/GaN HEMT. To determine the I-V characteristics, the drain-source voltage is swept from 0V to a high bias (> 20V) at a constant gate-source voltage. Any subsequent sweep within the time frame of the trapping process, will show a lower current in the low bias region. The time difference between sweeps in this figure was on the order of minutes. Dashed lines indicate the ideal response without current collapse. The traps causing the current collapse can also be studied by looking at the transient response of the drain-source current to a drain-source pulse. This measurement technique is called a drain lag measurement. The drain-source pulse should start at a relatively low level (< 5V), rise to a high level to cause the electron trapping (>20V), and then return to the low voltage state. The time it takes for the current to return to its original value can differ considerably ranging from seconds to hours. From the discussion above, it should be clear that current collapse, sometimes also referred to as drain lag, is caused by traps located in the material. Most of the efforts to reduce this effect are related to the growth of the buffer layer. Because the influence of processing on these traps is minimal, this effect was not studied extensively in this thesis. However, I-V data of fabricated 2x40µm submicron transistors (L g = 370nm) 6 shown in Figure 5.4, show signs of current collapse in the low-bias regime. It clearly degrades the power performance of these devices. Still, it is not the dominant dispersion effect in AlGaN/GaN HEMTs. 5.3.2 Surface-Related Gate Lag and Transient Response. Most HEMT devices that show moderate drain lag, still cannot deliver the output power at RF frequencies that one would expect based on static I-V data. As we will see next, this effect is in most cases related to charge trapping in surface states, although a true consensus has not been achieved yet. A number of terms in literature are used to describe this phenomenon like DC-to-RF dispersion, current slump, current compression, current collapse and gate lag. Some of these terms are also used to describe charge trapping in the buffer layer, which makes it sometimes difficult to discriminate between the two. 6 A more detailed discussion on the properties of these devices will follow in section 5.5.

5.3 Dispersion Phenomena in AlGaN/GaN HEMTs 71 Binari et al. [33] demonstrated a correlation between the measured RF output power and the drain-source current response during a gate lag measurement. In a gate lag measurement, the drain-source voltage is kept at a constant value, while a pulse (typically 1µs wide with a low duty cycle) is applied to the gate. Usually, this pulse is set to drive the transistor from below pinchoff to the on-state (e.g. V gs = 0V). By changing the value of V ds and the maximum voltage of the gate-source pulse, one can reconstruct the I-V characteristics. As demonstrated by the authors, this type of measurement can provide a good indication of the power capabilities of a device. In 1999, Kohn et al. [34] used a large-signal current swing measurement to show drainsource current compression in AlGaN/GaN HEMTs. This measurement is much like a gate lag measurement, but in this case a sinusoidal voltage is applied to the gate instead of a pulse. The maximum drain-source current swing showed a transition frequency in the khz range. In addition to the current swing, the transconductance and gate capacitance (capacitance with drain and source shorted) showed similar behavior. A reduction as much as 50 percent could be seen at high frequencies. Daumiller et al. [35] used the same measurement technique to show that this transition frequency can differ by many orders of magnitude for different devices ranging from 10 4 to 10 10 Hz. Dietrich et al. [36] demonstrated slow drain-source current transient responses after the device had been stressed for several minutes by applying different gate-source voltages with zero drain-source bias. After applying the stress, the device was biased at V gs = 0V and V ds = 0.1V and the drain-source current response was measured. A very slow transient response was measured on the order of minutes. The magnitude of current reduction increased with the magnitude and time of the applied gate-source bias stress prior to the measurement. Green et al. [37] showed that by passivating HEMTs with a 350nm SiNx layer, the microwave output power of these devices could be increased by as much as 100 percent. The transconductance, maximum drain-source current, and breakdown voltage increased 10, 20, and 25 percent, respectively, while the pinchoff voltage showed only a marginal shift of -0.25V. The SiNx layer caused an increase in the gate-drain capacitance, which in turn led to lower values for the small-signal gain, f t and f max. Similar findings were reported by others [38, 39]. Using gate lag measurements, it has been shown that the maximum current of an unpassivated device can be as low as 10 percent of the value that is obtained after passivation [27]. Vetury et al. [40] performed a large-signal current measurement in which the transistor was driven into saturation and pinchoff. The drain-source current waveform showed a decreasing amplitude with time. This decay was attributed to the formation of a virtual gate caused by electron trapping in surface states in the region between gate and drain. These electrons could be injected from the gate metal, a process which is facilitated by the large electric field at the drain-side edge of the gate. Trapped electrons deplete the channel limiting the full current swing that can be obtained. Applying a higher drainsource bias led to a faster formation of the virtual gate and a smaller current swing, while UV illumination cancelled the formation of the virtual gate. The steady-state electron population of the virtual gate is determined by the time constants of the trapping and de-trapping processes, the lateral transport of electrons to the traps, and the frequency of the applied signal. If the applied frequency is well above these constants, large-signal

72 AlGaN/GaN High Electron Mobility Transistors measurements will show a limited current swing, while small-signal measurements may not reveal anything. The latter is the reason why good f t and f max values have been reported for devices suffering from this effect. Koley et al. [41] used scanning kelvin probe microscopy (SKPM) [42] to investigate the surface potential during bias stress measurements. Changes in the bare surface barrier height (equal to changes in the surface potential with a negative sign [41]), can be monitored both in time and place using this technique. As discussed in chapter 4, if the 2DEG is depleted the polarization charges are not cancelled resulting in large electric fields in the AlGaN layer. As a consequence, the separation between the conduction band edge and the Fermi level at the interface (=barrier height) will be high. Drain-source current transients were recorded at V ds = 1V and V gs = 0V. Prior to the measurement, the device was stressed (V ds = 20V and V gs below pinchoff) for 2min. The drain-source current showed a slow recovery to the pre-stress values. Simultaneous SKPM measurements showed a direct correlation between the drain-source current transient and the transient observed in the surface potential. Furthermore, the changes in surface potential were mostly located in the gate-drain area. This further substantiates the possibility that electrons occupy surface states in the gate-drain region thereby forming a virtual gate. It was argued that since there was no current flowing during the bias stress, electrons from the gate are injected into the surface states. This process is facilitated by the high electric fields that exist under pinchoff conditions. Measurements indicated that indeed most of the voltage difference drops within 0.2µm from the gate [41]. Performing the measurements under UV illumination did not show the formation of a virtual gate. Measurements done at elevated temperatures or measurements done on devices passivated with SiNx, showed a significant reduction in the magnitude of the transient. The authors argue that the same effect is responsible for the reduced RF power output often encountered in AlGaN/GaN HEMTs. Although many groups have reported significant improvements in device performance after passivating with SiNx, there is no general framework yet by which this effect can be explained. Vertiatchikh et al. [43] used DLTS measurements on unpassivated Al- GaN/GaN HEMTs to show the presence of two traps. After passivation, the DLTS signal belonging to the most dominant trap was reduced significantly. This implicates that the effect of SiNx is to reduce the surface state density or at least the density of the trap causing the DLTS signal. Other authors argue that the nature of the interface states changes or that Si incorporates as a shallow donor [40]. The positive countercharge of the channel electrons may even have moved into the passivation layer, where it becomes fixed [44]. However, this same passivation layer could introduce trap levels itself, e.g. the K 0 -center in SiNx. This center has been identified in causing power slump in AlGaAs/GaAs power HEMTs [45]. The passivation layer could also prevent the attachment of ionic adsorbates to the surface [40]. The charge of these adsorbates could also lead to the formation of a virtual gate. Not only SiNx has proven to be a suitable candidate for passivation. Other materials like scandium oxide (Sc 2 O 3 ) and magnesium oxide (MgO) have also shown promising results [46]. SiNx has the disadvantage that it contains atomic hydrogen, which could diffuse into the AlGaN layer or gate metal over extended periods of device operation. These other materials do not have this problem.

C @ I 4 + 5.4 Optimization of AlGaN/GaN HEMT Processing 73 1 @ I F K I A @ + 8 @? 1 @ I 8 F K I A 8 @? = C E J K @ A 8 C I 8 F 8 C I 8 ) * J J E A I Figure 5.5: (A) Setup to measure gate lag. Black dots indicate nodes connected to multimeters, grey dots indicate nodes connected to a sampling oscilloscope. (B) Example of typical gate lag curves measured using the oscilloscope. Generally speaking, reliability studies on AlGaN/GaN HEMTs still have to be carried out to investigate whether the passivation techniques used today can withstand high bias stress, temperature and humidity levels. For GaAs-based pseudomorphic HEMTs, degradation in device performance is observed after prolonged stress. This is attributed to electron trapping in the SiNx layer and creation of traps due to hot-electron effects. With the high electric fields in GaN-based devices, these effects could even be worse [20]. 5.4 Optimization of AlGaN/GaN HEMT Processing In the previous chapters we have discussed the individual process steps for the fabrication of an AlGaN/GaN HEMT. In this section, we 7 will combine these steps into one process flow. We naturally have to fine-tune the different steps in order to give the best performance. The main criteria that were used during the optimization were the amount of gate lag, the maximum DC drain-source current and gate leakage. Figure 5.5A illustrates the setup used to analyze gate lag. The gate-source pulses are generated by a voltage pulse source. To provide the necessary DC offset, a voltage source (V dc1 ) is connected using the bias tee construction L 1 and C 1. The drain-source current is determined by measuring the voltage drop over R with a sampling oscilloscope. On the same scope, the gate-source voltage is measured. Capacitor C 2 is needed to supply the current during switching while still maintaining a nearly constant voltage. To determine the amount of gate lag, V gs was biased just below pinchoff and V ds was set to 10V. Pulses of 50ns in width (10% duty cycle) were used to drive V gs to 0V. The drain-source current was determined by inspecting the graph on the oscilloscope. For each measurement, the value for the pulsed current (I ds,pulsed ) was determined just after V gs had reached a steady-state, see Figure 5.5B. We will denote the amount of gate lag as the ratio between I ds,pulsed and I dss (= I ds at 0V DC). Whether a transient in the drain- 7 The work described in the remainder of this chapter was a joint effort between this author and M.C.J.C.M. Krämer, Ph.D. student at the same institute.

74 AlGaN/GaN High Electron Mobility Transistors source current can be seen within the pulse, as shown in Figure 5.5B, depends on the time constants involved. During the different experiments, different shapes were observed ranging from a constant value within the pulse to an almost linear curve starting at t 0. 5.4.1 Process Optimization The transistors used for the optimization described in this section all have a total gate width of 80µm. They consist of two 40µm wide parallel gates, each 2µm long and placed symmetrically between source and drain (drain-source separation is 10µm). Both undoped and doped AlGaN/GaN HEMT structures on sapphire were used. The starting point of the investigation was the following process flow, see Process 1 in Figure 5.6: 1. RIE etching of the mesa (Ar:SiCl 4 =10:10, 40mTorr, 105W, t=7min.) 2. Ti/Al/Ni/Au 30/180/40/150nm ohmic contacts followed by a 900 0 C RTA step for 30s in N 2 ambient. 3. Ni/Au 20/200nm Schottky contacts, in most cases without the NH 4 OH treatment. 4. Ti/Au 20/200nm metal overlay. 5. 100nm SiNx deposition at 250 0 C. For this process the SiH 4 /NH 3 ratio is adjusted such that the final SiNx layer has a dielectric constant (optical) of 1.99 ± 0.01. 6. Opening of the SiNx layer by an Ar:SF 6 plasma 10:10, 40mTorr, 105W, t=3min. This step is needed for probing the transistors. DC and gate lag measurements were carried out before and after the SiNx deposition. The results were very disappointing. All the devices showed severe gate lag (in excess of 50 percent) as well as excessive leakage. On the mask, several circular ohmic and Schottky test structures were present both on the AlGaN layer and the semi-insulating GaN buffer layer. Measurements on these structures revealed that: 1. Before SiNx deposition, the ohmic and Schottky contacts on the GaN buffer behaved normally, i.e. they only showed a small leakage current on the order of a few µa. After deposition, this leakage increased into the ma range. 2. Before and after SiNx deposition, the ohmic and Schottky contacts on the AlGaN behaved normally. This led us to the conclusion that the leakage in the transistor originated from leakage between the probe pads and not from within the intrinsic transistor. The most likely candidate to cause this phenomenon is the RIE etching of the mesa. It could be that the etching process causes too much damage to the GaN surface. Combining this damage with a SiNx layer could well lead to a thin conductive region at the surface. To test this hypothesis, etching tests were carried out using reduced powers. As starting material we used undoped AlGaN/GaN HEMT structures. First we tried to etch

! " #! "! " # $ 5.4 Optimization of AlGaN/GaN HEMT Processing 75 2 4 + - 5 5 2 4 + - 5 5 2 4 + - 5 5! 5 E N 5 E N 5 E N A I = A J? D E ) K F A E C E 5 E N 6 E ) E ) K 6 E ) K Figure 5.6: Evolution of the HEMT process. Process 1: 1) mesa definition by RIE etching 2) ohmic contact evaporation and RTA 3) Schottky contact evaporation 4) Overlay metallization (SiNx passivation) 5) Opening in SiNx for probing. The disadvantages of this process are the large leakage currents through the semi-insulating GaN buffer and the severe amount of gate lag. Process 2: 1) ohmic contact evaporation and RTA 2) mesa definition by RIE etching 3) Schottky and overlay metallization, (SiNx passivation) 4) Opening in SiNx for probing. This is a fast process with improved gate lag but it still suffers from buffer leakage. Process 3: 1) ohmic contact evaporation and RTA 2) mesa definition by RIE etching (SiNx passivation) 3) Schottky (e-beam) lithography followed by an Ar:SF 6 etch to open the SiNx 4) Schottky metallization 5) Opening the SiNx layer for 6) subsequent overlay metallization. This process shows low leakage currents and minimized gate lag.

76 AlGaN/GaN High Electron Mobility Transistors Figure 5.7: Leakage currents for the 105W (left) and 70W (right) etch processes, respectively. The inner ohmic contact had a diameter of 100µm and was separated from the outer contact by 4µm. Table 5.1: Process parameters for the RIE tests. All processes used an Ar:SiCl 4 =10:10 gas mixture at 40mTorr, 20 0 C. The RTA step was carried out at 600 0 C under N 2 ambient for 10min. The etch depth and etch rate are in nm and nm/s, respectively. nr. Power [W] time DC bias [V] etch depth etch rate RTA 1 105 8 30-370 70 8.2 no 2 70 30-288 105 3.5 no 3 30 70-147 N.A. N.A. no 4 105 8 30-370 70 8.2 yes 5 70 30-288 105 3.5 yes mesas of about 100-200nm using an Ar:SiCl 4 plasma at three different powers: 30W, 70W and 105W, see table 5.1. The 30W process did not produce a mesa height that could be measured, so we continued only with the 70W and 105W samples. On the etched GaN surface of these samples circular Ti/Al/Ni/Au ohmic contacts were evaporated, which were subsequently annealed at 900 0 C for 30s. I-V measurements were carried out before and after the deposition of a 100nm SiNx layer, see the curves no RTA in Figure 5.7. The difference in leakage current between the 70W and 105W process prior to deposition can clearly be seen, note the difference in voltage range. Evidentally, the damage caused by the 105W was indeed too large. However, for both processes a significant increase in leakage current can be observed after deposition of SiNx. Annealing processes at moderate temperatures are frequently used to repair surface damage caused by dry etching. To test if this could be beneficial in this case as well, two additional experiments were carried out. These tests were identical to the 70W and 105W processes, only this time the etching was followed by a 10min. RTA step at 600 0 C under a N 2 ambient, see table 5.1. The results of these tests are also indicated in Figure 5.7. Annealing the samples deteriorated leakage behavior seen prior to the deposition of SiNx. In addition, it did not prevent the increase in leakage currents encountered after deposition.

5.4 Optimization of AlGaN/GaN HEMT Processing 77 The next step was to determine if the SiNx thickness was related to the amount of leakage. Several samples were prepared using the 70W process and subsequent evaporation of ohmic contacts. Leakage measurements on the GaN buffer before and after the deposition showed that there is no correlation between the increase in leakage and the SiNx thickness. Furthermore, if the SiNx layer is removed using BHF, the original highly resistive behavior that existed prior to deposition is restored. A sample was also processed upside down to look at the influence of the deposition temperature (250 0 C). A slight increase in current could be measured, but this effect was several orders of magnitude less than the samples that were covered with SiNx. These results are in complete agreement with the work published by Tan et al. [47]. Several pre-deposition treatments were tried to minimize the impact of the deposition on the leakage. Maybe the interplay between an interfacial layer like Ga 2 O 3 and the SiNx was responsible for the increased leakage. Bearing this in mind, we tried a dip in a 10 percent diluted phosphoric acid (H 3 PO 4 ) solution, a 4 min. dip in pure AZ developer, a 4 min. dip in a sodium sulfide (Na 2 S) solution, an in-situ N 2 plasma at 25W for 15s, and combinations of these treatments. Of these tests only the H 3 PO 4 and the N 2 plasma showed consistent improvements compared to the non-treated samples. These preliminary results indicate that the leakage can be influenced by a suitable pre-treatment. This topic was not pursued in more detail because the amount of leakage did not pose a problem at that time. To make use of the findings mentioned above, the SiNx deposition process was modified so that it included the in-situ N 2 plasma. In the previous experiments we have seen that heat treatments deteriorate leakage behavior at different stages of the process. One possible reason could be that interfacial layers are modified or formed at the surface of the GaN, or that the surface itself is modified. The latter has been demonstrated by RTA experiments using high temperatures > 800 0 C [48]. The most severe heat treatment during the fabrication process is of course the annealing step for the ohmic contacts. It would therefore be very interesting to see if the leakage current prior to the deposition of SiNx can be influenced by a surface treatment. To this end, a sample was fabricated identical to the samples used in previous experiments. After the annealing process of the ohmic contacts, a leakage current was measured on the order of a few µa. To reduce the leakage current the entire sample was etched for 30s in a 20W RIE Ar plasma, which can be considered to be a very mild plasma (DC bias=-167v). Due to this etch, the leakage current had dropped a few orders of magnitude. Annealing the same sample restored the leakage current, which was later on removed by an identical Ar plasma. Although the current levels are relatively small, these findings confirm the statement that surface treatments are crucial for these devices. From the experiments discussed above, we have seen that there is a strong relationship between surface treatment and leakage current. Because gate lag is attributed to the dynamics of charging the surface, we expect a similar relationship to hold for the dispersion behavior. To investigate this, a new process was developed that allowed a transistor to be made using only 4 mask layers, see process 2 in Figure 5.6. In this process, the ohmic contacts are processed before the mesa. There were two reasons for this change. Firstly, we wanted to avoid that the etched surface is subjected to thermal treatments because we have seen that this increases leakage. Secondly, we wanted to avoid contamination of the surface by the masking layer of the etching process, in our case AZ4533 photoresist,

78 AlGaN/GaN High Electron Mobility Transistors J M A A A H )!! "! * 0. Figure 5.8: Example of an experiment in which each of the 4 transistor modules sees a different process flow. Figure 5.9: Comparison between I dss and I ds,pulsed for a device in module 2 of sample V1 10 before passivation. or contamination by etching remnants. This possible contamination could react with the surface during the high-temperature annealing step. Also, the annealing temperature was lowered to 800 0 C to avoid degradation of the crystallinity of the material [48]. By increasing the annealing time to 2min., decent ohmic contacts could still be obtained (R c 0.6Ωmm). The new mask set for this process contained 4 modules having 91 transistors each and was specifically designed for 1cm 2 samples. No changes were made in the layout of the transistor compared to the old mask. The approach that was followed for reducing the gate lag was based on the hypothesis that the surface should be free of contaminants. Furthermore, the most crucial point in the process flow in which contaminants can be incorporated in the semiconductor material, apart from the material growth itself, is the high-temperature annealing step for the ohmic contacts. If contaminants react with the surface or form a coating, they could prevent effective passivation by the SiNx. Several experiments were carried out to test the influence of cleaning treatments on the amount of gate lag. These treatments were applied either at the start of the processing, or just before the RTA step for the ohmic contacts. To make a good comparison between the different processes, and to exclude sample to sample spread, we needed to combine different processes on one sample. For instance, a tweezer was used to hold the sample such that only 2 modules are dipped in BHF, see Figure 5.8. For the etching experiments, some of the modules were covered by a piece of sapphire. This way, the covered modules were not etched nor were they covered with a protective coating like SiNx or photoresist. The latter is important, because we wanted to keep the surface of the modules as clean as possible. Although a large number of experiments were carried out, we will focuss on the series of experiments that led to the development of a new process that shows strongly reduced gate lag. The first experiment involved an undoped AlGaN/GaN structure, which was given two treatments before the RTA step for the ohmic contacts. Two RIE etching processes were done, a pure Ar plasma, and a SF 6 :SiCl 4 plasma. A piece of sapphire was used for masking. For each etching process this masking material was moved, so each module had

5.4 Optimization of AlGaN/GaN HEMT Processing 79 Table 5.2: Overview of treatments for each module. BHF represents a 1min. dip in BHF, done at the start of the process, Ar an Ar plasma just before the RTA step for the ohmic contacts (settings: 10sccm, 40mTorr, 20W, t=30s, DC bias=-167v) and SF 6 :SiCl 4 a SF 6 :SiCl 4 plasma (settings: 3:10sccm, 40mTorr, 20W, t=1min., DC bias=-60v) also done before the RTA step. Y=applied, N=not applied. vendor sample module BHF Ar SF 6 :SiCl 4 1 10 1 n n n 1 10 2 n y n 1 10 3 n n y 1 10 4 n y y 2 6 1 n n n 2 6 2 y n n 2 6 3 n n n 2 6 4 y n n 2 11 1 n n n 2 11 2 y n n 2 11 3 n y n 2 11 4 y y n 1 15 1 n n n 1 15 2 y n n 1 15 3 n y n 1 15 4 y y n 3 6 1 n n n 3 6 2 y n n 3 6 3 n y n 3 6 4 y y n a different process flow. More details on the processing, as well as a complete overview of this and other experiments, can be found in table 5.2. The transistor modules were characterized before and after the SiNx passivation. Figure 5.9 shows a comparison between I dss and I ds,pulsed before passivation. Gate lag is clearly visible in the entire drain-source bias region. Also, the knee voltage (V k ) is shifted to higher values. How the amount of gate lag is affected by the different treatments is shown in Figure 5.10 (graph on the left). Each module is represented by 4 vertical bars, adding up to 16 bars for the entire sample. The white dashed bar (outer left) represents I dss, the gray dashed bar to its right illustrates I ds,pulsed. The two bars to the right represent the same quantities but after passivation, i.e. the white and gray bar represent I dss and I ds,pulsed after passivation, respectively. The vertical stripes represent the ±1 standard deviation (2σ std ) intervals that were calculated using 12 transistors in each module 8. 8 In each corner of the module three transistors were measured.

80 AlGaN/GaN High Electron Mobility Transistors Figure 5.10: Results for sample V1 10 (left) and V2 6 (right), respectively. The dashed bars represent I dss (white) and I ds,pulsed (gray) before passivation, the corresponding clear bars represent the same quantities after passivation. From this graph, several observations can be made: 1. All the modules show a large amount of gate lag before passivation. This is especially true for the modules that were not given the Ar plasma treatment (M1 and M3). 2. After passivation, both I dss and I ds,pulsed increase. Gate lag is still visible for M1 and M3, i.e. I ds,pulsed (gray) is smaller than I dss (white), but for M2 and M4 it has vanished. The absence of self-heating causes I ds,pulsed to be higher than the corresponding I dss. 3. The Ar plasma (without the SF 6 :SiCl 4 plasma), not only reduces gate lag, but also reduces the spread in results across the module. In a second experiment, the influence of a BHF dip at the start of the processing was investigated. This was also done using an undoped AlGaN/GaN HEMT structure though from a different vendor. The BHF dip was applied to modules M2 and M4, whereas M1 and M3 were left untreated, see table 5.2. This resulted in two different processes on one sample. The graph on the right in Figure 5.10 shows that the BHF dip resulted in a slight improvement in uniformity and also improved gate lag behavior. Quantitatively however, the results from M2 and M4 are not consistent. Next, the BHF dip and the Ar plasma treatments were combined on one sample. In these experiments M1 was left untreated, M2 was given the BHF dip, M3 the Ar plasma, and M4 the BHF dip combined with the Ar plasma. This experiment was carried out on three different samples from three different vendors, see table 5.2. One of these samples, V3 6, was a doped AlGaN/GaN structure whereas the other two were undoped. The results from these experiments, shown in Figure 5.11, show a fairly consistent picture. The Ar-only treatment (M3) resulted in virtually dispersion-free transistors in all three cases, again with a low 2σ std interval. Even lowering the off-state bias of the pulsed measurement to values below -15V, did not result in changes in I ds,pulsed. The combination of the BHF dip and the Ar plasma does not give any advantages compared to the Ar-only

5.4 Optimization of AlGaN/GaN HEMT Processing 81 Figure 5.11: Results for samples V1 15 (upper left), V2 11 (upper right), and V3 6 (lower left), as well as the leakage currents (lower right) for these samples (b)efore and (a)fter passivation. M1=untreated, M2=BHF, M3=Ar-only, and M4=Ar+BHF. process. For the modules that were not treated with the Ar plasma, the results are not so consistent. Not treating the sample only gave good results for the doped structure. To determine whether this is related to the doping of the AlGaN layer, much more samples need to be processed. It should however be noted that if the AlGaN layer is doped, not all of the electrons in the 2DEG originate from surface states. This could reduce the gate lag somewhat. Doping the structure does however come with its disadvantages like a lower breakdown voltage, higher gate leakage, and troublesome pinchoff behavior. During the previous experiments we did not look at the leakage currents. It is important to know if there is a correlation between these currents and the treatments mentioned above. The leakage current is defined as the current supplied by the voltage source connected to the drain, V dc2 in Figure 5.5A, under pinchoff conditions. This current was found to be more or less linearly proportional to the drain-source voltage. This would again indicate leakage between the contact pads. The pads are on the semi-insulating GaN buffer layer that is exposed by RIE etching after all the treatments have been applied. It is therefore unlikely that a correlation exists between treatment and leakage current. This is confirmed by measurements as illustrated in Figure 5.11 (lower right). The leakage current measured on the three samples used in the previous experiment is plotted versus

82 AlGaN/GaN High Electron Mobility Transistors module number together with the 2σ std interval. For each module we have 6 bars, 2 for each sample (before and after passivation). If there is a correlation between leakage and treatment, we expect that the leakage current consistently shows either a maximum or a minimum for a given treatment/module. This however is not the case. One thing that can be noticed is the high leakage currents for the doped structure (V3 6). All the devices processed so far suffered from a considerable amount of leakage. This is most likely related to the substrate. Next, a new process will be presented that solves this problem, while still maintaining excellent dispersion behavior. 5.5 Submicron HEMTs In the optimized process described in the previous section, devices were passivated after the last metal step. These devices all had a fat gate (L g = 2µm), which limits the frequency response. We therefore needed to try the process using devices that had submicron gate lengths. Instead of optical lithography, we used e-beam lithography to fabricate the submicron gates. This technique requires a different kind of resist called poly(methyl methacrylate) (PMMA), which needs to be baked at higher temperatures (175 0 C) than photoresists. The general idea developed in the previous section is that we must try to keep the surface clean and avoid heat treatments of contaminated devices. Baking the PMMA under these conditions could therefore have a detrimental effect on device performance. We therefore modified the process to avoid this problem. In this new process, process 3 in Figure 5.6, the SiNx passivation step was done directly after annealing the ohmic contacts. PMMA resist, which is applied after the passivation, is therefore not in direct contact with the semiconductor surface and can therefore not cause any contamination. After e-beam exposure and resist development, a mild Ar:SF 6 plasma is used to etch openings in the SiNx layer. Directly after this, the Ni/Au Schottky gates are evaporated. The same plasma etch is used to make the openings for the subsequent metal overlay step. Because the openings are fully enclosed by the ohmic contacts, there is no direct contact between the metal overlay and the etched GaN buffer. This should lead to lower substrate leakage currents. A disadvantage of this process is that we have no means of examining the performance of devices before passivation. Using this process, submicron HEMTs were fabricated on undoped AlGaN/GaN structures on sapphire. These transistors had a gate length of 370nm and a gate-source and gate-drain separation of 1 and 2µm, respectively. Figures 5.12 and 5.13 illustrate typical I-V characteristics for these devices. The measurement time for each bias point was sufficiently long to allow the device to reach a steady temperature. Measurements done using faster times (1-10ms) showed 20 percent higher values for the maximum transconductance and drain-source current. Figures 5.14 and 5.15 show the high-frequency response of these devices. The threeterminal off-state breakdown voltage for these devices was on the order of 80V. Although these numbers are not state-of-the art, they are comparable to published results [49]. The results for the pulsed measurements are displayed in Figure 5.16. No significant amount of dispersion can be seen. In this figure two other currents are shown, the gate-

5.5 Submicron HEMTs 83 Figure 5.12: I ds and g m versus V gs for different values of V ds. Figure 5.13: I ds versus V ds for different values of V gs. Figure 5.14: Calculation of f t and f max. Figure 5.15: f t and f max for different bias conditions. Figure 5.16: Performance after passivation. The amount of gate lag is negligible and the leakage and pinchoff currents are acceptable. Figure 5.17: Power performance at 4GHz, V gs = 6V, V ds =26V. Peak power corresponds to 2.9W/mm class AB.

84 AlGaN/GaN High Electron Mobility Transistors leakage current and the pinchoff current. The latter is the drain-source current when the device is pinched off. It is similar to the leakage current mentioned in the previous section, though this current does not have the large substrate leakage components due to the isolating SiNx underneath the contact pads. Because the devices show negligible dispersion, it is interesting to see how they behave under RF conditions. To investigate this, devices were load-pulled at 4GHz using an active load-pull setup developed at TNO Physics Electronics Laboratories, see Figure 5.17. A maximum output power density of 2.9W/mm was achieved with a gain of 15dB. Even higher output powers (3.5W/mm) could be measured. However, at these levels, the device starts to degrade irreversibly and subsequent measurements show a severe drop in output power. It should also be noted that this power figure, as well as most figures presented in literature, are determined at a high gain compression point. If these devices are to be used in highly linear systems, much lower powers must be used. Based on the I-V data in Figure 5.13, we would expect a maximum output power in class A operation of: P out = 1 4 (V ds V k )I ds,max = 1 (26 7) 0.7 = 3.3W/mm (5.24) 4 where I ds,max was taken at V gs = 1.5V. This value comes very close to the measured output power, which further confirms the statement that, under the used measurement conditions, these devices are virtually dispersion-free. 5.6 Summary and Discussion The RF output power of AlGaN/GaN HEMTs can be significantly different from that what can be expected judging from the static I-V curves. The main reason for these dispersion phenomena is charge trapping at the surface and/or in the buffer layer. Traps in the buffer layer are related to material growth and are therefore difficult to manipulate during device processing. However, trapping processes at the surface can be reduced by a suitable passivation. In this chapter, a new process for HEMT fabrication was developed. One of the most important steps in this process is the application of an Ar plasma prior to the annealing step for the ohmic contacts. Using this step, as well as many other modifications to the original process, submicron transistors were processed that produced 2.9W/mm output power at 4GHz with 15dB gain. This power corresponds to the static I-V curves, which indicates that, under the used measurement conditions, the amount of dispersion in these devices is negligible. The question remains why the Ar plasma treated devices show much better behavior than the untreated devices and why the SiNx passivation prevents the formation of a virtual gate. Using DLTS measurements, it has been shown that the defect density at the surface decreases after passivation with SiNx [43]. The extent in which the passivant is able to reduce the number of defects will most likely depend on the nature of the surface before passivation. A reason why the Ar plasma provides such an improvement could be that it prepares the surface for effective passivation by removing contaminants or other

REFERENCES 85 irregularities, which else might have caused unwanted reactions with the surface under the high temperatures of the annealing process. If the passivation would eliminate all the traps at the surface, there would be a charge imbalance. However, if the passivant carries a fixed positive charge, this balance could be restored. The electrons in the 2DEG would in this case come from the source and drain contacts. It might also be that the passivation modifies the trapping and de-trapping time constants of the traps, i.e. their energy level, so that they are able to respond to the applied signals without delay. However, it should be noted that a change in time constants alone is not sufficient. The transport of charges from and to these traps should also be sufficiently fast. Unfortunately, based on the experimental work described in this chapter, it is impossible to rule out any of the possible arguments mentioned above. References [1] B.J. Moon, Y.H. Buyn, K. Lee, and M. Shur, New Continuous Heterostructure Field-Effect-Transistor Model and Unified Parameter Extraction Technique, IEEE Transactions on Electron Devices, vol. 37, no. 4, p. 908, 1990. [2] E. Kohn and J. Dickmann, Carrier Confinement and Feed-Back Correlation in In- AlAs/InGaAs HEMTs on InP Substrate, Indium Phosphide and Related Materials Conference Digest, p. 296, 1991. [3] E. Kohn, S. Strahle, D. Geiger, and U. Erben, High Field Drift Domains in GaAs and InP Based Heterostructure Field Effect Devices, Proceedings of the IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, p. 411, 1993. [4] S.H. Wemple, W.C. Niehaus, H.M. Cox, J.V. Dilorenzo, and W.O. Schlosser, Control of Gate-Drain Avalanche in GaAs MESFETs, IEEE Transactions on Electron Devices, vol. 27, no. 6, p. 1013, 1980. [5] H. Xing, Y. Dora, A. Chini, S. Heikman, S. Keller, and U.K. Mishra, High Breakdown Voltage AlGaNGaN HEMTs Achieved by Multiple Field Plates, IEEE Electron Device Letters, vol. 25, no. 4, p. 161, 2004. [6] M.H. Somerville, R. Blanchard, J.A. del Alamo, K.G. Duh, and P.C. Chao, On-State Breakdown in Power HEMT s: Measurements and Modeling, IEEE Transactions on Electron Devices, vol. 46, no. 6, p. 1087, 1999. [7] M.H. Somerville and J.A. del Alamo, A Model for Tunneling-Limited Breakdown in High-Power HEMTs, International Electron Devices Meeting, p. 35, 1996. [8] M.H. Somerville, J.A. del Alamo, and P. Saunier, Off-State Breakdown in Power phemt s: The Impact of the Source, IEEE Transactions on Electron Devices, vol. 45, no. 9, p. 1883, 1998. [9] N.Q. Zhang, B. Moran, S.P. DenBaars, U.K. Mishra, X.W. Wang, and T.P. Ma, Effects of Surface Traps on Breakdown Voltage and Switching Speed of GaN Power Switching HEMTs, IEDM Digest, p. 589, 2001. [10] R. Vetury, Y.F. Wu, P.T. Fini, G. Parish, S. Keller, S.P. DenBaars, and U.K. Mishra, Direct Measurement of Gate Depletion in High Breakdown (405V) AlGaN/GaN

86 REFERENCES Heterostructure Field Effect Transistors, International Electron Devices Meeting, p. 55, 1998. [11] A.V. Vertatchikh and L.F. Eastman, Effect of Drain-to-Source Spacing of Al- GaN/GaN Transistor on Frequency Response and Breakdown Characteristics, Electronics Letters, vol. 39, no. 11, p. 876, 2003. [12] R. Singh and C.M. Snowden, Small-Signal Characterization of Microwave and Millimeter-Wave HEMT s Based on a Physical Model, IEEE Transactions on Microwave Theory and Techniques, vol. 44, no. 1, p. 114, 1996. [13] T. Enoki, S. Sugitani, and Y. Yamane, Characteristics Including Electron Velocity Overshoot for 0.1 µm Gate Length GaAs SAINT MESFET s, IEEE Transactions on Electron Devices, vol. 37, no. 4, p. 935, 1990. [14] S.Y. Chou and D.A. Antoniadis, Relationship Between Measured and Intrinsic Transconductances of FET s, IEEE Transactions on Electron Devices, vol. 34, no. 2, p. 448, 1987. [15] S.J. Mason, Power Gain in Feedback Amplifiers, M.I.T. Research Lab of Electronics, tech. report, vol. 257, p. 20, 1953. [16] J.M. Rollet, Stability and Power-Gain Invariants of Linear Twoports, IRE Transactions on Circuit Theory, vol. 9, p. 29, 1962. [17] M.W. Medley, Microwave and RF Circuits. Artech House, 1992. [18] J.M. Golio, Microwave MESFETs and HEMTs. Artech House, 1991. [19] J.L.B. Walker, High-Power GaAs FET Amplifiers. Artech House, 1993. [20] S.C. Binari, P.B. Klein, and T.E. Kazior, Trapping Effects in GaN and SiC Microwave FETs, Proceedings of the IEEE, vol. 90, no. 6, p. 1048, 2002. [21] M.A. Khan, M.S. Shur, Q.C. Chen, and J.N. Kuznia, Current/Voltage Characteristics Collapse in AlGaN/GaN Heterostructure Insulated Gate Field Effect Transistors at High Drain Bias, Electronics Letters, vol. 30, no. 25, p. 2175, 1994. [22] S.C. Binari, W. Kruppa, H.B. Dietrich, G. Kelner, A.E. Wickenden, and J.A. Freitas, Fabrication and Characterization of GaN FETs, Solid-State Electronics, vol. 41, no. 10, p. 1549, 1997. [23] P.B. Klein, J.A. Freitas, S.C. Binari, and A.E. Wickenden, Observation of Deep Traps Responsible for Current Collapse in GaN Metal-Semiconductor Field-Effect Transistors, Applied Physics Letters, vol. 75, no. 25, p. 4016, 1999. [24] P.B. Klein, S.C. Binari, J.A. Freitas, and A.E. Wickenden, Photoionization Spectroscopy of Traps in GaN Metal-Semiconductor Field-Effect Transistors, Journal of Applied Physics, vol. 88, no. 5, p. 2843, 2000. [25] G. Meneghesso, A. Chini, E. Zanoni, M. Manfredi, M. Pavesi, B. Boudart, and C. Gaquiere, Diagnosis of Trapping Phenomena in GaN MESFETs, International Electron Devices Meeting, p. 389, 2000. [26] P.B. Klein, S.C. Binari, K. Ikossi, A.E. Wickenden, D.D. Koleske, and R.L. Henry, Investigation of Traps Producing Current Collapse in AlGaN/GaN High Electron Mobility Transistors, Electronics Letters, vol. 37, no. 10, p. 661, 2001. [27] S.C. Binari, K. Ikossi, J.A. Roussos, W. Kruppa, D. Park, H.B. Dietrich, D.D.

REFERENCES 87 Koleske, A.E. Wickenden, and R.L. Henry, Trapping Effects and Microwave Power Performance in AlGaN/GaN HEMTs, IEEE Transactions on Electron Devices, vol. 48, no. 3, p. 465, 2001. [28] P.B. Klein, S.C. Binari, K. Ikossi, A.E. Wickenden, D.D. Koleske, and R.L. Henry, Current Collapse and the Role of Carbon in AlGaN/GaN High Electron Mobility Transistors Grown by Metalorganic Vapor-Phase Epitaxy, Applied Physics Letters, vol. 79, no. 21, p. 3527, 2001. [29] J. Neugebauer and C.G. Van de Walle, Defects and Doping in GaN, International Conference on the Physics of Semiconductors, vol. 3, p. 2327, 1995. [30] Y. Hori, M. Kuzuhara, N. Samoto, and T. Itoh, Bias Dependent Collapse and Its Recovery Phenomenon in AlGaAs/GaAs 2DEGFETs at Low Temperatures, IEEE Transactions on Electron Devices, vol. 39, no. 12, p. 2720, 1992. [31] M.D. McCluskey, N.M. Johnson, C.G. Van de Walle, D.P. Bour, and M. Kneissl, Metastability of Oxygen Donors in AlGaN, Physics Review Letters, vol. 80, no. 18, p. 4008, 1998. [32] S. Nozaki, H. Feick, and E.R. Weber, Compression of the DC Drain Current by Electron Trapping in AlGaN/GaN Modulation Doped Field-Effect Transistors, Applied Physics Letters, vol. 78, no. 19, p. 2896, 2001. [33] S.C. Binari, K. Ikossi-Anastasiou, W. Kruppa, H.B. Dietrich, G. Kelner, R.L. Henry, D.D. Koleske, and A.E. Wickenden, Correlation of Drain Current Pulsed Response with Microwave Power Output in AlGaN/GaN HEMTs, Wide Bandgap Semiconductors for High Power, High Frequency and High Temperature Applications Symposium, vol. 572, p. 541, 1999. [34] E. Kohn, I. Daumiller, P. Schmid, N.X. Nguyen, and C.N. Nguyen, Large Signal Frequency Dispersion of AlGaN/GaN Heterostructure Field Effect Transistors, Electronics Letters, vol. 35, no. 12, p. 1022, 1999. [35] I. Daumiller, D. Theron, C. Gaquière, A. Vescan, R. Dietrich, A. Wieszt, H. Leier, R. Vetury, U.K. Mishra, I.P. Smorchkova, S. Keller, N.X. Nguyen, C. Nguyen, and E. Kohn, Current Instabilities in GaN-Based Devices, IEEE Electron Device Letters, vol. 22, no. 2, p. 62, 2001. [36] R. Dietrich, A. Vescan, A. Wieszt, H. Leier, K.S. Boutros, J.M. Redwing, K. Kornitzer, R. Freitag, T. Ebner, and K. Thonke, Effect of Illumination on the Electrical Characteristics of AlGaN/GaN FETs, Physica Status Solidi A, vol. 176, no. 1, p. 209, 1999. [37] B.M. Green, K.K. Chu, M. Chumbes, J.A. Smart, J.R. Shealy, and L.F. Eastman, The Effect of Surface Passivation on the Microwave Characteristics of Undoped AlGaN/GaN HEMTs, IEEE Electron Device Letters, vol. 21, no. 6, p. 268, 2000. [38] J.S. Lee, A. Vescan, A. Wiestz, R. Dietrich, H. Leier, and Y.S. Kwon, Small Signal and Power Measurements of AlGaN/GaN HEMT with SiN Passivation, Electronics Letters, vol. 37, no. 2, p. 130, 2001. [39] W. Lu, V. Kumar, R. Schwindt, E. Piner, and I. Adesida, A Comparative Study of Surface Passivation on AlGaN/GaN HEMTs, Solid-State Electronics, vol. 46, no. 9, p. 1441, 2002.

88 REFERENCES [40] R. Vetury, N.Q. Zhang, S. Keller, and U.K. Mishra, The Impact of Surface States on the DC and RF Characteristics of AlGaN/GaN HFETs, IEEE Transactions on Electron Devices, vol. 48, no. 3, p. 560, 2001. [41] G. Koley, V. Tilak, and L.F. Eastman, Slow Transients Observed in AlGaN/GaN HFETs: Effects of SiN x Passivation and UV Illumination, IEEE Transactions on Electron Devices, vol. 50, no. 4, p. 886, 2003. [42] G. Koley and M.G. Spencer, Surface Potential Measurements on GaN and Al- GaN/GaN Heterostructures by Scanning Kelvin Probe Microscopy, Journal of Applied Physics, vol. 90, no. 1, p. 337, 2001. [43] A.V. Vertiatchikh, L.F. Eastman, W.J. Schaff, and T. Prunty, Effect of Surface Passivation of AlGaN/GaN Heterostructure Field-Effect Transistor, Electronics Letters, vol. 38, no. 8, p. 388, 2002. [44] T.R. Prunty, J.A. Smart, E.M. Chumbes, B.K. Ridley, L.F. Eastman, and J.R. Shealy, Passivation of AlGaN/GaN Heterostructures with Silicon Nitride for Insulated Gate Transistors, Proceedings of the IEEE/Cornell High-Performance Devices Conference, p. 208, 2000. [45] J.C.M. Hwang, Relationship between Gate Lag, Power Drift, and Power Slump of Pseudomorphic High Electron Mobility Transistors, Solid-State Electronics, vol. 43, no. 9, p. 1325, 1999. [46] B. Luo, J.W. Johnson, B.P. Gila, A.H. Onstine, C.R. Abernathy, F. Ren, S.J. Pearson, A.G. Baca, A.M. Dabiran, A.M. Wowchack, and P.P. Chow, Surface Passivation of AlGaN/GaN HEMTs using MBE-grown MgO or Sc 2 O 3, Solid-State Electronics, vol. 46, no. 4, p. 467, 2002. [47] W.S. Tan, G. Hill, P.A. Houston, M.W. Low, P.J. Parbrook, and R.J. Airey, The Effect of Dielectric Stress on the Electrical Characteristics of AlGaN/GaN Heterostructure Field-Effect Transistors, International Symposium on Electron Devices for Microwave and Optoelectronic Applications, p. 130, 2002. [48] C.F. Zhu, W.K. Fong, B.H. Leung, C.C. Cheng, and C. Surya, Effects of Rapid Thermal Annealing on the Structural Properties of GaN Thin Films, IEEE Transactions on Electron Devices, vol. 48, no. 6, p. 1225, 2001. [49] L.F. Eastman, V. Tilak, B.M. Green, E.M. Chumbes, R. Dimitrov, H. Kim, O.S. Ambacher, N. Weimann, T. Prunty, M. Murphy, W.J. Schaff, and J.R. Shealy, Undoped AlGaN/GaN HEMTs for Microwave Power Amplification, IEEE Transactions on Electron Devices, vol. 48, no. 3, p. 479, 2001.

Chapter 6 Passive Components on AlN 6.1 Introduction Generally, a high-power amplifier consists of multiple transistors. These devices have to be connected to construct a circuit. Figure 6.1 presents an example of a two-stage HPA with two transistors in parallel in the second stage. In this circuit passive components are needed for two important reasons: 1) to provide the biasing to the active devices and 2) to provide a matching between different impedance levels. As already mentioned in chapter 1, losses in these circuits should be as low as possible to avoid severe degradation in PAE. In this chapter, some important issues for passive components will be demonstrated by investigating several matching networks. In addition, we will address the problem of choosing the most suitable technology in which to realize these components. 6.2 Matching Networks Consider a device with output impedance Z out that has to be matched to a device with input impedance Z in. We will assume that both impedances are real. Not all of the E J A H I J = C A = J? D E C E F K J > E = I K J F K J 0-6 E F K J = J? D E C K J F K J = J? D E C Figure 6.1: Schematic illustration of a two-stage HPA. 89

90 Passive Components on AlN available power will be transferred to the second device if the devices are not matched. In the next two subsections, two different approaches are presented to solve this problem. 6.2.1 Quarter-Wavelength Transformer The quarter-wavelength transformer makes use of the fact that voltage and current in a waveguide are travelling waves, see Appendix A.2: v(z) = v 0 ( c + e γz + c e +γz) (6.1) i(z) = v 0 Z 0 ( c + e γz c e +γz) (6.2) where Z 0 is the characteristic impedance of the line, γ the propagation constant, c + and c complex constants, and v 0 the voltage normalization. At z = 0, we connect a waveguide of length l to a device with input impedance Z in. Using Eqs. (6.1) and (6.2) and the condition v = Z in i at z = 0, we find: c = Z in Z 0 Z in + Z 0 c + = Γc + (6.3) where Γ is called the reflection coefficient. For a match, the impedance seen at the beginning of the waveguide (z = l) has to equal Z out : Z out = v( l) i( l) = Z c + e γl + Γc + e γl 0 (6.4) c + e γl Γc + e γl If we assume that the waveguide is lossless and choose its length to be a quarter of a wavelength ( 1 λ), we find: 4 Zout = Z2 0 (6.5) Z in Choosing Z 0 according to this relation, we can obtain a perfect match at the frequency for which l = 1/4λ. The characteristic impedance depends on the geometry of the waveguide. Choosing a particular Z 0 for matching purposes can sometimes require impractical dimensions. For instance, in coplanar waveguide technology, a high characteristic impedance requires small metal tracks. This causes problems in the output stage of the HPA where large currents flow. Another drawback of this method is related to size. For a coplanar waveguide on AlN, which will be discussed later on, a quarter of a wavelength equals 3.6mm at 10GHz. These large lengths result in high losses and large chip areas. In conclusion, for X-band amplifiers we must look for other matching options. 6.2.2 L-type Matching Networks Consider the circuit depicted in Figure 6.2. It represents the same matching problem as before. For a match, the impedance seen into the circuit has to equal Z out : Z out = jωl + Z in 1 + jωcz in (6.6)

+ 6.2 Matching Networks 91 K J E Figure 6.2: L-type matching network. A device with output impedance Z out is matched to a device with input impedance Z in. Remembering that both Z out and Z in are real, we can split this equation in a real and imaginary part: Z out = Z in 1 + ω 2 C 2 Z 2 in (6.7) From Eq. (6.7), we can solve for C: jωl = jωcz2 in 1 + ω 2 C 2 Z 2 in (6.8) C = 1 nt 1 ωz out n 2 T (6.9) where n T = Z in /Z out is the transformation ratio 1. Combining this with Eq. (6.8) yields: L = Z out nt 1 (6.10) ω For a given frequency, a perfect match can be obtained by choosing the component values according to these relations. The bandwidth of this type of network decreases strongly with increasing n T. This can be solved by placing several networks in series. Figure 6.3 presents an example of how the L-type matching networks can be applied in the output matching stage of the HPA mentioned in section 6.1. In this figure, the two HEMTs are represented by a parallel connection of the large-signal output resistance (100Ω) and the output capacitance (0.8pF) in series with the drain inductance (50pH), feedback by the gate-drain capacitance is neglected 2. Because the layout is symmetrical, only the upper part of the circuit will be discussed. The first part of the matching network consists of shunt inductor L BIAS that cancels the reactive part of the impedance seen into the transistor. The combination of this inductor and the FET results in a real impedance of 71Ω. Biasing of the FETs is done 1 It is assumed that Z in > Z out. If this is not the case, the circuit has to be flipped and Z out and Z in have to be interchanged. 2 The large-signal output impedance is estimated using the breakdown voltage (100V) and maximum current (1A) for a 1mm AlGaN/GaN HEMT. The capacitance and inductance values are typical for GaAs FETs of equal size [1].

92 Passive Components on AlN + * 1 ) 5 * 1 ) 5. - 6 * 1 ) 5 % 0 # F 0 # 0 * A @ & F. D % D & # D & 0 + @?. - 6 6 K? J E N & F.! F. # D + H I I Figure 6.3: Output stage matching network of a HPA. Three L-type matching networks are used in combination with two bias networks and a DC-blocking capacitor. using the same inductor. Capacitor C BIAS is added to prevent high-frequency signals from entering the bias supplies. The next step is to match the 71Ω to the impedance looking towards the bend. To ensure maximum bandwidth, this impedance is chosen so that the impedance transformation in the upper branch, consisting of 0.5nH and 0.08pF, is equal to the transformation in the output stage, consisting of 0.28nH and 0.13pF. For this example, this intermediate impedance equals 85Ω. The capacitor needed for matching 71Ω to 85Ω (0.08pF) is doubled because it functions for both branches (upper and lower) simultaneously. The resulting value of 0.16pF is also easier to fabricate. After the cross, we see an impedance of 85/2 = 42.5Ω looking towards the HEMTs. This impedance has to be matched to the 50Ω output. The transformation ratio is the same as in the previous stage. A DC-blocking capacitor (C dc ) is included to make sure that only the RF signal is on the output of the HPA. To realize the component values, we could use chip capacitors and chip inductors to construct the matching network. A necessary condition for this technique to work is that the wavelength of the signal is much larger than the dimensions of these components, otherwise we cannot regard them as lumped elements. As a rule of thumb, we demand that the typical dimension of the chip component is less than 1/10λ. For components on AlN, this results in a maximum size of 1.4mm at 10GHz. These sizes are very impractical to handle if available at all. In addition, transmission properties, like electrical delay between the different components, has to be accounted for. These problems make these components difficult to use in the X-band. Instead, we can use waveguide elements. How to realize these components depends on the technology used.

C 6.3 Microstrip and Coplanar Waveguide Technology 93 I C I C ) * Figure 6.4: Cross-section of a microstrip (A) and a coplanar waveguide (B). The coplanar line has both the signal (s) and ground (g) tracks on the topside of the wafer. 6.3 Microstrip and Coplanar Waveguide Technology In this section we will discuss two technologies used for on-chip integration: microstrip and coplanar waveguide (CPW). The layout for these technologies is depicted in Figure 6.4. Both technologies consist of a substrate on which metal tracks are fabricated. The most important difference between the two is related to the location of the ground plane. For microstrip technology it is on the backside of the substrate, while coplanar technology has all the metal tracks on the topside of the substrate. This makes coplanar technology easier and cheaper to fabricate than microstrip. However, compared to microstrip, losses and dispersion are somewhat higher [2]. Passive components can be made on the same material as the active devices. This is called monolithic integration. If the passive components are made on a different material and/or substrate we have a hybrid integration. The latter requires some sort of connection between the active and passive parts of the circuit. This can be done using bondwires or flip-chip techniques. If a circuit made in microstrip technology requires a ground connection, a hole is made through the substrate. Such a connection is called a via-hole. Depending on the substrate material that is used, dry or wet etching techniques are employed. Fabrication of a viahole is far from trivial. It requires a deep etch (> 100µm), so the etching process itself should have a reasonable etch rate ( 1µm/min). In addition, the via-hole should have sloped side walls so that it can be covered with a thick metal layer, e.g. gold or copper, using electroplating. The reactive ion etching process described in chapter 3, does not provide suitable etch rates for the fabrication of via-holes in GaN. In addition, preliminary investigations into the etching of SiC revealed an etch rate of about 40nm/min. Other etching techniques like ICP, have shown to yield more useful etch rates on WBGS [3] but such a system was unfortunately not available for this work. Choosing either GaN or SiC as substrate material will therefore implicate the use of coplanar technology.

94 Passive Components on AlN Table 6.1: Thermal and electrical properties for various substrate materials. Material Therm. cond. Breakdown field Diel. constant (W/cmK) (MV/cm) BeO 1 2.6 0.095 6.5 ceramic AlN 1 1.7 0.15 8.8 sapphire [4] 0.23 0.4 2 8.6 Si [5] 1.5 0.3 11.8 GaN [4] 2.1 3.3 [5] 9.5 SiC (4H) [5] 3.3 2 10 AlN 3-3.4 [6] 1.2 1.8 3 8.5 ± 0.2 [4] 1 www.stellar-ind.com, 2 www.mkt-intl.com 3 www.ioffe.ru/sva/nsm/semicond/aln/index.html 6.4 Substrate Material and Integration Technique Table 6.1 lists some of the possible substrates for passive components. Based on this list, we will now discuss some of the potential realizations of a HPA: Monolithic integration using SiC substrates. This solution is the most attractive in terms of heat dissipation, but is also one of the most cost-expensive. Hybrid integration of AlGaN/GaN HEMTs on SiC, AlN, or GaN with ceramic substrates. Because more than 80% of the total amplifier consists of passive components, it makes sense to use relatively cheap ceramic substrates like AlN or beryllium oxide (BeO) for the passive components while still maintaining high-performance HEMTs. Although this solution will certainly not outperform monolithic integration on SiC, it could provide a more cost-inexpensive solution. Furthermore, this approach allows the active devices to be tested before they are flip-chipped saving costly area in case a HEMT fails due to material/processing defects. AlN would likely be the prime candidate because it has excellent thermal and electrical properties and is not a highly toxic material like BeO. Monolithic integration using AlN or GaN substrates. Compared to monolithic integration using SiC, this approach should result in better quality GaN films with less defects. This could in turn improve reliability of the HEMTs. On the other hand, the thermal conductivity is slightly less than that of SiC. Although results on AlGaN/GaN HEMTs on AlN have been published [6], this approach is much less mature than SiC. Similar arguments hold for devices grown on GaN. Commercial availability of both AlN and GaN bulk substrates is still limited 3. 3 For GaN substrates see: www.cree.com, www.sumitomo.com or www.tdii.com. For AlN substrates see: www.crystal-is.com.

6.5 Constructing a CPW Library 95 Monolithic integration using Si substrates. The obvious advantages of this approach are costs and the possibility to scale the process to large diameter wafers. Performance of devices on Si do not yet approach those obtained on SiC or sapphire. However, the thermal conductivity is much better than that of sapphire. These devices could well be the optimum balance between costs and performance that is needed for further commercialization of the GaN material system for electronic applications. Hybrid integration of AlGaN/GaN HEMTs on sapphire with ceramic substrates. The thermal conductivity of sapphire is too low for effective monolithic integration. Instead, flip-chipping devices on AlN increases the power handling capability of these devices although performance does not approach that obtained with SiC devices [7]. It is therefore questionable whether this solution will eventually be preferred over devices on Si. For the work described in this thesis, it was decided to use coplanar technology on ceramic AlN to fabricate passive devices. The most important reasons for this decision were: Microstrip technology is only feasible for devices on Si. For other substrates other equipment is needed. Even then, it remains highly questionable whether a via-hole process proves to be crucial for the development of WBGS. It has to be noted that via-holes could influence thermal behavior. Ceramic AlN approaches the thermal performance of BeO, which has been the preferred substrate for high-power applications for many years. Environmental and health concerns have stimulated the use of ceramic AlN as substrate material 4. In addition, if in the future devices on bulk AlN become available, this technology can be easily transferred. The isolating properties of ceramic AlN (> 10 12 Ωcm) and low dielectric loss tangent (< 0.001) can never be parallelled by semiconductor materials. At the time this decision was made, semi-insulating SiC was not available. In addition, it makes more sense to use the relatively cheap ceramic AlN (10$/2inch wafer) to develop the necessary processing and later on, when the processing is more mature, make the change to SiC substrates (2000$/2inch wafer). Most likely, only a limited amount of work has to be repeated to account for e.g. the difference in dielectric constant. 6.5 Constructing a CPW Library At the start of this research, a CPW process was not available. Hence, a processing scheme had to be developed with which all the necessary passive components can be realized. In addition, models had to be developed that describe the electrical performance. 4 See DuPont thick film news bulletin number 19 June 2002, at www.dupont.com/mcm/horizons.

96 REFERENCES These models have to be scalable so that the designer has the freedom to tailor a specific component to his or her needs instead of using only a limited amount of available components. An example is a resistor in which the width and length of the resistive layer (NiCr) determine the overall resistance. By making a model that describes the resistance as a function of these parameters, the designer can use arbitrary resistance values. Typical matching networks consist of transmission lines, bends, T-junctions, crosses, resistors and capacitors. All these components need to be developed and characterized to form a component library. The development of this library will be described in the next few chapters: Chapter 7 will start with transmission lines. Adaptors that are connected to either side of the transmission line are needed for probing but they distort the overall measurement. A so-called de-embedding algorithm will be presented that solves this problem. Orthogonal and multi-port structures will be analyzed in chapter 8. These elements have to be measured carefully because the ports are placed orthogonally. The multiports will be analyzed using a series of two-port measurements. Tapers, resistors and capacitors will be the subject of investigation in chapter 9. These elements are crucial for matching networks. The electrical length of the intrinsic element, i.e. without the taper and adaptor, has to be known very accurately, otherwise the center frequencies of the matching networks will shift. The accuracy of the models will be verified in chapter 10 using two matching networks. By comparing measured and simulated data, the applicability of the scalable models will be demonstrated. Although the processing of devices was a very crucial aspect of this research, it is not part of the main body of this thesis. A detailed description on the processing of passive components, as well as the material properties of the ceramic AlN that was used, can however be found in Appendix B. The approach followed to develop the library is a practical one. All the components are fabricated, measured and modelled. We could also use electromagnetic simulators to generate the data needed for the construction of the models. Ideally, both approaches should be combined. The work described in this thesis is restricted to the practical implementation. It will be shown that an accurate library can be constructed that is useful for designing power amplifiers in subsequent projects. Nevertheless, electromagnetic modelling is a powerful tool, which, when combined with the practical results described in this thesis, could enhance the accuracy of the design. One example in which these tools are indispensable is in designs where there is a large amount of electromagnetic coupling between different components. This coupling is not accounted for if the design is built up using models of devices that were characterized separately. References [1] A.P. De Hek, Design, Realisation and Test of GaAs-based Monolithic Integrated X- band High-Power Amplifiers. PhD thesis, Eindhoven University of Technology, 2002.

REFERENCES 97 [2] K.C. Gupta, R. Garg, and I.J. Bahl, Microstrip Lines and Slotlines. Artech House, 1979. [3] F.A. Khan, B. Roof, L. Zhou, and I. Adesida, Etching of Silicon Carbide for Device Fabrication and Through Via-Hole Formation, Journal of Electronic Materials, vol. 30, no. 3, p. 212, 2001. [4] L. Liu and J.H. Edgar, Substrates for Gallium Nitride Epitaxy, Material Science and Engineering Reports, vol. 37, no. 3, p. 61, 2002. [5] R.T. Kemerlay, H.B. Wallace, and M.N. Yoder, Impact of Wide Bandgap Microwave Devices on DoD systems, Proceedings of the IEEE, vol. 90, no. 6, p. 1059, 2002. [6] X. Hu, J. Deng, N. Pala, R. Gaska, M.S. Shur, C.Q. Chen, J. Yang, G. Simin, M.A. Khan, J.C. Rojo, and L.J. Schowalter, AlGaN/GaN Heterostructure Field- Effect Transistors on Single-Crystal bulk AlN, Applied Physics Letters, vol. 82, no. 8, p. 1299, 2003. [7] J. Sun, H. Fatima, A. Koudymov, A. Chitnis, X. Hu, H.M. Wang, J. Zhang, G. Simin, J. Yang, and M.A. Khan, Thermal Management of AlGaN-GaN HFETs on Sapphire Using Flip-Chip Bonding With Epoxy Underfill, IEEE Electron Device Letters, vol. 24, no. 6, p. 375, 2003.

98 REFERENCES

Chapter 7 Coplanar Transmission Lines 7.1 Introduction In this chapter we will develop a scalable model for coplanar transmission lines. Data required for the construction of the model will be obtained by measuring transmission lines of various geometries. We will start by investigating which electromagnetic modes can propagate through these lines. It will be shown that if specific design rules are obeyed, a quasi-tem mode will be dominant. Not complying with these rules will result in lines showing distortion and/or dispersive behavior at high frequencies. The model by Heinrich [1], which is based on the quasi-tem approximation, will be used to illustrate the behavior of coplanar lines. It contains a set of equations describing the components of an equivalent circuit for the transmission line. Next, we will discuss measurements of lines with different geometries. The spacing and signal line width of the lines are varied and each line is examined for irregular nonquasi-tem behavior. From this set of lines, we will define the geometrical quasi-tem range. Lines with dimensions that fall within this range will show the desired quasi-tem behavior. The actual transmission lines are embedded between two adaptors. These adaptors are needed because most lines have dimensions that make them impossible to probe. An algorithm will be presented by which the influence of the adaptors can be removed. This de-embedding algorithm is based on the through-reflect-line (TRL) algorithm [2] used for the calibration of network analyzers. It uses the transmission line model, which makes it only applicable to quasi-tem lines. The de-embedding algorithm will then be used to determine the characteristics of transmission lines that operate in the quasi-tem range. A scalable model will be developed based on the model by Heinrich. The complex shape of the metal conductors has to be accounted for in order to get a good agreement between measurements and model. In addition, a scalable model for the adaptor will be developed. 99

D 100 Coplanar Transmission Lines M C I M I M C J ) 5 K > I J H = J A Figure 7.1: Cross-sectional view of a conductor-backed coplanar waveguide on AlN. 7.2 Geometrical Quasi-TEM Range 7.2.1 Quasi-TEM Approximation Consider the coplanar transmission line illustrated in Figure 7.1. This type of structure is called a conductor-backed coplanar waveguide (CBCPW). The metal layer on the bottom of the substrate represents the non-grounded metal chuck on which the devices are placed during testing. This layer is not part of the processing but it plays a significant role in the analysis of possible propagation modes. The fields in this structure are not only concentrated in the dielectric substrate but also in the air region above. This structure does therefore not support pure TEM modes. To determine the properties of the line, rigorous full-wave techniques are required. However, in most cases the fields parallel to the propagation direction can be neglected compared to the transverse fields [3]. Under these conditions, an approximate solution can be found using a quasi-static analysis similar to that used for TEM modes. This approach is called the quasi-tem approximation and the resulting mode is named the quasi-tem mode, which will be referred to as the CPW mode in the remainder of this chapter. The frequency (f) up to which the quasi-tem approximation can be used is given by [1]: f 1 1 1 10 µ0 ɛ 0 ɛ r w + 2s (7.1) where ɛ 0 and µ 0 are the electric permittivity and magnetic permeability of vacuum, respectively, and ɛ r the relative dielectric constant of the substrate. This equation states that the wavelength in the dielectric should not be less than 10 times the characteristic width of the transmission line, w + 2s (see Figure 7.1). The CPW mode will prove to be very important. Many of the ideas developed in this chapter, like the de-embedding algorithm, are based on the assumption that this mode is dominant. 7.2.2 Non-CPW Modes The CPW mode is not the only mode that can propagate through the structure. Other modes, which are mostly dispersive, can couple with the CPW mode resulting in power loss. It is evident that these modes must be avoided. This can be done by carefully choosing the dimensions of the line and by suppressing excitation of these modes at discontinuities using airbridges.

7.2 Geometrical Quasi-TEM Range 101 ) * + Figure 7.2: The CPW mode (A), slotline mode (B) and parallel-plate mode (C). For the CBCPW, the most important non-tem modes are the parallel-plate mode, also called the microstrip line mode or the microstrip coplanar mode, and the slotline mode. The electric field lines for these modes, together with those of the CPW mode, are illustrated in Figure 7.2. It can be shown that the influence of the parallel-plate mode can be neglected if the following two conditions apply [4]: w g (w + 2s) (7.2) h (w + 2s) (7.3) The slotline mode becomes important at discontinuities where this mode can be excited. Airbridges, which connect the two ground planes, can be used to suppress this mode. Because the transmission line is measured using coplanar probes, the ground planes are connected during measurement. It is therefore not expected that this mode will be excited at the probe tips. The excitation of non-tem modes is not only detrimental for the transmission properties of the line itself, it also results in coupling between neighboring lines. The amount of coupling between two transmission lines sharing a ground plane of width a g can be neglected if [5]: a g w + 2s 2 (7.4) Note that if a g = 2w g, which represents two CPW lines next to each other, this condition equals Eq. (7.2). If the ground planes on top of the sample are connected to the backside metal, resonance peaks can occur, which may result in strong coupling effects [5]. This is an important fact for packaging of devices. In most coplanar designs, unused area of the sample is covered with ground metal. Apart from the advantages in processing, this suppresses surface wave modes that may propagate through the dielectric [4]. However, if the ground planes become too large, resonances may occur similar to those encountered in patch antennas [6]. These resonance frequencies can be estimated from: f mn = c ( ) 2 ( ) 0.5 2 m n 2 + (7.5) ɛ r w g l

102 Coplanar Transmission Lines 6 @ 4 6 @ / 6 @ + 6 @ @ Figure 7.3: The transmission line model. where c is the speed of light in vacuum, m and n are mode numbers, and l is the length of the line. For typical transmission lines investigated in this thesis (w g = 300µm, l = 1000µm and ɛ r = 9), f 11 equals 174GHz. These resonances will therefore not be an issue. The conditions mentioned above are guidelines for designing coplanar transmission lines and/or other coplanar elements. If non-cpw modes propagate because one of these conditions is not met, distortion or other irregular behavior in the measurement must become visible. 7.3 Quasi-TEM Behavior of CPW Lines 7.3.1 Transmission Line Model If the CPW mode is dominant, we can treat the mode like a pure TEM wave. In this case the transmission line can be described by the transmission line model depicted in Figure 7.3, see Appendix A.4. It is a distributed model valid for an infinitesimally small piece of line. The elements of this model correspond to the normal low-frequency definitions per unit length. The propagation constant (γ) and characteristic impedance (Z 0 ) of the line can be computed using: and γ = Z 0 = (jωl T + R T ) (jωc T + G T ) (7.6) jωlt + R T jωc T + G T = γ jωc T + G T (7.7) where L T, R T, C T, and G T are the line inductance, resistance, capacitance, and conductance, respectively, per unit length (for a derivation see Appendix A.4). Heinrich [1] proposes the use of a conformal mapping technique to derive closed-form expressions for the component values of the transmission line model 1. We will use this model to explain the characteristics of coplanar lines. 1 The complete set of equations is too extensive to be presented here. Interested readers are referred to the original paper.

I M I I 7.3 Quasi-TEM Behavior of CPW Lines 103 M = J M C A H J = @ 5 K > I J H = J A Figure 7.4: Coplanar transmission line on an infinitely thick substrate (ɛ r ) with a non-zero loss tangent (tanδ) having conductors of finite conductivity (σ) and thickness (t m ). The recession ( n m ) of the conductor wall m is used to calculate the line resistance. 7.3.2 Conformal Mapping Results Consider the coplanar line illustrated in Figure 7.4. This geometry is too complex to find analytical solutions for the electromagnetic fields. It can however be mapped onto a different plane using a conformal mapping. Using a suitable mapping results in a geometry that is less complex and for which a solution can be found. Applying the inverse mapping to this solution gives the fields in the waveguide. Heinrich applied this technique to CPW lines having infinitely thick substrates. In practice, we can treat a substrate as infinitely thick if [1]: h 2(w + 2s) (7.8) If this condition and/or Eq. (7.1) is not met, the model will produce inaccurate results. The closed-form equations for the transmission line components are derived in steps: First an equation for the line capacitance is found, which is assumed to be frequency independent. At high frequencies, the magnetic field is pushed out of the conductors due to the skin effect. For ω, there is no magnetic field left in the conductors. A similar situation would occur if the conductors were perfect. In that case, the line inductance would have a constant value L e regardless of the frequency. For lossy transmission lines, L e therefore represents the high-frequency inductance limit. It can be computed using ω L e C = ω/c with C the capacitance when ɛ r = 1. Having found an analytical expression for L e, Wheeler s incremental inductance rule [7] is used to find values for the line resistance and inductance in the skin-effect regime. For low frequencies, L T and R T can be derived from magnetostatic and electrostatic theories, respectively. Transition functions are used to provide a smooth connection between the low- and high-frequency limits. The line conductance is proportional to ω, the loss tangent, and a geometrical factor. It follows roughly the same geometrical trends as the line capacitance although the conductance does not depend on metallization thickness (t m ).

104 Coplanar Transmission Lines In practice, the signal line width and spacing are the parameters that can be changed in order to obtain a specific characteristic impedance or propagation constant. To investigate the influence of these parameters on the component values, the model of Heinrich was used to simulate various lines, see Figures 7.5-7.8. For these simulations w g = 5w, f = 10GHz, σ = 3 10 7 S/m, ɛ r = 8.8 and tanδ = 0.0005, which corresponds to the lines on AlN that will be discussed in section 7.6. The behavior of the components can be described by the following analogies: The line inductance shows behavior similar to that of a closed-loop inductor. Inductance decreases with signal line width and increases with spacing. The line capacitance shows trends similar to that of a parallel-plate capacitor. Decreasing the signal line width (=top plate) decreases the capacitance while reducing the spacing (=distance between top and bottom plate) causes an increase. Because the line conductance and capacitance are both related to fields in the dielectric, they show roughly the same behavior. The line resistance shows a somewhat counterintuitive behavior. It depends on the spacing between the signal line and ground conductors. This is related to the operating frequency. At DC the three lines in Figure 7.7 coincide, but as frequency increases, they separate due to the skin effect. To explain this behavior, we will briefly review Wheeler s incremental inductance rule [7]. Imagine that the conductors are lossless. In this case, the current flows across the surface and the magnetic field inside the conductors is zero. If the conductors have a finite conductivity, the magnetic field will decay exponentially in the conductor. These fields result in an additional (incremental) inductance L i. This increment is usually evaluated as the change in inductance when all the conductors are recessed by an amount of δ s /2 (see Figure 7.4): L e δ s n m 2 (7.9) L i = m 2/ωµ 0 σ is the skin depth. In the skin-effect regime the total inductance where δ s = is given by the sum of L i and L e. Both the resistance and L i are related to the same magnetic fields in the conductors. In fact, it can be shown that [8]: R T = ωl i = m ωδ s 2 L e n m (7.10) The derivative of the inductance with respect to its walls depends on the spacing. This will in turn affect the line resistance, as demonstrated in Figure 7.7. Figure 7.9 presents the line inductance and resistance as a function of frequency. The low- and high-frequency regime show the familiar characteristics. In the skin-effect regime the inductance and resistance are proportional to 1/ f and f, respectively, see Eqs. (7.9) and (7.10). For low frequencies, both approach a constant value. Figure 7.10 illustrates the effective (relative) dielectric constant (ɛ eff ) and propagation loss as a function of frequency. The effective relative dielectric constant is related to the propagation constant γ = α + jβ by: ( ) ( ) c 2 2 cβ ɛ eff = = (7.11) υ ω

7.3 Quasi-TEM Behavior of CPW Lines 105 Figure 7.5: L T (w, s). Figure 7.6: C T (w, s). Figure 7.7: R T (w, s). Figure 7.8: G T (w, s). Figure 7.9: L T (ω) and R T (ω). Line dimensions: w = 50µm, s = 45µm. Figure 7.10: ɛ eff (ω) and loss(ω). Line dimensions: w = 50µm, s = 45µm.

106 Coplanar Transmission Lines Figure 7.11: Phase and magnitude of S 11 (left) and S 12 (right), respectively, simulated using the model by Heinrich. Line dimensions: w = 50µm, s = 60µm, l=3mm. where υ is the speed of the electromagnetic wave in the coplanar line. When ɛ eff changes with frequency the line is dispersive. Looking back at Figure 7.10, we can see that this is especially true at low frequencies. In this regime ωl T R T, which reduces Eq. (7.6) to: γ = (jωl T + R T )jωc T jωr T C T = ωrt C T (1 + j) (7.12) 2 where the conductance has been neglected, which is allowed for materials with a low loss tangent [9]. Combining this with Eq. (7.11) we can see that the dielectric constant is inversely proportional to f. For frequencies above 1GHz, we can assume that the influence of the resistance is small compared to that of the inductance: CT γ = (jωl T + R T )jωc T jω L T C T + R T (7.13) 2 L T This demonstrates that the losses, which are related to R T /2 C T /L T, increase with frequency because of an increase in R T and a decrease in L T. Heinrich s model was used to compute the S-parameters of a 3mm line (w = 50µm, s = 60µm), see Figure 7.11. The points of maximum transmission roughly correspond to l/λ = 1 n with λ = 2π/β the wavelength of the mode and n an integer. In the next section, 2 we will compare experimental data to these graphs to identify quasi-tem behavior. 7.4 Assessment of the Quasi-TEM Range To examine the effects of geometry on propagation behavior, lines of different dimensions were measured. The layout of these lines is illustrated in Figure 7.12. An adaptor is connected to either side of the transmission line for probing. The adaptors allow a smooth transition between the actual line and the measurement apparatus. Apart from the region on which the probes are placed, the adaptors contain 200µm of transmission line. This line is included to ensure that at the end of the adaptor only the desired CPW mode propagates. A taper is included to provide the transition from probe area to line geometry.

N N I 7.4 Assessment of the Quasi-TEM Range 107 ) * + = @ = F J H % # % # % # # M M # % # J H = I E A E I I E % # Figure 7.12: CPW layout; all dimensions are in µm. The adaptor consists of (A) probe area (B) taper (C) line element. The value of x is such that the width of the adaptor is either 525µm or equal to the width of the line (= 11w + 2s). The vertical and horizontal ruler indicate the dimensions of different parts of the layout. Figure 7.13: Typical quasi-tem behavior. Line data (w, s, l) = (50, 80, 3200) µm. Figure 7.14: Non-quasi-TEM effects. Line data (w, s, l) = (200, 320, 3200) µm. Figure 7.15: Comparison between S 11 measured directly on a metal chuck and using a piece of plastic between chuck and sample. Line data (w, s, l) = (200, 320, 3200) µm.

108 Coplanar Transmission Lines Table 7.1: Qualification into quasi-tem (+) and non-quasi-tem behavior ( ). s w 25 50 75 100 150 200 10 + + + + + 20 + + + + +/ 40 + + + +/ 80 + + + +/ 160 + + + +/ 320 +/ +/ +/ The key parameters that were varied are the signal-ground spacing (s), the signal line width (w) and the length of the line (l). The width of the ground planes was determined from w g = 5w. This ensured that condition Eq. (7.2) was fulfilled for the lines of interest. A more detailed description of the structure will be given in this chapter later on. The measurements showed two types of behavior, illustrated in Figures 7.13 and 7.14, respectively. The behavior in Figure 7.13 corresponds to the quasi-tem behavior in Figure 7.11. The behavior depicted in Figure 7.14 shows the distorting effects at high frequencies (> 30GHz) when non-quasi-tem modes propagate through the line. Measurements on similar lines, but with different lengths, have shown that this occurs irrespective of the length of the line. Because the line is overmoded, it suffers from strong dispersion, which makes modelling of these lines very difficult. If possible, the use of these lines should therefore be avoided. All the measurements were inspected for quasi-tem behavior. Because it is difficult to assign a numerical value to the degree of quasi-tem behavior, each line was qualified using + and symbols representing quasi- and non-quasi-tem behavior, respectively. Table 7.1 shows this qualification for the fabricated lines. Quasi-TEM behavior can only be assured if the signal-ground spacing and signal line width are not too large. This of course corresponds to condition Eq. (7.3) for suppressing the parallel-plate mode. An additional test was conducted to find further evidence that the parallel-plate mode is indeed responsible for the distortion at high frequencies. A thick piece (> 3mm) of plastic was placed between the metal chuck of the probe station and the sample. The characteristics before and after placing the plastic are shown in Figure 7.15. Because the distance between the metal chuck (=bottom plate) and the metal tracks on top of the sample (=top plate) is increased, the influence of the parallel-plate mode has disappeared. All the measurement data presented above included the influence of the adaptor. To determine the properties of the transmission line itself we must develop an algorithm to extract the transmission line parameters from the measurements.

> = 7.5 De-embedding Algorithm for CPW Lines 109 = @ = F J H ) = @ = F J H ) = > ) ) =! >! > " = " I E C = E A C H K @ J H = I E I I E E A Figure 7.16: Layout of a coplanar waveguide connected to two adaptors. As illustrated on the right, the structure can be represented by a cascade of three separate components. 7.5 De-embedding Algorithm for CPW Lines 7.5.1 The Modified TRL Approach Removing the influence of the adaptors much resembles the techniques developed for the calibration of network analyzers. The algorithm described in this section is based on the generalized TRL algorithm [2]. Unlike the short-open-load-through (SOLT) or throughshort-delay (TSD) algorithms, this method does not rely on a well-defined short or load. Instead, it uses two lines of different length and two unknown but equal reflects. Because of symmetry in the layout, the TRL algorithm can be simplified. Next, it will be shown that the adaptors can be fully characterized using two transmission lines of different length and a line capacitance measurement. The analysis that will follow is based on (cascade) T -parameters. For a two-port, these parameters can be computed using the corresponding S-parameters: ( b1 a 1 ) = T ( a2 b 2 ) = 1 ( S11 S 21 S 22 1 ) ( a2 b 2 ) (7.14) where a and b are travelling waves (see Appendix A.3) and = S 11 S 22 S 12 S 21. We start by examining the coplanar line in Figure 7.16. Because the adaptors and line are cascaded, the T -parameters for the entire structure (T M ) can be found by multiplying the individual matrices: T M = T A T L T A (7.15) where T L represents the actual coplanar line and T A and T A are the cascade parameters of the adaptor on the left and right, respectively. The underline indicates that the adaptors on the left and right are mirrored images. Next, the individual matrices will be determined in three steps. Measurement of a through and a delay. We start the de-embedding routine by measuring the cascade parameters of a line of length l: T DE = T A T L T A (7.16)

110 Coplanar Transmission Lines where T L is the cascade matrix of the line element. Next, we measure a through, which equals a line of zero length: T T R = T A T A (7.17) We assume that in both structures the same mode propagates characterized by Z 0. To continue, we need an expression for T L. Following the definition of Marks and Williams [10] for a and b, see Appendix A.3, we find: ( ) e γl 0 T L = 0 e γl (7.18) This matrix has a diagonal form because a and b are travelling waves. If we had used the more common power wave definition by Kurokawa [11] and Youla [12], T L would have had off-diagonal elements 2. So, here we make explicit use of the fact that a and b are travelling waves. Although, a 2, b 2, a 3 and b 3 are referenced to Z 0 of the line, the other parameters are not. They are referenced to Z ref, which is the reference impedance of the network analyzer as determined by the calibration (usually 50Ω). Hence, T L is referenced to Z 0 at both ports but T A and T A are not. They are referenced to Z 0 at their inner ports but to Z ref at their outer ports. To continue we eliminate T A from Eqs. (7.16) and (7.17): M T A = T A T L (7.19) where M = T DE T T R 1. We can expand this relation into [13]: M 11 T 11A + M 12 T 21A = T 11A e γl (7.20) M 21 T 11A + M 22 T 21A = T 21A e γl (7.21) M 11 T 12A + M 12 T 22A = T 12A e γl (7.22) M 21 T 12A + M 22 T 22A = T 22A e γl (7.23) Dividing Eq. (7.20) by (7.21) and (7.22) by (7.23) yields two quadratic equations that have identical coefficients: M 21 x 2 + (M 22 M 11 )x M 12 = 0 (7.24) where x = T 11A /T 21A or x = T 12A /T 22A. To determine which solution to assign to which T -parameter ratio, we use Eq. (7.14) to expand the ratios: T 11A T 21A = S 11A S 21AS 12A S 22A (7.25) T 12A T 22A = S 11A (7.26) The adaptors should have a high transmission. It is therefore safe to assume that S nn S nm so we can assign the larger solution of x to Eq. (7.25). We can obtain information about the propagation constant by dividing Eq. (7.23) by Eq. (7.20): where x 1 > x 2. 2 See Appendix A.3.2 for an extensive discussion. e 2γl = M 21x 2 + M 22 M 12 /x 1 + M 11 (7.27)

7.5 De-embedding Algorithm for CPW Lines 111 Expanding the through measurement. The adaptors are represented by the S- matrices S A and S A, see Figure 7.16. A correlation between these matrices can be found by connecting identical sources on the left and right. Symmetry dictates that a 1 = a 4, b 1 = b 4, a 2 = a 3, and b 2 = b 3. Using the definition: ( ) 0 1 I = (7.28) 1 0 we find: ( b3 b 4 ) = I ( b1 b 2 ) = IS A I ( a2 a 1 ) = IS A I ( a3 a 4 ) (7.29) Therefore, adaptor matrix S A can be computed using S A = IS A I. Using this result we can expand the through measurement into: T T R = T A T A = 1 ( ) ( ) S11A 1 S22A (7.30) S 21A S 22A 1 S 12A S 11A 1 where Eq. (7.14) was used. For the individual terms of T T R we have: T 11T R = T 12T R = T 21T R = T 22T R = 1 ( 2 S ) 2 11A S 12A S 21A (7.31) 1 (S 22A S 11A ) S 12A S 21A (7.32) 1 (S 22A S 11A ) S 12A S 21A (7.33) 1 ( ) 1 2 S22A S 12A S 21A (7.34) Using the measurement data collected so far, we cannot fully determine S A. If we assume S 12A = S 21A, which is common for reciprocal networks, we can combine Eqs. (7.26), (7.33) and (7.34) to find S 22A : S 22A = T 21T R T 22T R T 12A T 22A (7.35) The remaining unknown S 12A can then simply be found using Eq. (7.34). It can be shown that the ratio of S 21 and S 12 for a passive network is given by [10]: S 21 = K 1 1 j Im(Z ref,1 )/Re(Z ref,1 ) S 12 K 2 1 j Im(Z ref,2 )/Re(Z ref,2 ) (7.36) where Z ref,n is the reference impedance at port n and K n the corresponding reciprocity factor. The reciprocity factors K 1 and K 2 can be taken 1 for most practical applications. But, because the reference impedance on both ports is not equal and because Z 0 is generally complex, the assumption S 12A = S 21A does not hold. We therefore need additional equations to solve for S A. Note that if the reference impedance is the same for both ports S 12A = S 21A. A way to accomplish this is to transform all the measurement data to Z 0 and then start the algorithm again. But we do not know the value of Z 0 at this point. Using the transmission line model in combination with a line capacitance measurement provides an answer.

112 Coplanar Transmission Lines Determining Z 0 and re-computation. Like in section 7.3, we assume that the CPW mode is dominant so we can use the transmission line model. Because AlN is an excellent isolator with a low loss tangent, it is safe to assume that jωc T G T for the frequency band of interest [9]. This reduces Eq. (7.7) to: Z 0 = γ jωc T (7.37) where γ is already determined from measurements. The line capacitance (C T ) can be determined using low-frequency S-parameter measurements or using an LCR measurement bridge. Having determined Z 0, we can transform the reference impedance of all measurements to Z 0 3. This way, the reference impedance for the adaptors is the same for each port, so we can apply S 21A = S 12A. Eqs. (7.26), (7.35) and (7.34) can then be used to determine S 11A, S 22A and S 12A, respectively. Finally, the S-parameters of the adaptor are converted back to Z ref, which is normally 50Ω. 7.5.2 Summary of the Algorithm. The de-embedding algorithm is summarized below: Measure a line of length l and a through. Measure the capacitance of both structures using low-frequency S-parameter measurements or an LCR bridge. Determine the line capacitance using C T =(C(line)-C(through))/l. Calculate γ using Eq. (7.27). Calculate Z 0 from γ and C T using Eq. (7.37). Convert the reference impedance of the delay and through measurement to Z 0 of the line. Calculate S 11 using Eq. (7.26). Because S 12 = S 21, apply Eqs. (7.35) and (7.34) to compute S 22 and S 12, respectively. Convert the reference impedance of the S-parameters of the adaptor to Z ref of the analyzer, commonly 50Ω. Because this algorithm uses the transmission line model it can only be applied to quasi- TEM lines. 3 The transformation formulas are based on the definition of a and b in Eqs. (A.14) and (A.15), respectively. These formulas are different than those based on the power wave definition. A description on how to perform the transformation is given in [10].

7.5 De-embedding Algorithm for CPW Lines 113 F H J C F H J + + + + Figure 7.17: Coplanar transmission line embedded between two adaptors. For this simulation l = 1mm, Re(Z 0 )=50Ω, C 1 = 10fF, C 2 = 5fF, and L = 50pH. Figure 7.18: Magnitude ratios of S-parameters computed using the power wave definition (P) and the travelling wave definition (T) versus the loss per mm in the line at 10GHz. 7.5.3 Comparison with Algorithm Based on Power Waves In the previous section, it was shown that the T -matrix of a line element has a diagonal form because this matrix relates the travelling waves a and b. The definition of the a and b waves is not conventional. Instead, the power wave definition, described in Appendix A.3.2, is commonly used. If the characteristic impedance is complex, these definitions are not equal. Then, the power waves are not travelling waves and the T -matrix has off-diagonal elements. The equation used for transforming the S-matrix based on power waves into Z-parameters is also different. Strictly speaking, the entire algorithm of the previous section cannot be used, but it is interesting to know what would have happened if we had used the power wave definition and the assumption S 12 = S 21. To check this, we used the circuit shown in Figure 7.17 to simulate a coplanar line embedded between two adaptors. A through and delay measurement were simulated for a 1mm line. These measurements were fed into the de-embedding algorithm described in the previous section. The resulting S-parameters of the adaptor corresponded to the S-parameters computed directly from the component values. This validated the algorithm. We also determined the S-parameters using the same algorithm but this time assuming that S 21 = S 12. The

I I M M M, 114 Coplanar Transmission Lines 6 E ) K M C ) K M C ) ) K ) 5 K > I J H = J A * 5 E N ) 5 K > I J H = J A J J (w,s) (w,s) (10,40) (20,100) (20,40) (35,20) (30,40) (45,75) (40,40) (50,45) (50,40) (70,75) (60,40) (75,45) (70,40) (85,100) (80,40) (90,40) (100,40) Figure 7.19: Cross-section of a CPW: (A) idealized shape used by Heinrich, (B) schematic illustration of a processed device. Table 7.2: Dimensions of CPW lines (in µm). transformation formulas used in the final step to convert the reference impedance to 50Ω are based on the power wave definition instead of the travelling wave definition. Several simulations were performed for different values of the argument of Z 0. For each argument, Z 0 was determined so that Re(Z 0 )=50Ω. A line capacitance of 100pF/m was used to compute the propagation constant. The results of this simulation are shown in Figure 7.18. The ratios of the S-parameters of the adaptor computed using the two approaches are plotted versus the loss per mm in the line at 10GHz. When the line is lossless, which corresponds to a zero argument of Z 0, there is no difference between the two approaches. This is because the final conversion steps are the same and because S 12 = S 21, see Eq. (7.36). When the line is lossy, large differences can arise. The approach based on power waves tends to underestimate the transmission of the adaptors. Hence, the transmission properties of other components, like a bend or T-junction, determined using these adaptors can show amplification. 7.6 Quasi-TEM Coplanar Lines on AlN In the remaining part of this chapter we will restrict our analysis to the set of quasi-tem lines described in table 7.2. This table consists of two parts. The part with constant spacing (s) describes the lines that are needed for the extraction of a taper model in chapter 9. The other part tries to cover the quasi-tem range. For this work, the equations developed by Heinrich were used to construct a scalable model. Implementation of this model is however not straightforward because: The metal tracks of processed devices are not rectangular but have a cross-section as depicted in Figure 7.19. To make an easy comparison, the ideal shapes used by Heinrich are also included. The metal tracks consist of a thin Ti/Au metallization (50/200nm) underneath a thick electroplated Au layer (typically 4µm). This poses a

7.6 Quasi-TEM Coplanar Lines on AlN 115 problem in choosing the correct values for t m, s, w, and w g to use in the simulations. There is a thin SiNx layer (200nm) in between the metal tracks. Although this layer is thin compared to the rest of the structure it might influence the measurements. There is no information regarding the loss tangent at microwave frequencies as well as the conductivity of the electroplated Au. The loss tangent of the AlN is specified at 1GHz to be 0.0005. We do not have information about the behavior of AlN at higher frequencies. A similar argument holds for the dielectric constant of AlN, which is 8.8 at 1GHz. We also have to account for the difference between dimensions on the mask and the actual dimensions of processed devices. The substrate has a finite thickness of 508µm. Heinrich s model assumes Eq. (7.8) to be valid. Not all of the lines in table 7.2 comply with this condition. To solve these problems we assume that: The capacitance and conductance are mainly determined by the thin Ti/Au metallization in combination with the AlN substrate. Hence, for calculation of the capacitance and conductance we use w, s and w g as illustrated in Figure 7.19. The thickness for this calculation is taken equal to the average Au thickness (= 4µm). The dielectric constant and loss tangent of the AlN are fixed at 8.8 and 0.0005, respectively, for the entire frequency range. An optimization routine will be used to determine the conductivity of the electroplated Au layer that will give the best fit to the measurements. The inductance and resistance are mainly determined by the electroplated Au layer. In this case there is no clear definition for w, s, t m and w g. To overcome this problem we will set t m to the average Au thickness (= 4µm) and use w + 2, s 2, and w g + 2 as values for the width, spacing and ground width, respectively, see Figure 7.19. The parameter will be determined using an optimization scheme. The optical lithography causes the actual width of the metal tracks to be half a micron larger than their corresponding mask dimensions. This deviation has to be accounted for during the simulation of the devices. However, in the remainder of this thesis we will use the integer values mentioned in table 7.2 to identify transmission lines and/or other components. The influence of the thin SiNx layer and the finite substrate will be determined from experiments. Both effects cannot be accounted for during the simulations. 7.6.1 Scalable Model for the Line Capacitance As was mentioned in section 7.5, we need to determine the line capacitance if we want to know the characteristic impedance of the line. In the low-frequency limit the transmission line (including adaptors) can be described by the circuit in Figure 7.20, which is just the

116 Coplanar Transmission Lines 4 + + Figure 7.20: Low-frequency equivalent circuit for a transmission line including the adaptors. low-frequency approximation of the transmission line model. The line capacitance can be found from C T = (C DE C T R )/l where C T R and C DE represent the capacitance measurement of a through and a line of length l, respectively. Three different methods were used to determine the line capacitance: Low-frequency two-port S-parameter measurements. A network analyzer was used to measure the S-parameters of the through and delay. These were then converted to Y -parameters, which were in turn used to determine the component values of the equivalent circuit in Figure 7.20 at each frequency point. Figure 7.21 shows the extracted line capacitance as a function of frequency. Even at low frequencies it cannot be assumed constant. The measurement is distorted due to the calibration, which is very cumbersome in this frequency range. To overcome this problem, the capacitance data was fitted to a third-order polynomial in a smooth region of the curve (3-10GHz). The coefficients of the polynomial were restricted to give a zero derivative at 0Hz. LCR bridge. An LCR bridge was used to determine the capacitance at 100kHz. At these frequencies, inductive effects can be neglected. The capacitances C DE and C T R can be read directly off the display of the apparatus. Calculation using the model by Heinrich. The line capacitance for a given geometry is calculated directly using the conformal mapping approach by Heinrich taking into account the deviations introduced by lithography (0.5µm). Figure 7.22 presents a comparison between the different methods for lines with constant spacing. The model by Heinrich can be regarded as an average of the two experimental approaches. It will be used to calculate the line capacitance in the remainder of this thesis. Using this approach, an average relative error of less than three percent at 10GHz can be achieved. 7.6.2 Scalable Model for the Propagation Constant The de-embedding algorithm described in section 7.5 was used to calculate the propagation constant for the lines in table 7.2.

7.6 Quasi-TEM Coplanar Lines on AlN 117 Figure 7.21: C T = (C DE C T R )/l versus frequency; w = 50µm, s = 45µm. A polynomial fit is used to overcome an imperfect calibration. Figure 7.22: Comparison of the extracted line capacitances using S-parameter measurements, an LCR bridge, and the model by Heinrich (s = 40µm). Figure 7.23: Simulated and experimental effective dielectric constant (left) and loss (right) for a 1mm line with w = 50µm and s = 45µm. A line simulated without dielectric losses is included for reference. Figure 7.23 illustrates the good fit for the effective dielectric constant that can be achieved with the equations by Heinrich. To simulate the losses in the line, a conductivity of 3 10 7 S/m was used. This value gave the best fit for the lines of interest. A simulation without dielectric losses, as indicated by the tanδ = 0 line, demonstrates the dominating effect of the ohmic losses. The overall fit for the losses is not as good as that for the dielectric constant. In the next section, it will be shown that this difference could be related to the measurement setup. The value of used for the simulation was determined by minimizing the relative error in γ at 10GHz. A value of 2.7µm was found. Although is determined using an optimization routine, this parameter can be estimated using a microscope combined with a distance meter. Measurements on different lines all showed this value to be roughly 3µm, which corresponds well with the value found by optimization. Using the same distance

118 Coplanar Transmission Lines Figure 7.24: The effective dielectric constant (left) and losses (right) of a 1mm line (w = 40µm and s = 40µm) determined using two different network analyzers compared to the model. meter, it was found that w 2 = w 8µm, see Figure 7.19. Using the equations by Heinrich with the correct values for, and accounting for offset caused by optical lithography, results in a scalable model that is able to predict the propagation constant with an average relative error of 2 percent at 10GHz. The error in predicting the loss can be much higher, but because this value is low compared to the imaginary part of γ, the overall error remains low. The dielectric constant has roughly the same value of 4.4 for all lines. This allows for a quick estimation of the real part of the characteristic impedance using Z 0 = ɛ eff /(cc T ). As discussed earlier, the influence of w and s on the capacitance, and therefore on the characteristic impedance, can be explained by a simple parallel-plate analogy. 7.6.3 Influence of the Measurement Setup. We have seen that although the fit for the dielectric constant is very good, the fit for the losses in the line is somewhat poor. It is interesting to know if this applies to measurements done on a different setup as well. To this end, we compared the losses and dielectric constant measured by two different network analyzers. A HP8510B (500MHz - 40GHz) and a HP8510C (500MHz-50GHz) were used, both calibrated using the line-reflect-match (LRM) technique. Figure 7.24 presents a comparison between these two systems, the Heinrich model is included for reference. The dielectric constant determined by the two systems differs about 2 percent. Other measurements have shown that the difference between the setups is not systematic, i.e. the HP8510C does not always show a lower dielectric constant than the HP8510B. As shown in the graph on the right, these small differences do however significantly change the loss characteristics. The HP8510B shows a better fit with the Heinrich model than the HP8510C. This effect was systematic, i.e. the loss measured by the HP8510C was always equal to or larger than the loss measured by the HP8510B. The latter always showed a better fit with the Heinrich model. The two systems did not use the same probes. A random error, like the probe-to-metal contact resistance, could explain the difference in the measured losses. There are however

+ 7.6 Quasi-TEM Coplanar Lines on AlN 119 4 + E K J C range S 21 Z in Z out 1-30GHz 1.2% 6.0% 5.9% 8-12GHz 0.4% 2.8% 2.6% Figure 7.25: Equivalent circuit used for the scalable model of the adaptor. Table 7.3: Typical maximum errors for a given geometry of the adaptor model. numerous other causes that could provide an explanation. Nevertheless, it is important to keep in mind that we should be careful with measured losses in the line. 7.6.4 Scalable Model for the Adaptor The de-embedding algorithm of section 7.5 also determines the characteristics of the adaptor. Constructing a scalable model for the adaptor can be very useful. For instance, if an unknown device is connected to adaptors that have different dimensions than the adaptors described in this chapter, we can use this model to de-embed the adaptors from the measurement much like we did with the transmission lines. Figure 7.25 illustrates the equivalent circuit used for the adaptor model. Comparing with Figure 7.12, the piece (200µm) of transmission line can be identified. The taper and probe areas are represented by a π-network. The component values of the equivalent circuit were found by de-embedding the 200µm piece of transmission line. Values were obtained by averaging between 15 and 30GHz. Because C 1 and C 2 differed strongly and randomly for different lines, their values were set to 0.01pF, which is an average for all the lines in table 7.2. The complete set of functions describing the equivalent circuit can be found in Appendix C.1. To determine the accuracy of the model, the relative errors in S 21, Z in (S 11 ), and Z out (S 22 ) were determined for two different frequency ranges, 1-30GHz and 8-12GHz. Table 7.3 presents the average maximum errors that were found in these ranges. Using this equivalent circuit accuracies of better than 2 percent can be achieved for the transmission over the entire frequency range (1-50GHz). The relatively high errors for Z in and Z out are related to the very small values for S 11 and S 22, respectively. 7.6.5 Design Considerations The geometry of the transmission line used in an amplifier depends on the stage in which it is employed. For instance, if the transmission line is used in the output stage of the amplifier, it must be able to handle high currents and at the same time provide impedance matching. The current carrying capability of a line is limited by electromigration. This refers to the damaging effects of electrons colliding with the metal structure. It results in an increase in resistance and eventually leads to device failure. To avoid this problem one

120 Coplanar Transmission Lines Figure 7.26: Losses at 10GHz and the maximum current versus the thickness of the electroplated Au. Figure 7.27: Inductance (solid) and capacitance (dashed) contour plots. The values around the graph correspond to 10GHz. Figure 7.28: Contour plot of the characteristic impedance in Ohms at 10GHz. Figure 7.29: Contour plot of the losses at 10GHz. usually sets a limit to the current density that is allowed to flow through the metal. This limit depends on the metal used and the operating frequency. If we assume a limit of 4mA/µm 2 for the DC component [14], we find that the widest line of table 7.2 (w = 100µm and t m = 4µm) supports a maximum current of 1.6A. This value can only be increased by using a thicker layer of gold or changing the width of the line. The latter option involves changing the thickness of the AlN substrate if quasi-tem behavior is to be guaranteed. Figure 7.26 illustrates the maximum current and losses for a 1mm line with w = 45µm and s = 75µm as a function of the thickness of the electroplated Au layer. Increasing thickness beyond 1µm is especially important for the maximum current, RF losses do not decrease strongly if thicker gold is used. For matching purposes the transmission line acts as an inductor. Figure 7.27 presents an overview of the line inductance and capacitance at 10GHz for different geometries. For completeness the contour plots for the characteristic impedance and transmission line

7.7 Summary 121 losses are also included, see Figures 7.28 and 7.29, respectively. These figures can be a very useful tool. Let us assume that we have to match 25Ω to 50Ω at 10GHz. Using Eqs. (6.8) and (6.9) we find that we need an inductance of 0.4nH and a capacitance of 0.32pF. As an example we will take a line that has w = 35µm and s = 100µm. According to Figure 7.27, using 0.66mm will give the desired inductance. In addition, it will give a capacitance value of about 0.05pF. The remaining 0.27pF can be realized with the use of MIMCAPs, which will be discussed in chapter 9. For accurate design, the use of optimization tools is inevitable. Like in any optimization, the outcome depends strongly on the correct choice of starting values. The approach used in this example can provide these values. 7.7 Summary Several electromagnetic modes can propagate through coplanar transmission lines. However, if certain design rules are respected, the quasi-tem approximation is valid. It is based on the observation that the field components parallel to the propagation direction are much smaller than the transverse fields. As a result, the characteristics of the line can be analyzed using conformal mapping techniques. A geometrical range of transmission lines for which the quasi-tem approximation is valid was experimentally determined. This was done by measuring the characteristics of lines with different signal line widths and signal-ground spacings. Especially for large values of these parameters, distortion was seen at high frequencies indicating the presence of the parallel-plate mode. The transmission lines were embedded between two adaptors. These adaptors were necessary because not every line has dimensions suitable for probing. Measurements of these lines are therefore distorted. A de-embedding algorithm, based on the quasi-tem approximation, was developed by which the influence of the adaptors could be removed. A scalable model for the transmission lines was developed based on the conformal mapping results obtained by Heinrich. An accuracy of better than 3% was obtained using a correction to account for the deviation in metal shapes of processed devices compared to the ideal shapes used by the analytical model. A scalable model was also derived for the adaptor. Using this model, adaptors can be de-embedded that have different dimensions than the ones discussed in this chapter. References [1] W. Heinrich, Quasi-TEM Description of MMIC Coplanar Lines Including Conductor Loss Effects, IEEE Transactions on Microwave Theory and Techniques, vol. 41, no. 1, p. 45, 1993. [2] R.R. Pantoja, M.J. Howes, J.R. Richardson, and R.D. Pollard, Improved Calibration and Measurement of the Scattering Parameters of Microwave Integrated Circuits, IEEE Transactions on Microwave Theory and Techniques, vol. 37, no. 11, p. 1675, 1989.

122 REFERENCES [3] G.L. Matthaei, K. Kiziloğlu, N. Dagli, and S.I. Long, The Nature of the Charges, Currents, and Fields in and about Conductors Having Cross-Sectional Dimensions of the Order of a Skin Depth, IEEE Transactions on Microwave Theory and Techniques, vol. 38, no. 8, p. 1031, 1990. [4] M. Riaziat, R. Majidi-Ahy, and I-Jaung Feng, Propagation Modes and Dispersion Characteristics of Coplanar Waveguides, IEEE Transactions on Microwave Theory and Techniques, vol. 38, no. 3, p. 245, 1990. [5] F. Schnieder, H.M. Heiliger, and W. Heinrich, Coupling Between Neighboring CPW s in MMIC s, IEEE Microwave and Guided Wave Letters, vol. 8, no. 8, p. 290, 1998. [6] W.H. Haydl, Resonance Phenomena and Power Loss in Conductor-Backed Coplanar Structures, IEEE Microwave and Guided Wave Letters, vol. 20, no. 12, p. 514, 2000. [7] H.A. Wheeler, Formulas for the Skin Effect, Proceedings IRE, vol. 30, p. 412, 1942. [8] K.C. Gupta, R. Garg, and I.J. Bahl, Microstrip Lines and Slotlines. Artech House, 1979. [9] D.F. Williams and R.B. Marks, Transmission Line Capacitance Measurements, IEEE Microwave and Guided Wave Letters, vol. 1, no. 9, p. 243, 1991. [10] R.B. Marks and D.F. Williams, A General Waveguide Circuit Theory, Journal of Research of the National Institute of Standards and Technology, vol. 97, no. 5, p. 533, 1992. [11] K. Kurokawa, Power Waves and the Scattering Matrix, IEEE Transactions on Microwave Theory and Techniques, vol. 13, no. 3, p. 194, 1965. [12] D.C. Youla, On Scattering Matrices Normalized to Complex Port Numbers, Proceedings IRE, vol. 49, p. 1221, 1961. [13] G.F. Engen and C.A. Hoer, Thru-Reflect-Line: An improved Technique for Calibrating the Dual Six-Port Automatic Network Analyzer, IEEE Transactions on Microwave Theory and Techniques, vol. 27, no. 12, p. 987, 1979. [14] A.P. De Hek, Design, Realisation and Test of GaAs-based Monolithic Integrated X- band High-Power Amplifiers. PhD thesis, Eindhoven University of Technology, 2002.

Chapter 8 Orthogonal Elements 8.1 Introduction This chapter presents a study on bends, T-junctions and crosses. Figure 8.1 illustrates the layout for these structures as well as the corresponding equivalent circuits. Again, adaptors are needed to make the structure suitable for probing. The border between adaptor and the actual bend, T-junction or cross, is indicated by dotted lines. The gray boxes represent airbridges that run over metal tracks, which connect the ground planes. This connection is necessary to suppress slotline modes that can be excited at these discontinuities. Other layouts, which have the airbridge crossing the signal line, are also possible, but they have a significantly lower current carrying capability. This is due to the fact that underneath the airbridge the metal is much thinner (< 300nm). The objective of this chapter is to construct scalable models that predict the values for the components in the equivalent circuits as a function of geometry. For the bend the parameters are the width (w) and spacing (s) of the connecting transmission line. For T-junctions and crosses the number of parameters is doubled to allow for two different types of transmission line to be connected. In theory, a T-junction or cross could be used to connect three or four types of line, respectively. Using only two line geometries introduces a symmetry within the structure that reduces the number of measurements needed. The same (w,s) combinations are used as in the previous chapter, see the righthand side of table 7.2. This results in 8 different bends, 64 different T-junctions, and 36 different crosses. The reader is encouraged to check the redundancy of the remaining 64-36=28 crosses. As can be seen from Figure 8.1, the components do not have all of their ports aligned. Characterization therefore requires some sort of orthogonal calibration. Furthermore, T- junctions and crosses have three and four ports, respectively, while the network analyzer only has two. So we have to address the problem of how to analyze a multi-port structure with a two-port analyzer. The first problem will be addressed in the section on bends. A solution to the second problem will be presented in the section on T-junctions and crosses. 123

F F 124 Orthogonal Elements F H J F F ) F H J F H J F H J F! "! * F F H J! F H J " F H J F H J F " "!! " F! # F + F H J! Figure 8.1: Layout and equivalent circuit for a bend (A), T-junction (B), and cross (C). Airbridges run over the ground interconnects to maintain a high current carrying capability. Ground interconnects are used to suppress slotline modes that can be excited. The equivalent circuits model the inner parts of the structures indicated by the inner dotted boxes. Z 1 and Z 4 represent capacitances whereas the other components consist of an inductor and resistor in series.

8.2 Coplanar Bend 125 Figure 8.2: Comparison between a bend (w = 45µm, s = 75µm) measured with an orthogonal SOLT calibration and a LRM calibration followed by rotating the probe. (B) and (C) stand for the HP8510B and HP8510C network analyzer, respectively, which were used for the measurement. 8.2 Coplanar Bend 8.2.1 Calibration The first problem that has to be tackled in the analysis of the coplanar bend is related to the fact that the ports are not horizontally aligned. Usually, calibration of the network analyzer is performed with the probes facing each other. To be able to measure the bend one has to either rotate the probe arm or place the probe itself on another probe arm that is already in the right position. Either way, the re-adjustment should be done carefully and without removing the cables from the probe. Any difference in electrical length introduced by bending the cables should be avoided. Another solution to this problem is an orthogonal calibration. The probes are placed in the correct position for the measurement of the bend. During the calibration, orthogonal structures are used that are on the calibration substrate. The problem with this approach is the accuracy of the model for the orthogonal through [1]. Both approaches were used to compare the measured S 12 of a bend (w = 45µm, s = 75µm) 1. The results of this comparison can be found in Figure 8.2. The orthogonal SOLT calibration shows amplification at high frequencies, something which of course is impossible for passive components. The other two measurements, which used a LRM calibration followed by manually rotating the probe, do not show amplification. The HP8510B (40GHz) and HP8510C (50GHz) network analyzers were used for these measurements. Both measurements show the same trend but small differences, which are inevitable, remain. Because the orthogonal SOLT calibration results in non-physical data, the LRM calibration was used for the measurements of all orthogonal structures. In fact, the LRM calibration was used for all elements, including lines, capacitors, and resistors. 1 The measured S 12 includes the influence of the adaptor.

126 Orthogonal Elements 8.2.2 Development of a Scalable Model Looking back at Figure 8.1, we can see that the actual bend, illustrated by the inner dotted box, is much smaller than the structure itself. To determine the properties of the bend, we have to remove the influence of the adaptors and the pieces of transmission line in between the adaptor and the bend. To this end the following steps were used: Measure a delay and a through that have the same width and spacing as the bend. Use the Heinrich model to compute the line capacitance. Calculate γ and Z 0 and the S-parameters of the adaptor using the TRL algorithm described in the previous chapter. Measure the bend structure. De-embed the adaptors on both ports. De-embed 5w 30 microns of transmission line between adaptor and bend on each port using γ and Z 0 that were determined earlier. This shifts the reference plane to the beginning of the airbridge. Having determined the properties of the bend itself, we can calculate the component values of the equivalent circuit in Figure 8.1 at each frequency point using: C(ω) = L(ω) = Im(Z 2) ω 1 = 1 jωz 1 ω Im (Y 11 + Y 12 ) (8.1) = 1 ( ) 1 ω Im (8.2) R(ω) = Re(Z 2) ω = 1 ω Re Y 12 ( ) 1 Y 12 (8.3) The total resistance is then given by R tot = R ω. The ω dependence models the skin effect. Results for L and R are averaged between 1 and 30GHz. The value for C was found by averaging between 30 and 50 GHz. Using this procedure, three component values for each (w,s) combination were found. Tablecurve2D 2 was used to find functions R(w, s), L(w, s) and C(w, s), which are listed in Appendix C.2. These functions together with the equivalent circuit constitute the scalable model for the bend. Figure 8.3 presents a comparison between the measured and modelled reflection (S 11 ) and transmission (S 12 ) of a bend (w=45µm, s=75µm). The relatively large error in the phase of S 11 is not critical as the corresponding magnitude is very low. The overall errors of the model, which are described in table 8.1, indicate that the model is very accurate in the X-band. Although more than suitable, a better fit at high frequencies can be obtained by averaging the component values in that region, but this would degrade the model at other frequencies. Also, more components could be introduced to the model but then the values have to be determined by optimization instead of direct calculation. 2 Version 3, AISN Software Inc.

8.2 Coplanar Bend 127 Figure 8.3: Magnitude and phase of S 11 (left) and S 12 (right) for a bend (45,75). Table 8.1: Relative errors in percent for the scalable model of the bend in the X-band (8-12GHz) and the 1-30GHz band. The values inside the brackets stand for the minimum, average, and maximum values, respectively. S 12 [8-12GHz] Z in [8-12GHz] S 12 [1-30GHz] Z in [1-30GHz] (0.4, 0.6, 1.3) (1, 1.5, 2.7) (1.3, 1.8, 2.4) (2.7, 4.8, 6.5) 8.2.3 Properties of Coplanar Bends An ideal bend should behave like a short circuit. In that case, losses should be zero and the impedance seen into port 1 is the same as the input impedance of the circuitry attached to port 2. For practical bends this is not true for two reasons: 1) electrical delay between ports 1 and 2 due to the non-zero length and 2) the bend does not behave like a pure transmission line. This last effect causes the two impedances to be different even if the bend is connected to the characteristic impedance of the corresponding line dimension. Most likely, this is related to the airbridges in the signal line and the concentration of the electric field at the corners of the bend. This effect was studied by comparing the bends with pieces of transmission line that have the same length. Both were modelled by the equivalent circuit in Figure 8.1. The discrepancies between the component values determine how much different the bend is behaving from a transmission line. Figure 8.4 shows the absolute (C bend C line ) and relative ((C bend C line ) /C bend ) difference for the capacitance. It shows that, although both spacing and width change, the difference in capacitance depends predominantly on the width. Furthermore, the relative difference is approximately 50 percent. The larger capacitance is indicative of field crowding because the capacitance introduced by the airbridges, calculated using a parallel-plate approximation, is negligible. Figure 8.5 shows the results for the resistance and inductance. The resistance is somewhat higher than that of a transmission line. These deviations depend mostly on the spacing, and become more pronounced at smaller values. The relative difference in inductance has a more random nature and is not so large as the other components.

128 Orthogonal Elements Figure 8.4: Absolute and relative difference in capacitance. Each symbol corresponds to a different (w,s) combination. Figure 8.5: Relative difference in resistance and inductance. Each symbol corresponds to a different (w,s) combination. In conclusion, the right-angle nature of the bend introduces extra capacitance and resistance compared to a straight transmission line. As a result, the losses in the bend are somewhat higher than in the transmission line. Measurements indicate a loss of 0.05± 0.03dB at 10GHz for all structures. Using a different layout for the bend can decrease the change in component values. Techniques like chamfering the corners [2], also known as mitering, using a step change in signal line width [3], and applying a dielectric overlay [4], can produce better results. However, the first two techniques involve a reduction in metal cross section, increasing the risk of electromigration. The last technique requires a more complicated processing scheme. Currently, there is no indication that these structures are necessary. 8.3 Coplanar T-junctions and Crosses 8.3.1 Measurements on Multi-Ports Because T-junctions and crosses have more than two ports, these structures cannot be measured in one visit. A solution to this problem is to use multiple measurements in which we terminate the ports that are not probed with a known impedance. This approach, suggested by Rautio [5], allows the S-parameters of the multi-port to be determined using n(n 1)/2 measurements, where n stands for the number of ports. The termination of a port consists of a probe that is terminated by a 50Ω load. To determine the properties of the probe-load combination, we use a delay line that we terminate at port 2 with this combination. Using the measured reflection coefficient at port 1, we can compute the reflection coefficient of the probe-load combination: Γ load+probe = Γ DE 11 DE 12 DE 21 + DE 22 (Γ DE 11 ) (8.4) where DE represents the S-parameter measurement of the delay line, and Γ the measured reflection of the terminated line.

"! "! 8.3 Coplanar T-junctions and Crosses 129 2 ' 2 ' ) ) ) 2 $! 2 $! ) ) * Figure 8.6: Measurement configurations for a measurement between ports 1 and 2 (A) and ports 1 and 3 (B). NA 1 stands for port 1 of the network analyzer. P630 and P911 identify the probes that were used for the termination with 50Ω. Table 8.2: Measurement matrix for a cross and/or T-junction. This table indicates what is connected to each port of the structure for each measurement M ij between ports i and j. Measurement port 1 port 2 port 3 port 4 M 12 NA1 NA2 P630 P911 M 13 NA1 P630 NA2 P911 M 34 cross only P911 P630 NA1 NA2 M 41 cross only NA2 P911 P630 NA1 M 24 cross only P630 NA1 P911 NA2 M 32 cross only P911 NA2 NA1 P630 To determine the properties of both the cross and the T-junction we use two different orientations of probes and terminations as illustrated in Figure 8.6. By rotating the cross or T-junction we obtain the measurement matrix given in Table 8.2. For a T-junction only the first two measurements are performed, the remaining measurements can be found from M 23 = M 13 because of symmetry considerations. Here, M ij represents the S-parameters measured between ports i and j. Similarly, for the cross only the first three measurements are done. The remaining measurements can be found from M 32 = M 41 = M 24 = M 13. All measurements are assumed to be symmetric, e.g. M ij = M ji. Rautio [5] describes an analytical solution to compute the true n-port S-parameter matrix from these measurements. A necessary condition is however that the terminations at each port must be known and that only one termination is associated with each port. This condition is met for the T-junctions, where each port is associated with P 630 only. For crosses this condition does not hold. For instance, port 3 is terminated by P 630 or

130 Orthogonal Elements P 911 depending on the measurement that is performed. For the crosses an alternative technique was used [5]. It is an iterative technique in which the four-port S-parameters ( 4 S) can be found from [6]: S Γ it S tj t S 4 S ij = 2 rj S ij S it S tr Γ r 1 S rr Γ r + Γ S tj r S ir S rj 1 S tt Γ t S tr Γ r S rt Γ t 1 S rr Γ r 1 S tt Γ t S ir S rt Γ t (8.5) This equation states how to compute the four-port S-parameters if ports t and r are terminated by Γ t and Γ r, respectively 3. The 4 x 4 matrix 2 S ij is filled with measurement data according to: 2 S = M11 12 M12 12 M12 13 M12 13 M21 12 M22 12 M12 13 M12 13 M12 13 M12 13 M11 34 M12 34 M12 13 M12 13 M21 34 M22 34 (8.6) where M 12 21 represents S 21 of measurement M 12. The iteration process starts by using 2 S as starting point for 4 S. Then use Eq. (8.5) to re-calculate 4 S until the values converge. Typically, this situation is obtained after a few (< 5) iterations. 8.3.2 Development of a Scalable Model The procedure described in the previous section yields the true n-port data of the structure. Like for the bend, we have to de-embed the adaptors and the pieces of transmission line between the adaptors and the actual structure. To find the S-parameters of the de-embedded n-port we must: Measure a delay and through that have the same width and spacing as ports 1 and 2 of the structure. Use the Heinrich model to compute the line capacitance. Calculate γ and Z 0 and the S-parameters of the adaptor using the TRL algorithm described in the previous chapter. Repeat the steps above for ports 3 and 4. Measure the cross or T-junction. Compute the true n-port data as described in the previous section. Remove the adaptors at all ports. Remove 5 w 30 microns of transmission line at all ports using γ and Z 0, which were determined earlier, to shift the reference plane to the beginning of the airbridge. 3 The notation assumes that t < r.

8.3 Coplanar T-junctions and Crosses 131 Having determined the S-parameters we can calculate the values for the components of the equivalent circuit in Figure 8.1. For the T-junction we find: For the cross we have: C 1 (ω) = C 4 (ω) = 1 = 1 k=3 jωz 1 ω Im Y 1k (8.7) k=1 1 = 1 k=3 jωz 4 ω Im Y 3k (8.8) k=1 α(ω) = Y 12 (8.9) Y 13 L 2 (ω) = Im(Z 2) = 1 ( ) ω ω Im α (8.10) Y 12 (1 + 2α) L 3 (ω) = Im(Z 3) = 1 ( ω ω Im α 2 ) (8.11) Y 12 (1 + 2α) R 2 (ω) = Re(Z 2) = 1 ( ) α Re (8.12) ω ω Y 12 (1 + 2α) R 3 (ω) = Re(Z 3) = 1 ( α 2 ) Re (8.13) ω ω Y 12 (1 + 2α) C 1 (ω) = C 4 (ω) = 1 = 1 k=4 jωz 1 ω Im Y 1k (8.14) k=1 1 = 1 k=4 jωz 4 ω Im Y 4k (8.15) k=1 α = 1 + Y 34/Y 13 (8.16) 1 + Y 12 /Y 13 2α β = (8.17) αy 12 /Y 13 1 L 2 (ω) = Im(Z 2) = 1 ( ) ω ω Im αβ (8.18) Y 13 (4α + 2αβ + 2β) L 3 (ω) = Im(Z 3) = 1 ( ) ω ω Im β (8.19) Y 13 (4α + 2αβ + 2β) L 5 (ω) = Im(Z 5) = 1 ( ) ω ω Im α (8.20) Y 13 (4α + 2αβ + 2β) R 2 (ω) = Re(Z 2) = 1 ( ) αβ Re (8.21) ω ω Y 13 (4α + 2αβ + 2β) R 3 (ω) = Re(Z 3) = 1 ( ) β Re (8.22) ω ω Y 13 (4α + 2αβ + 2β) R 5 (ω) = Re(Z 5) = 1 ( ) α Re (8.23) ω ω Y 13 (4α + 2αβ + 2β)

132 Orthogonal Elements Figure 8.7: Modelled and measured S 12 (left) and S 13 (right) of a T-junction. Figure 8.8: Modelled and measured S 12 (left) and S 13 (right) of a cross. Like for the bend, the inductors and resistors are averaged in the 1-30GHz band whereas the capacitors are averaged between 30 and 50GHz. For each component we now have a single value corresponding to a particular combination of w 1, s 1, w 3, and s 3. The next thing to do is to find a suitable function that can describe the components as a function of these variables. Guidelines for finding such a function, as well as the functions used for this work, can be found in Appendix C.6. 8.3.3 Results Figure 8.7 presents a comparison between the scalable model and measurements for a T-junction with dimensions w 1 = 45, s 1 = 75, w 3 = 50, and s 3 = 45, all in microns. Figure 8.8 illustrates the same comparison but now for a cross with similar dimensions. These figures show the excellent agreement that is obtained by both models. The errors made by the models are listed in table 8.3.

8.4 Summary 133 Table 8.3: Relative errors (%) of the scalable models for the T-junction and cross determined in the [8-12]GHz band (x) and the [1-30]GHz band (w). structure S 12 (w) S 12 (x) S 13 (w) S 13 (x) RMS(S) at 10GHz CROSS minimum 1.5 1.0 0.6 0.4 0.7 average 3.5 1.7 1.7 0.9 1.4 maximum 7.4 4.2 3.4 1.8 2.1 T-JUNCTION minimum 0.9 0.7 0.3 0.3 0.5 average 2.7 1.7 1.0 0.8 1.7 maximum 7.6 3.7 2.3 1.7 3.6 The root mean square (RMS) value was determined according to: RMS(S) = i 0.5 ((S meas,ij S mod,ij ) /S meas,ij ) 2 /n tot j (8.24) where S meas,ij and S mod,ij are the measured and modelled S ij, respectively, and n tot the number of ports squared. The losses introduced by the T-junction and cross were computed using: ( ) ( Pout k 1 S 1k 2 ) Loss = 10 log = 10 log (8.25) 1 S 11 2 P in The loss computed this way corresponds to the situation in which a signal enters port 1 with the other ports terminated with 50Ω. For the T-junctions a (minimum, average, maximum) loss of (0.02, 0.06, 0.11)dB was found at 10GHz. For the crosses these numbers were (0.02, 0.12, 0.22)dB. 8.4 Summary Scalable models have been developed for coplanar bends, T-junctions and crosses. The accuracy of these models in the X-band is on the order of 2 percent, at 30GHz the errors increase to about 5 percent. The measurements needed for the development of the models were obtained using a normal LRM calibration. To perform the orthogonal measurements the probes and cables were carefully re-oriented. This option proved to be superior to an orthogonal SOLT calibration. A series of two-port measurements was used to compute the S-parameters of the T- junction and the cross. For this technique, the ports that were not connected to the network analyzer were terminated by a known load. An iterative technique yielded the properties of the cross while an analytic solution was available for the T-junction.

134 REFERENCES References [1] S. Basu and L. Hayden, An SOLR Calibration for Accurate Measurement of Orthogonal On-Wafer DUTs, IEEE Microwave Theory and Techniques Symposium Digest, p. 1335, 1997. [2] A.A. Omar, Y.L. Chow, L. Roy, and M.G. Stubbs, Effect of Air-Bridges and Mitering on Coplanar Waveguide 90 degrees Bends: Theory and Experiments, IEEE MTT-S International Microwave Symposium Digest, no. 2, p. 823, 1993. [3] T.M. Weller, R.M. Henderson, S.V. Robertson, and L.P.B. Katehi, Optimization of MM-Wave Distribution Networks Using Silicon-Based CPW, IEEE MTT-S International Microwave Symposium Digest, no. 2, p. 537, 1998. [4] R.N. Simons and G.E. Ponchak, Modeling of Some Coplanar Waveguide Discontinuities, IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 12, p. 1796, 1988. [5] J.C. Rautio, Techniques for Correcting Scattering Parameter Data of an Imperfectly Terminated Multiport when Measured with a Two-Port Network Analyzer, IEEE Transactions on Microwave Theory and Techniques, vol. 31, no. 5, p. 407, 1983. [6] T.Y. Otoshi, On Scattering Parameters of a Reduced Multiport, IEEE Transactions on Microwave Theory and Techniques, vol. 17, no. 9, p. 722, 1969.

Chapter 9 Capacitors and Resistors 9.1 Introduction Capacitors and resistors are important components in matching and biasing networks. Crucial features of these networks, like the location of the pass-band in the frequencydomain, depend on the values of these elements. Accurate models are therefore a necessity. These components can be placed in series or connected to ground, see Figure 9.1. Both types will be studied in this chapter. The series capacitor contains an adaptor and a taper on either side. In between is the actual capacitor, which consists of a 200nm SiNx layer that is sandwiched between the bottom and top plate. This SiNx layer covers the entire sample except for places where gold is electroplated. It even covers the NiCr layer used for the resistors that are discussed later on. An airbridge connects the top plate of the capacitor to the signal line. The capacitor to ground is mainly the same structure except for the fact that the bottom plate is a large metal area, which connects to both grounds. A second taper is therefore obsolete. For both structures the top plate is square. The series resistor also contains two adaptors and two tapers. Its resistance comes from a 125nm NiCr layer, a metal alloy that has a high specific resistance. One can control the total resistance by varying the width, length and thickness of this layer. Like the capacitor to ground, the resistor to ground does not have the second taper. The NiCr layer ends directly on a large ground plane. In both structures, 100µm tapers are used to make a transition from the adaptor to the dimensions of the capacitor or resistor. These tapers need to be de-embedded if accurate models for the resistors and capacitors are to be obtained. For this work only tapers are used that make the transition from the (w = 45µm, s = 75µm) geometry to the geometry of the capacitor/resistor (table 9.1 lists the dimensions of the components that were fabricated). As a consequence, the work done in this chapter is only valid if the resistors/capacitors are applied in a design that uses the (45,75) transmission line geometry. But as will be demonstrated next, a taper model can be constructed that allows this work to be applied to other geometries as well. 135

M M M M 136 Capacitors and Resistors F = J A @ ) K J F F = J A = E H > H E @ C A F = J A @ ) K = E H > H E @ C A F = J A @ ) K > J J F = J A 5 E N J = F A H % = @ = F J H I " + C @ + I A H E A I J = F A H = @ = F J H E + H I " 4 I A H E A I 4 C @ Figure 9.1: MIMCAP and NiCr resistor in a series and ground configuration. The definitions for width, height and length are the same for both configurations.

M I 9.2 Tapers 137 Table 9.1: Relevant dimensions (in microns) of the resistors and capacitors in Figure 9.1. All structures have been realized in a ground and series configuration. The top plate of the capacitor is a square with sides of w microns. structure w(idth) s(pacing) l(ength) Capacitor [10, 20 40 n.a. (10 X)..100] Resistor [10, 20 40 [20, 40, 80 (24 X) 40, 80] 160, 320, 640] = @ = F J H I J = F A H = @ = F J H! M Figure 9.2: Taper layout (left) and segmentation approach (right). The dotted lines in the figure on the right represent the taper that is modelled by 3 transmission lines in series. 9.2 Tapers To determine the properties of the taper we use the layout as depicted in the left-hand side of Figure 9.2. In this figure, the adaptor on the left has the (45,75) geometry while the adaptor on the right has the (w 2 = [10, 20...100], s 2 = 40) geometry (see table 9.1). The approach used to determine the properties of the taper is straightforward. The adaptors on both sides can be determined using the TRL algorithm of chapter 7, after which they can be de-embedded from the overall measurement. An intuitive way to model the taper would be to use segments of transmission lines, as illustrated in the right-hand side of Figure 9.2. To verify this technique, the S-parameters of the de-embedded taper were compared with a model that uses 5 transmission lines of equal length. The difference between w 1 and w 2, and between s 1 and s 2, was distributed evenly. For instance if w 2 = 85µm and s 2 = 35µm, the segments would be 20µm in length and would have the dimensions (45,75), (55,65), (65,55), (75,45), (85,35), all in microns 1. Figure 9.3 illustrates the S-parameters of a taper that makes the transition between the (45,75) and (30,40) geometry. In the same figure, data is plotted corresponding to 1 This particular taper was not fabricated.

138 Capacitors and Resistors Figure 9.3: Modelled and measured S 11 (left) and S 12 (right) of a (45,75) to (30,40) taper; no C is included. Figure 9.4: Modelled and measured S 11 (left) and S 12 (right) of a (45,75) to (30,40) taper; C = 0.95fF. the segmentation approach. Using more than three line segments did not improve the fit. Nevertheless, five elements are used throughout this thesis. Taking a closer look at Figure 9.3, one notices that the magnitude of S 12 exceeds 0dB, which is impossible for passive devices. This can be related to the influence of the large adaptors. Keep in mind that the combined length of the adaptors exceeds 800µm, which is very large compared to the taper (100µm). Also, the losses in the taper are very small. Any overestimation of the losses in the adaptor will result in amplification in the taper. This problem will most likely occur at low frequencies (< 10GHz) where the losses of both taper and adaptor are very low. The same figure shows that the deviation in the phase of S 12 is about 1 degree at 20GHz. This can be improved by adding a capacitor between the input and the output of the taper. However, in doing so, the fit of S 11 degrades. Inspection of the Y -parameters shows that if a term jωc is subtracted from each element in the Y -matrix, an improvement in all S-parameters can be obtained. This corresponds to adding a capacitor C between ports 1 and 2 and adding 2C between both ports and ground.

9.3 Capacitors 139 Table 9.2: Relative errors (%) made by the taper model. Z in,1 and Z in,2, computed using S 11 and S 22, respectively, stand for the relative errors in input impedance. (x) = [8-12]GHz (w) = [1-30]GHz. S 12 (x) Z in,1 (x) Z in,2 (x) S 12 (w) Z in,1 (w) Z in,2 (w) C = 0 min 0.4 1.4 1.0 1.1 8.1 6.0 ave 0.9 2.0 1.7 1.9 9.0 7.4 max 1.1 2.5 2.3 2.3 10.2 8.6 C 0 min 0.2 1.0 1.0 0.6 4.9 3.1 ave 0.2 1.4 1.3 0.9 6.0 4.1 max 0.3 1.7 1.5 1.6 7.0 5.3 For each taper a value for C was determined, see Appendix C.3. For the tapers of interest this value was around 1fF. Figure 9.4 illustrates the improvement that can be achieved by adding the capacitance. This technique should be regarded as mathematical fine-tuning. The influence of this capacitance can probably be neglected in most circuits. Table 9.2 demonstrates the accuracy that was achieved with this model. A distinction is made between the model with and without the capacitors. The simplicity of the model allows the extension of the work described in the remainder of this chapter to dimensions other than the (45,75) geometry. For instance, if we want to use a capacitor in a (100,20) line geometry we simply use the same capacitor only with a different taper. 9.3 Capacitors Knowing the characteristics of the taper, we can determine the properties of the actual capacitor. Looking back at Figure 9.1, we can see that there are three elements that have to be removed from the overall measurement: Adaptor (45,75): Determined using the TRL algorithm. Taper (45,75)-(x,40): Simulated using the model described in the previous section. Transmission line: Small pieces of transmission line are located between the actual capacitor and the taper. A capacitor in series contains a piece of 70µm and 100µm, while a capacitor to ground only has a line of 100µm to be removed. These lines are simulated using the Heinrich model discussed in chapter 7. We will use the equivalent circuits illustrated in Figure 9.5 to model the capacitors. Apart from the actual capacitance (C), these models contain additional components to model the signal propagation through the structure. Again, the objective is to determine the

140 Capacitors and Resistors 4 + 4 + + + + + I A H E A I + C @ Figure 9.5: Equivalent circuits used for modelling a capacitor in series and to ground. component values for every fabricated device and to try and describe them with a suitable analytical function. Both models contain too much components to allow for direct computation at each frequency point. We therefore have to match the circuits in the frequency-domain. Because both models resemble π-networks, it is convenient to use Y -parameters. For the equivalent circuit of a capacitor in series we find: Y 12 = 1 jωl + 1 jωc + R = We now define an effective capacitance (C eff ) using: ( ) 1 Im Y 12 jωc 1 ω 2 LC + jωrc = 1 = (1 ω2 LC) ωc eff ωc (9.1) (9.2) This relation was used for each value of w to compute the inductance (L) and capacitance (C) for the capacitor in series. The corresponding resistor (R) can easily be determined from: ( ) 1 R = Re (9.3) As a consistent frequency dependence for this component could not be found, its value was found by averaging between 1 and 50GHz. The input and output capacitances C 11 and C 22, respectively, were found by an optimization routine that minimized S meas S mod 2. Equations that describe the components mentioned above as a function of the width of the top plate can be found in Appendix C.4. A comparison between the measured and modelled effective capacitance for a capacitor with a top plate of 20 20µm 2 can be found in Figure 9.6. For the same capacitor, a comparison between measured and modelled reflection (S 11 ) and transmission (S 12 ) is illustrated in Figures 9.7 and 9.8, respectively. Because the capacitor to ground is a one-port, which has a capacitor C 11 to ground at its input, an approach similar to Eq. (9.1) could not be employed. Instead an iterative technique was used that is based on the assumption that the losses in the capacitor are very low. In this case the magnitude of the reflection coefficient will be one leaving only its phase containing useful information. The values for the components in the equivalent circuit can then be determined using the following steps: Y 12

9.3 Capacitors 141 Figure 9.6: Modelled and measured 1/C eff versus frequency. Top plate is 20 20µm 2. Figure 9.7: Modelled and measured S 11 of a capacitor in series. Top plate is 20 20µm 2. Figure 9.8: Modelled and measured S 12 of a capacitor in series. Top plate is 20 20µm 2. Figure 9.9: Modelled and measured phase of S 11 of a capacitor to ground. Top plate is 50 50µm 2. Use an optimization technique to find values for C, C 11 and L that provide the best fit to the angle of S 11 for a given R (take R = 0 as starting value). Practice has shown that this approach does not depend strongly on the starting point of the optimization. Using the values found in the previous step, use another optimization to find the value for R that gives the best fit to the measured S 11. Use the newly-found value for R to re-calculate the other components in the first step. After a limited amount of iterations (< 5) a stable solution was found for all elements. Suitable functions, which describe the component values as a function of w, can be found in Appendix C.4. Figure 9.9 illustrates a comparison between modelled and measured values of the reflection coefficient for a capacitor with a top plate of 50 50µm 2.

142 Capacitors and Resistors Table 9.3: Relative errors (%) made by the capacitor models. Z in,1 and Z in,2, computed using S 11 and S 22, respectively, stand for the relative errors in input impedance. (x) = [8-12]GHz (w) = [1-30]GHz. S 12 (x) Z in,1 (x) Z in,2 (x) S 12 (w) Z in,1 (w) Z in,2 (w) Series min 0.4 0.8 0.8 1.5 3.2 2.5 ave 0.7 1.3 0.8 3.1 4.4 4.3 max 1.3 3.1 2.6 5.7 8.0 5.6 Ground min 0.6 1.5 ave 1.4 3.8 max 2.2 6.0 Apart from small correction terms, C scales with the area of the top plate for both the series capacitor and the capacitor to ground. The capacitor process has an average capacitance density of 284pF/mm 2. Table 9.3 demonstrates that both models are sufficiently accurate for X-band design. 9.3.1 Breakdown Mechanisms The breakdown field of SiNx is approximately 1 10 7 V/cm [1], which for a 200nm dielectric would amount to 200V. At these field strengths, avalanche effects cause a rapid increase in current causing irreversible damage to the device. Therefore, the voltage range in which the capacitors can be used is much smaller than this maximum voltage. An explanation can be found by looking at the current-voltage characteristics of these devices. Figure 9.10 depicts the low-bias behavior of a capacitor with a top plate of 20 20µm 2. From this figure, a parallel resistance of 1.3TΩ can be calculated. At high bias (> 60V), the characteristics show an exponential behavior. This corresponds to the Frenkel-Poole current mechanism. At low bias, electrons that reside within traps in the SiNx layer have to overcome an energy barrier (Φ t ) to participate in current transport. For high bias, the applied electric field (E) lowers this barrier height by an amount of qβ F P E causing a strong increase in free electrons within the SiNx. This process is called Frenkel-Poole emission. The Frenkel-Poole emission coefficient (β F P ) can be computed from: q β F P = (9.4) πɛ 0 ɛ r Effectively, electrons hop from trap to trap. This process can be described by: J = σ F P E exp ( ) (Φt qβ F P E) kt (9.5)

9.4 Resistors 143 Figure 9.10: Leakage current at low bias of a 20 20µm 2 capacitor. Figure 9.11: Frenkel-Poole current mechanism occurring at high bias for a 20 20µm 2 capacitor. where J is the current density and σ F P the Frenkel-Poole conductivity. Taking the logarithm gives: ln(j/e) = ln(σ F P ) Φ t /kt + qβ F P E/kT (9.6) The capacitor process has a capacitance density of 284pF/mm 2, which corresponds to ɛ r = 6.42. Using this value we find qβ F P /kt = 1.2 10 2 (cm/v) 0.5. Figure 9.11 shows a plot of Eq. (9.6) for the same 20 20µm 2 capacitor. The extracted slope corresponds very well to the calculated value, which further confirms the Frenkel- Poole current mechanism. The electrons that move through the SiNx can get permanently trapped resulting in charge build-up within the layer. These charges modify the electric field in the SiNx. At some point, the critical electric field will be reached and the device breaks down. Usually, this occurs near the weakest part of the SiNx layer, e.g. near a non-uniformity (particle) or an area with a high defect density. The time after which this happens depends on the applied DC bias stress. Therefore, the maximum voltage ratings of a capacitor depend on life-time specifications. 9.4 Resistors 9.4.1 Series Resistor Compared to the capacitors, a different approach will be used to extract the resistor models. Because some of the resistors are quite long, a lumped-element approach will not accurately describe the propagation delay. We will therefore try to describe the resistor as a lossy transmission line. The most obvious choice is the Heinrich model discussed in chapter 7. The de-embedding algorithm discussed in that same chapter will be used to determine the properties of the resistor per unit length. We will define the shortest resistor as a through, see Figure 9.12. This structure contains two adaptors back to back, like in chapter 7, only in this case the adaptor is a

M 144 Capacitors and Resistors = @ = F J H E + H = @ = F J H = @ = F J H = @ = F J H " H A I E I J H = @ = F J H 6 0 4 7 / 0, - ) ; A C J D 4, + + = @ = F J H J = F A H Figure 9.12: Definition of a through and delay for extraction of the resistor models. The resistor adaptor contains the (45,75) adaptor, a taper and a piece of resistor. The latter is modelled by the equivalent circuit depicted in the lower-right corner. different structure. It not only contains the (45,75) adaptor, but also a taper and half of the shortest NiCr resistor (= 10µm, see table 9.1). To find a model for the series resistor of a given width we use the following steps: Determine the line capacitance (C T ) using low-frequency (< 10GHz) S-parameter measurements on the shortest (=through) and longest resistor. The transmission line parameters are calculated using the TRL algorithm. The shortest resistor is used as through measurement whereas the other lengths are used as delay measurements. This results in five different sets of transmission line parameters, which in theory should be equal. Neglecting the line conductance, we can use the transmission line model to determine the line inductance and line resistance for each of the delays: L T = Re ( γ 2 ω 2 C T ) (9.7) R T = Re ( ) γ 2 jωc T (9.8) Ideally, the line inductance and resistance should be equal for all lengths. However, as depicted in Figure 9.13, in practice some averaging is required.

9.4 Resistors 145 Figure 9.13: Extracted line resistance for five different resistors with w=20µm (left). The graph on the right illustrates the ratio between the imaginary and real parts of the propagation constant (Eq. (9.9)) as well as the real part of γ/ ω (Eq. (9.10)). Figure 9.14: Measured and modelled S 11 (left) and S 12 (right) for a 640µm long and 40µm wide resistor after de-embedding the (45,75) adaptor. Finally, a model for the resistor adaptor is constructed. This is done by deembedding the (45,75) adaptor and taper from the resistor adaptor and using the equivalent circuit in Figure 9.12 to model the remaining part of this structure. For a lossy transmission line, in which ωl T computed from: R T, the propagation constant can be γ = ωrt C T (jωl T + R T )jωc T jωr T C T = (1 + j) (9.9) 2 This equation shows that the ratio of the imaginary and real part of the propagation constant should be one. We also find: Re ( γ ω ) = RT C T 2 (9.10)

146 Capacitors and Resistors Both ratios are indicated in the right-hand side of Figure 9.13. The line resistance shows an almost flat behavior with respect to frequency. This was to be expected because the skin depth is very large due to the low conductivity. To determine the line resistance and inductance in the skin-effect regime, Heinrich s model uses Wheeler s incremental inductance rule. This rule becomes less accurate for very thin metal layers with high resistivity [2, 3]. Heinrich s model was used to simulate the resistor structures, but relatively high errors in excess of 20% at high frequencies stimulated the use of a different approach. Because the skin effect is not so important in this frequency range, we can use constant values for L T, C T, R T and the components of the equivalent circuit in Figure 9.12. Values for each component were found by averaging over the different lengths and frequencies (10-30GHz), resulting in a single value for a given width of the resistor. This routine has to be repeated for all four widths mentioned in table 9.1. Equations for these components as a function of width are listed in Appendix C.5. Figure 9.14 presents a comparison between this model and measurements for a 640µm long and 40µm wide resistor. Both the line resistance and the resistance of the adaptor are inversely proportional to the width of the NiCr layer and can be described by a sheet resistance of 15.6Ω/square. Using the thickness (t m ) of the deposited NiCr layer (125nm), we find a specific resistance of R sh t m = 195µΩcm, which is higher than the 108µΩcm stated on the NiCr data sheet 2. Reasons for this difference might be found in the processing of the devices. A 200nm SiNx layer, the same layer as used for the MIM capacitors, is deposited at 250 0 C on top of the resistor to stabilize its behavior in time. Furthermore, the roughness of the AlN substrate is much higher than the roughness of the Si reference sample on which the thickness of the NiCr is measured. This leads to an effectively thinner NiCr layer. 9.4.2 Resistor to Ground To model the resistor to ground we will use the information derived in the previous section. Looking back at Figures 9.1 and 9.12, we notice that a resistor to ground contains the following components: The resistor adaptor. The resistor itself minus 10µm that is already accounted for in the resistor adaptor. The ground connection. All of the components mentioned above are known from previous measurements except for the ground connection. To determine the properties of this connection we have to de-embed the other components from the overall measurement. The ground connection is modelled using an inductor and resistor in series. These components were calculated for every resistor. Scalable functions for these components can be found in Appendix C.5. The physical properties of the ground connection were not the dominant factor that determined these functions because in that case the component values should not depend 2 Goodfellow Ni(80)Cr(20) data sheet.

9.5 Summary 147 Table 9.4: Relative errors (%) made by the resistor models. Z in, computed using S 11, stands for the relative error in input impedance. (x) = [8-12]GHz (w) = [1-30]GHz. Series S 12 (x) Z in (x) S 12 (w) Z in (w) min 0.9 2.0 2.8 3.0 ave 2.1 4.7 5.6 8.4 max 4.4 8.5 10.4 12.0 Ground S 11 (x) S 11 (w) min 1.6 2.3 ave 3.3 6.5 max 9.6 18.3 on the length of the resistor. It is more likely that they account for small errors in the model of the series resistor. 9.4.3 Model Accuracy and Discussion The accuracy of the scalable models for the series resistor and resistor to ground is described in table 9.4. The results indicate that the accuracy of the models is significantly lower than that of other models described in this thesis. As already indicated in Figure 9.13, rather large differences can exist between resistors of equal width. Furthermore, the calculation of the ground connection showed a somewhat random distribution of the values for inductance and resistance. The processing of thin NiCr resistors is very sensitive to surface roughness of the AlN. Also, the inhomogeneity of the NiCr layer itself is on the order of 4 percent as measured on a Si reference sample. One a more fundamental level, the quasi-tem approximation assumes that the transverse fields are much larger than the fields parallel to the propagation direction. For very poor conductors, this might no longer be true. In that case, the transmission line as well as the de-embedding algorithm will introduce errors. All of the issues mentioned above have to be addressed if a higher accuracy is required. However, for most HPA designs, the series resistor is more important than the resistor to ground. The accuracy of this component in the X-band is sufficient. 9.5 Summary In this chapter, scalable models were developed for resistors and capacitors, both in a series and ground configuration. The scalable models for the capacitors show a capacitance density of 284pF/mm 2 using a 200nm SiNx layer. An accuracy of better than 3 percent is obtained at 10GHz for both configurations. The resistor models show a sheet resistance of 15.6Ω/square. However, the accuracy of these models is worse than that of other models

148 REFERENCES in this thesis. Still, for the series resistor an accuracy of better than 5 percent can be obtained in S 12 at 10GHz. A taper model was developed that describes the transition between the adaptor needed for on-wafer probing and the actual resistor/capacitor. The taper can be approximated by several pieces of transmission line. This model can be tuned by adding capacitors but the accuracy without these components is already sufficient. This model enables the use of the capacitors and resistors in arbitrary transmission line geometries. In the next chapter, we will look at several examples in which the capacitor is used in combination with other elements to form matching networks. This will demonstrate the validity of the models developed in this thesis. References [1] J. Scarpulla, E.D. Ahlers, D.C. Eng, D.L. Leung, S.R. Olson, and C.S. Wu, Dielectric Breakdown, Defects and Reliability in SiN MIMCAPs, GaAs Reliability Workshop Proceedings, p. 92, 1998. [2] C.L. Holloway and E.F. Kuester, Closed-Form Expressions for the Current Density on the Ground Plane of a Microstrip Line, with Application to Ground Plane Loss, IEEE Transactions on Microwave Theory and Techniques, vol. 43, no. 5, p. 1204, 1995. [3] G.B. Stracca, A Simple Evaluation of Losses in Thin Microstrips, IEEE Transactions on Microwave Theory and Techniques, vol. 45, no. 2, p. 281, 1997.

Chapter 10 Application Examples: Matching Networks 10.1 Introduction In previous chapters, scalable models were developed for many different CPW elements. In this chapter we will verify these models by combining them in matching networks. Specific features, like the pass-band and resonance peaks, will indicate to which extent we can use the scalable models to predict the performance of these circuits. The emphasis will lie on the comparison between model and measurement and not on the optimization of the design itself. The circuits in this chapter are based on the L-type matching networks discussed in chapter 6. These networks consist mainly of inductors and capacitors. In this chapter, we will use pieces of transmission line to realize the inductors. For the capacitors we can use the MIMCAPs developed in chapter 9, or we can employ a technique called stub-tuning. The latter will be explained next. 10.2 Stub-Tuning Stub-tuning relies on the fact that the reflection of a terminated transmission line varies along the line. Generally, if we terminate a transmission line with a load impedance (Z l ) at z = 0, the reflection coefficient seen looking towards the load at z = l equals: where Γ(0) = c /c + is the reflection coefficient at z = 0: Γ(z = l) = c e γl c + e +γl = Γ(0)e 2γl (10.1) Γ(0) = Z l Z 0 Z l + Z 0 (10.2) with Z 0 the characteristic impedance of the transmission line. For the input impedance we find: Z in ( l) = v( l) i( l) = Z 0 c+e +γl + c e γl = Z c + e +γl c e γl 0 1 + Γ(0)e 2γl (10.3) 1 Γ(0)e 2γl 149

150 Application Examples: Matching Networks Figure 10.1: Normalized inductance and capacitance as a function of the length of the transmission line for three frequencies. The symmetry axis of the curves corresponds to a quarter-wavelength. To the right of this axis, the curve has a phase shift of 180 degrees. The graph is periodic with λ/2. We will now look at two special terminations, a short circuit Γ(0) = 1 and an open circuit Γ(0) = 1, using a lossless line (γ = jβ). For the shorted transmission line, Eq. (10.3) becomes: and for the open line we have: Z in,short = Z 0 1 e 2γl 1 + e 2γl = Z 0 eγl e γl e γl + e γl = jz 0 tan(βl) (10.4) Z in,open = Z 0 1 + e 2γl 1 e 2γl = Z 0 eγl + e γl e γl e γl = jz 0 cot(βl) (10.5) Both impedances range from j to j depending on the length and propagation constant of the line. For lengths smaller than a quarter-wavelength, Z in,short is inductive whereas Z in,open is capacitive. We can define a normalized inductance and capacitance according to: L norm = L Z 0 = Im(Z in,short) ωz 0 = tan(βl) ω C norm = CZ 0 = Im (1/Z in,open) Z 0 ω = tan(βl) ω (10.6) The normalized inductance and capacitance, illustrated in Figure 10.1, have the same dependency on length and frequency. The data in this plot corresponds to β = 7 10 9 ω, which is a good approximation for the CPW lines discussed in chapter 7. Furthermore, Eq. (10.6) is computed as a function of length for three different frequencies. The sharp peaks occur when the length of the line equals a quarter-wavelength. Beyond these peaks both parameters have a 180 degrees phase shift. The entire graph is periodic with λ/2. Figure 10.1 can be used to quickly compute the length needed to realize a certain capacitance or inductance. For instance, if we need a capacitance of 0.1pF at 10GHz, we can use 1.3mm of open transmission line with Z 0 = 100Ω.

10.2 Stub-Tuning 151 2 -.. 5-6 2 - # M # 5 0 4 6.. 5-6 5 0 4 6 Figure 10.2: Layout for the short and open. The open is merely an adaptor without any connection, the short is an adaptor connected to a ground plane that has a width of 5w. The offset short and open have a line of 1500µm embedded in the structure. If we want to keep the length of the transmission line small while still realizing high inductance or capacitance values, we have to use lines with a high and low characteristic impedance, respectively. Another way is to increase the operating frequency, but this is usually not a design freedom. The shorted transmission line can be used directly after the transistor to cancel the output capacitance. Sometimes, this element is used not only for matching, but also for biasing the transistors. The application of the open transmission line for X-band amplifier design is limited due to size considerations. To realize capacitances larger than 0.3pF, lengths are required in excess of 2.5mm. Including these lines in the layout of the overall amplifier becomes very difficult. Furthermore, losses in the line itself become important for these dimensions. These components are however easy to fabricate and their performance can be predicted accurately. In the discussion above we have assumed a perfect short or open termination. In practice however, stray capacitances and the inductance of the ground connection cause deviations. To quantify these errors, a short and open were fabricated in the (45,75) line geometry. The layout for these components is illustrated in Figure 10.2. The characterization of both components is straightforward. The adaptor is computed using the TRL algorithm and de-embedded from the overall measurement. For the short, the remaining impedance is used to calculate the inductance of the ground connection, while the admittance is used to compute the stray capacitance of the open. These procedures are illustrated in Figures 10.3 and 10.4, respectively. To verify the extracted values we used measurements of an offset short and offset open, which are illustrated in Figure 10.2. In both cases, a (45,75) line of 1.5mm was included between the adaptor and the actual open or short. Figures 10.5 and 10.6 show the excellent agreement between simulations and measurements obtained for these components.

152 Application Examples: Matching Networks Figure 10.3: Input impedance of the short after removal of the adaptor. An equivalent inductance of 9.45pH is extracted. The real part of the impedance can be neglected. Figure 10.4: Input admittance of the open after removal of the adaptor. An equivalent capacitance of 2.20fF is extracted. The real part of the admittance can be neglected. Figure 10.5: Comparison between measurement and model for the offset short. The transmission line is modelled using the Heinrich model. Figure 10.6: Comparison between measurement and model for the offset open. The transmission line is modelled using the Heinrich model.

10.3 35-50 Ohm Matching Network 153 + C @ 6 E A F H J F H J ) @ = F J H " % % # 6 K? J E ) @ = F J H Figure 10.7: Layout for the 35 50Ω matching network. 10.3 35-50 Ohm Matching Network In this section we will look at a matching network that matches 35Ω to 50Ω at 10GHz. The layout for this circuit is illustrated in Figure 10.7. It is based on the L-type matching networks discussed in chapter 6, see Figure 6.2. All components are realized in the (45,75) line geometry. The working principle of this network will be explained using the equivalent circuit in Figure 10.8. This circuit contains only the most important elements to reduce the complexity of the analysis. For example, the T-junction is modelled using transmission lines that are perfectly connected at the center of the junction. The piece of line to the right of this center is not considered at all. We start by investigating Eqs. (6.8) and (6.9) for the L-type matching network. The inductance is realized by using a piece of transmission line, which can be approximated by a π-type network with a series inductor (L line1 ) and two capacitors (C line1 ) to ground. The necessary capacitance is realized using a capacitor to ground (C gnd ). The pieces of line 1 in between the center of the T-junction and C gnd, described by C line2 and L line2, increase the effective capacitance seen at the center. In addition, the capacitance C line1 has to be accounted for. If we neglect the capacitance C line1 at the input of the circuit, we can easily calculate the length of line needed to realize the inductance. This in turn fixes C gnd because C line2 and L line2 are properties of the T-junction and the capacitor to ground. Using this approach one finds a good approximation for the lengths of line needed as well as the dimensions of the capacitor to ground. However, due to the number of approximations made, computer optimization is always needed. These calculated values can be used as starting values for the optimization. This provides a quick and intuitive way to reach a final solution. Figures 10.9-10.10 illustrate the performance of this network. Measured data, after 1 To be more precise, this includes the piece of line between the center of the T-junction and its boundary (= 322.5µm), the taper (= 100µm), and the 70µm of line inside the capacitor to ground.

154 Application Examples: Matching Networks + C @ + E A E A F H J E A F H J + E A + E A + E A Figure 10.8: The equivalent circuit used for the 35 50Ω matching network. Figure 10.9: Transmission and reflection at port 2 in the X-band (8-12GHz). Port 1 is referenced to 35Ω, port 2 to 50Ω. Figure 10.10: Magnitude and phase of S 12 (left) and S 22 (right). Port 1 is referenced to 35Ω, port 2 to 50Ω. removal of the adaptors, is compared to simulations based on the scalable models derived in the previous chapters. The most important parameters of the network are the reflection and transmission parameters in the target frequency band (8-12GHz), illustrated in Figure 10.9. Model and measurement agree very well, although losses are somewhat underestimated, which might be related to the Heinrich model discussed in chapter 7. 10.4 2-to-1 Combiner An extension of the matching network discussed in the previous section is the 2-to-1 combiner illustrated in Figure 10.11. This circuit, which is also based on the (45,75) line geometry, can be used to combine the signals from sources connected to ports 1 and 2. For this circuit, the input impedance at ports 1 and 2 is 25Ω, which is different than the 50Ω seen at port 3.

N 10.4 2-to-1 Combiner 155 + C @! + C @ F H J 6 E A 6 E A 6 K? F H J ) @ = F J H " % % # 6 K? J E 6 K? J E ) @ = F J H + C @ # 6 E A 6 K? J E ) @ = F J H F H J! Figure 10.11: Layout for the combiner circuit. Apart from the transmission lines, all the components used in this layout have identical values. + C @ + E A + C @ + E A " E A E A E A! E A " F H J F H J! + E A + E A! + E A + E A + E A! + E A " Figure 10.12: Equivalent circuit for the combiner. The part of the circuit inside the box represents one of the upper branches of the combiner. This circuit is connected to the lower branch twice.

156 Application Examples: Matching Networks Figure 10.13: Magnitude (left) and phase (right) of S 31. Ports 1, 2 and 3 are referenced to 25Ω, 25Ω and 50Ω, respectively. Figure 10.14: Magnitude of S 33. Figure 10.15: S 31 and S 33 in the X-band (8-12GHz). To explain how the device works we will use the equivalent circuit depicted in Figure 10.12. The part of the circuit inside the dotted box represents one of the two matching networks in the upper part of the layout. It is similar to the network in Figure 10.8. This part of the circuit matches the 25Ω at ports 1 or 2 to 50Ω seen at the center of the upper left or upper right T-junction, respectively. The remaining part of the circuit constitutes a third matching network. Its boundaries are the center points of the upper left, upper right and lower T-junction. In the equivalent circuit, C line3 and L line3 represent the equivalent line length between these points. Because the upper left and upper right networks are connected in parallel, the impedance seen into these circuits is 25Ω 2. The third network therefore also has to match 25Ω to 50Ω. The same capacitors can therefore be used in all three branches. Figures 10.13-10.15 illustrate the reflection and transmission seen at port 3. In these figures, as well as the figures that will follow, ports 1 and 2 are referenced to 25Ω, whereas 2 Of course we have to account for the pieces of line between the center points of the middle and outer T-junctions.

10.5 Conclusions 157 Figure 10.16: Magnitude of S 11 (left) and S 12 (right). port 3 is referenced to 50Ω. The reflection in the X-band is below 16dB while the transmission is about -3.5dB. Ideally, the power entering port 3 should be split equally over ports 1 and 2 resulting in S 31 = 3dB. Losses in the components cause the attenuation of 0.5dB. Although the reflection at port 3 is low, reflections at ports 1 and 2 are not, see Figure 10.16. This can be explained by looking at the input impedances in the center of the T- junction in the middle of the layout. Neglecting line lengths, we see an input impedance of 50Ω looking towards port 1 and port 2, while we see 25Ω looking towards port 3. Hence, port 3 is matched but ports 1 and 2 are not. Furthermore, ports 1 and 2 are not isolated as illustrated by a non-zero S 12 in Figure 10.16. This circuit was designed to minimize reflections seen at port 3. If other design goals are pursued better reflection and isolation properties can be obtained for ports 1 and 2. However it can be shown that a perfect match at all ports using only lossless reciprocal elements cannot be obtained [1]. 10.5 Conclusions The matching networks presented in this chapter demonstrate the validity of the approach used to develop scalable models in the previous chapters. Although the circuits developed in this chapter are not ideal, which was also not the main objective, they demonstrate that model and measurement agree very well. Size considerations limit the applicability of stub-tuning. Replacing a capacitor to ground by a open transmission line requires impractical lengths for most X-band applications. The open and shorted transmission lines are however easy to model and fabricate. References [1] D.M. Pozar, Microwave Engineering. Addison-Wesley, 1990.

158 REFERENCES

Chapter 11 Conclusions 11.1 HEMTs on AlGaN/GaN Heterostructures GaN-based HEMTs are excellent candidates for high-power, high-frequency applications. The high electron saturation velocity (1.5 10 7 cm/s) and critical electric field (3.3MV/cm) allow these devices to be operated in the high-power, high-frequency realm, far exceeding other semiconductor material systems. The wide band gap (3.44eV) of GaN not only allows the fabrication of blue to ultraviolet light emitting devices, it also predicts an inherent quality of chemical and thermal robustness. The GaN material system usually has a wurzite crystal structure. Strong polarization fields exist within the material even when it is fully relaxed. These fields can be described by equivalent fixed polarization charges that reside at the interfaces in the material. This mechanism allows the realization of undoped AlGaN/GaN structures that contain very large (> 10 13 /cm 2 ) electron sheet densities. The polarization charges at the AlGaN/air and AlGaN/GaN interface set up an electric field that drives electrons towards the quantum well channel at the AlGaN/GaN interface. These electrons originate from states at the AlGaN surface. In this respect, the GaN-based material system is completely different from traditional materials like GaAs or InP, in which dopant atoms are responsible for the electrons in the channel. The first problem to be tackled in device fabrication is the isolation of adjacent devices. In this thesis, reactive ion etching processes were developed that provide suitable etch rates for GaN and AlGaN layers. By adding SF 6 to the existing Ar:SiCl 4 chemistry, etch rates as high as 125nm/min were achieved for etching GaN. To etch AlGaN, this compound cannot be used due to the formation of non-volatile Al-F species. The next step in device fabrication are the metal-semiconductor contacts. The general theoretical framework for these components was modified to include the influence of the polarization fields. A detailed description of the energy band diagram revealed how the electron sheet density increases with AlGaN thickness, as long as the physical boundaries of material relaxation are respected. For the ohmic contacts, the Ti/Al/Ni/Au metallization scheme was optimized. Thicknesses as well as thickness ratios of the different layers were varied independently. In addition, annealing time and temperature were investigated. This resulted in a very low contact resistance and specific contact resistance of 0.2Ωmm and 7.3 10 7 Ωcm 2, respec- 159

160 Conclusions tively. FIB and EDS analysis have shown that the metal layer stack is not maintained during the high-temperature annealing step of 900 0 C for 30s, which is most likely related to the melting of Al (melting point of 660 0 C). The balling-up of metal resulted in large clusters of Au and Al. The surface of these contacts can show height differences as much as 300nm. This could prevent accurate alignment needed for subsequent process steps. Schottky contacts were fabricated using the Ni/Au metallization scheme. Different pre-treatments, both wet and dry etching/cleaning, were tried to decrease the reverse current of these diodes. Measurements performed directly after fabrication showed the presence of a parasitic resistance of about 1MΩ irrespective of the pre-treatment that was used. This resistance effectively bypassed the diode. After lying on the shelf for two weeks, the diodes showed a remarkable decrease in reverse current (> 50%). In addition, the bypass resistor had disappeared. Instabilities in the charge distribution at the AlGaN surface or in the AlGaN layer itself might be responsible for this. Using the NH 4 OH pre-treatment, which proved to be the best option, Schottky contacts were realized that had a reverse current density of about 0.7mA/mm 2 at -20V. Although the GaN-based material system has the potential for becoming the material of choice for high-power, high-frequency applications, trap-related dispersion effects have hampered rapid progression in this field. These traps are mainly located in the buffer layer and/or at the surface of the device. In buffer-related current collapse, electrons in the highly resistive GaN buffer layer could get captured by traps after a high (> 20V) drainsource bias has been applied. The emission of electrons from these traps is characterized by very long time constants on the order of minutes to hours. Another dispersion effect is surface-related gate lag. The high electric fields that exist in the gate-drain region, especially during pinchoff, allow electrons to tunnel from the gate metal into the surface states in the gate-drain region. These electrons form a so-called virtual gate that depletes the channel. The time constants involved with this trapping process can be much larger than the operating frequency. As a result, the maximum current swing, and therefore power output, obtained at high frequencies is much lower than one would predict judging from static I-V data. The detrimental effect of gate lag can be greatly reduced using a SiNx passivation layer. In this thesis, an optimization of the HEMT process was presented that resulted in virtually dispersion-free devices. Consistent results were obtained on different AlGaN/GaN structures, both doped and undoped. Several important changes had to be made to the original processing scheme. Firstly, the etching power had to be reduced to 70W to avoid excessive leakage. Secondly, a 100nm SiNx passivation layer was introduced that reduced the amount of surface-related dispersion in all cases. Thirdly, a mild Ar plasma was introduced in between the evaporation and the annealing of the ohmic contacts. The idea behind this process step was to free the surface of any contaminants as they could react with the AlGaN surface during the high-temperature annealing step. The added value of this process has been demonstrated using AlGaN/GaN submicron transistors on sapphire that showed an output power density of 2.9W/mm at 4GHz. These results correspond to the power output predicted using static I-V data, which shows that, under the measurement conditions, these devices have negligible dispersion.

11.2 Passive Components on AlN 161 11.2 Passive Components on AlN A high-power amplifier contains more than just active elements. Passive components are needed to provide the interconnect and impedance matching between different amplifying stages. Several technologies exist, like microstrip or coplanar waveguide, in which these passive components can be realized. Microstrip is the most mature interconnect technology and is, unlike coplanar waveguide technology, well implemented in commercial circuit simulator software. It does however require a via-hole connection between the top of the substrate and metal ground plane on the back. This presents a technological challenge regardless which substrate is used. In addition, advanced etching techniques are required that were unfortunately not available. All passive components were therefore realized in a coplanar waveguide technology on ceramic AlN. This substrate material was chosen for its excellent thermal and electrical properties. A technology base was set up for several different types of components on AlN. The first component that was realized was the coplanar transmission line. The dimensions of these elements, especially the spacing between the signal and ground lines as well as the width of the signal line itself, determine the modes that may propagate through the structure. Ideally, only the quasi-tem wave should propagate. Choosing the dimensions of the line too wide causes a parallel-plate mode to propagate, which results in highly dispersive behavior at high frequencies (> 30GHz). Measurements of lines that demonstrated quasi-tem behavior were matched to an analytical model that was based on conformal mapping. After implementing some correction terms to account for processing artifacts, like lithography offset and metal profiles, this model was able to predict the propagation constant with an accuracy of better than 3% at 10GHz. These results could not have been obtained without the development of a new deembedding algorithm. This algorithm was used to remove the influence of the adaptors, the two structures between the probes and actual device, from the overall measurement. This algorithm is based on the TRL calibration algorithm for network analyzers though some modifications were introduced to account for complex line impedances. Without these modifications, some elements showed amplification at low frequencies. Next, orthogonal elements like bends, T-junctions and crosses were fabricated and modelled. The same de-embedding algorithm was used to derive equations that describe the performance of these components as a function of geometry. On average, the models matched measurements with an accuracy of better than 5% at 10GHz. The same approach was followed for SiNx-based MIMCAPs and NiCr resistors. Models were derived for these components both in a series and to ground configuration. The SiNx capacitors showed a capacitance density of 284pF/mm 2 and could be operated well above 100V. The leakage current for these devices corresponded to the Frenkel-Poole current mechanism. Accuracies of better than 4% were achieved at 10GHz. The NiCr resistor process had a sheet resistance of 15.6Ω/square and was used to fabricate resistors in the 2Ω-2kΩ range. The accuracy of the resistor models was somewhat worse than for the other components, but was still better than 10% at 10GHz. A possible reason could be the uniformity of the NiCr layer on the relatively rough AlN surface. Two different matching networks were designed using the models described above. The first matching network was a two-port device that matched 35 to 50Ω, the second device

162 Conclusions was a three-port that matched port 3 (50Ω) to ports 1 and 2 (both 25Ω). Both circuits were designed for the X-band (8-12GHz). Simulated and measured data demonstrated the applicability of the coplanar component library for future X-band high-power amplifier design. 11.3 Concluding Remarks The work described in this thesis covers almost every component needed to realize a high-power amplifier based on AlGaN/GaN HEMTs. In addition, a complete library of passive CPW components has been setup, which enables a fast and accurate design of the necessary matching networks. Maybe the most important result from this thesis is the HEMT process developed in chapter 5. Especially the use of the Ar plasma significantly improved performance. This is probably related to some change in the nature or density of surface states. It is likely that changing the substrate from sapphire to SiC, GaN or AlN, will influence the behavior of these states. This could therefore require some tuning of the process. Still, the use of these substrates is inevitable if power densities in excess of 5W/mm are required. In general, the success of GaN for electronic applications will depend on the ability the suppress the different dispersion phenomena in this material system. Even if all these issues have been solved, it remains unclear if it can become a commercial success in the electronic market. It will most certainly become an important material system for military applications where cost requirements are less stringent. Whether it will ever rise out of this niche market remains an open question.

Appendix A Waveguide Circuit Theory A.1 Introduction In electric circuit theory, the behavior of each element is characterized by the impedance matrix that relates terminal voltages and currents. The definition of voltage originates from electrostatic theory. Strictly speaking, voltages are only defined in the case of timeindependent magnetic fields. In that case the curl of the electric field vanishes and we can write the voltage as a path integral of the electric field. The actual value is independent of the path followed. In the microwave realm it becomes difficult to speak of voltage. The actual value of the voltage depends on the definition or to be more specific, on the integration path. Hence, it is impossible to define an unambiguous voltage and current like in the low-frequency case. Waveguide circuit theory provides an analogy between low-frequency electric circuit theory and the electromagnetic description of waveguides or other waveguide components. The objective is to reduce the complex electromagnetic problem to the much simpler waveguide voltage and current description. This approach is more suitable for engineering and is more easy to comprehend. However, the waveguide voltage and current depend on definition and normalization. Another difference with their low-frequency counterparts is that they are related to travelling waves. The scattering matrix (S) is another way to describe components. This matrix relates two quantities a and b that represent incident and reflected waves, respectively. These quantities are related to the waveguide voltage and current. Compared to the impedance matrix (Z), this description has the advantage that it is more accessible for measurement. It does not rely on the measurement of voltage and current, which is impossible in most cases. The travelling waves a and b can be measured accurately using a network analyzer. By determining the ratios of the incoming and outgoing waves, the S-matrix of the device under test can be determined. If needed, transformation formulas can be used to transform the scattering matrix into the impedance matrix. In this chapter we will briefly review the waveguide circuit theory proposed by Marks and Williams [1, 2]. It provides a definition of waveguide voltage, current and characteristic impedance that is power normalized and causal. This theory deviates from the more common theory based on power waves [3, 4, 5, 6], which is used in commercial circuit 163

164 Waveguide Circuit Theory simulators today. A crucial difference between the two theories is related to reciprocity. This difference played an important role in the accurate modelling of coplanar transmission lines in chapter 7. Another difference is the way in which the travelling waves a and b are defined. This results in different transformation formulas for conversion between the scattering and impedance matrices. In this chapter, we will demonstrate some counterintuitive consequences if the more conventional formulas are used. It is important to remember that the review given below is merely a short summary of the actual theory, most of the mathematical proof has been left out for clarity. A.2 Waveguide Voltage, Current and Characteristic Impedance Assume a waveguide that is uniform and infinitely long in the z direction. In this case, the Maxwell equations are separable and many linear independent solutions exist, each representing a different mode. In this chapter we will only look at the behavior of a single mode although the theory can be extended to include multiple modes [7]. We will denote the solution of the transverse ( z) electric and magnetic field of a single mode by e t and h t, respectively. These fields have an arbitrary but fixed normalization. Because e t /α n and h t /α n with α n complex, are also solutions, we have a degree of freedom in choosing e t and h t. Using a fixed normalization means that we keep α n constant at an arbitrary value. The general solution for the transverse fields will consist of a linear combination of the forward and backward propagating modes: E t (ω, r t, z) = [c + (ω)e γz + c (ω)e +γz ] e t (ω, r t ) (A.1) H t (ω, r t, z) = [c + (ω)e γz c (ω)e +γz ] h t (ω, r t ) (A.2) where γ is the propagation constant, ω the angular frequency, r t the transverse position, and c + and c complex functions of frequency. We now define the waveguide voltage (v) and current (i) using: v(ω, z) E t (ω, r t, z) = v 0 (ω) e t(ω, r t ) (A.3) H t (ω, r t, z) = i(ω, z) i 0 (ω) h t (ω, r t ) (A.4) where v 0 and i 0 represent the frequency-dependent normalization for the voltage and current, respectively. This normalization allows v and i to have the normal dimensions of voltage and current. Like in electric circuit theory, the voltage and current are proportional to the electric and magnetic fields, respectively. When only the forward propagating mode is present (c = 0, c + = 1), the waveguide voltage and current equal v 0 e γz and i 0 e γz, respectively. The ratio between these quantities is called the characteristic impedance (Z 0 ) of the mode: Z 0 (ω) v(ω, z) i(ω, z) c =0 = v 0(ω) i 0 (ω) (A.5)

A.2 Waveguide Voltage, Current and Characteristic Impedance 165 At this point the definition of the voltage and current normalization v 0 and i 0 is arbitrary. Restrictions can be imposed if we require that the complex power through the waveguide, like in electric circuit theory, is given by: p = 1 2 vi (A.6) Complex power transported through a waveguide can be computed by integrating the Poynting vector over cross-section A: p = 1 E t H 2 t da (A.7) Combining Eqs. (A.3), (A.4) and (A.7) gives: p = 1 E t H 2 t da 1 vi = 2 v 0 i 0 Comparing this with Eq. (A.6) gives: v 0 i 0 p 0 = A A A A e t h t d A e t h t d A (A.8) (A.9) Using this result we can see that the power criterium fixes the argument of the characteristic impedance: ( ) ( ) ( v0 p0 v0 2 ) Z 0 = = = i 0 2 = p 0 (A.10) i 0 This result is independent of the field normalization. In fact, it is a property of the mode. The magnitude of the characteristic impedance is still arbitrary. Also, v 0 and i 0 can still be chosen arbitrarily although the argument of their product is fixed. Writing Eqs. (A.3) and (A.4) in the time-domain exposes an interesting correlation between the different parameters 1 : p 0 ˆ E t (t, r, z) = ˆv(t, z) e ˆ tn (t, r) (A.11) ˆ H t (t, r, z) = î(t, z) ˆ htn (t, r) (A.12) where e ˆ tn = ˆ e t /v 0, h ˆ tn = ˆ ht /i 0, and stands for convolution in the time-domain. We would like that the description of the waveguide is causal, i.e. waveguide voltage and current are simultaneous with ˆ Et and ˆ Ht, respectively. If this were not the case, we would have a waveguide voltage at some point in time without the electric field it refers to, or vice versa. For arbitrarily chosen v 0 and i 0, simultaneity is not achieved. Re-writing the convolution integral in Eq. (A.11) gives: ˆ E t (t, r, z) = + ˆv(τ, z) e ˆ tn (t τ, r)dτ (A.13) 1 In the remainder of this section, ˆf stands for the function f in the time-domain.

166 Waveguide Circuit Theory which shows that ˆ Et and ˆv can only be simultaneous if etn ˆ starts at t = 0. A similar argument holds for ˆ htn. Williams and Alpert have demonstrated a construction algorithm for v 0 (ω) and i 0 (ω) such that e ˆ tn and ˆ htn indeed start at t = 0 [2]. This ensures that v and E t, and i and H t, are simultaneous. In that same paper, the authors show that waveguide voltage, current, and characteristic impedance are all fixed to within a constant multiplier, if the conditions of causality and simultaneity are imposed, together with the aforementioned power criterium. A.3 The Scattering Matrix A.3.1 Travelling Waves As discussed in the previous section, travelling waves propagate through the waveguide. It therefore appears more intuitive to try and characterize the waveguide in terms of waves than using voltages and currents. An obvious choice is to investigate the properties of the travelling waves [1]: a = b = Re(p 0 )c + e γz = Re(p 0 )c e +γz = Re(p 0 ) 2v 0 (v + iz 0 ) (A.14) Re(p 0 ) 2v 0 (v iz 0 ) (A.15) These equations represent multiples of the travelling waves of Eq. (A.1) and (A.2). If we take the magnitude of these waves at z = 0 and subtract we get: a 2 b 2 = Re(p 0 ) ( c + 2 c 2) (A.16) To understand the meaning of this equation we look at the real part of the complex power: 1 2 Re(vi ) = 1 [ 2 Re v0 2 ( c + 2 c 2 ) Z0 2j v 0 2 ] Im(c + (c ) ) Z0 = 1 2 Re(p 0) ( c + 2 c 2) + Im(p 0 )Im(c + (c ) ) (A.17) where Eqs. (A.1)-(A.4) were used. This equation represents the time-averaged real power transported through the waveguide. If Z 0 is real or when either a = 0 or b = 0, Eq. (A.17) reduces to: 1 2 Re(vi ) = 1 ( a 2 b 2) (A.18) 2 This means that the transported power is the difference in power carried by the forward and backward waves 2. 2 If we had defined v and i as RMS values the factor 2 would have vanished.

A.3 The Scattering Matrix 167 The behavior of a n-port can be characterized using the S-matrix: b 1. b n = S 11... S 1n.... S n1 S nn a 1. a n (A.19) where n stands for the number of ports. The advantage of using the scattering matrix compared to other methods, like the Z-matrix, is that it is more susceptible to measurement. It does not rely on the measurement of current and/or voltage, which is impossible in most cases. The travelling waves a and b can be measured using a network analyzer or by using voltage standing wave ratio (VSWR) techniques. A.3.2 Power Waves Although the a and b waves defined in the previous section are intuitive, they do not form the basis of modern circuit simulators. Most of the microwave analysis is based on a different definition of these waves, which may cause problems in some cases. Unfortunately, these cases apply to the work described in this thesis. We begin our analysis by looking at the power waves a and b defined by Kurokawa and Youla [5, 6]: a = v + Zi (A.20) 2 Re(Z) b = v Z i 2 Re(Z) (A.21) where v and i are the waveguide voltage and current, respectively, and Z an arbitrary reference impedance, although 50Ω is mostly used. When Z = Z 0 is real, these relations are similar to Eqs. (A.14) and (A.15) derived in the previous section, apart from the phase difference v 0 /v 3 0. Hence, these waves are travelling waves only if the reference impedance is real and equal to the characteristic impedance of the waveguide. These waves however have the interesting property that the real part of the complex power can be computed from: 1 2 Re(vi ) = 1 ( a 2 b 2) (A.22) 2 for every Z. This relation was also derived in the previous section for the specific case when Z 0 is real. Because network analyzers are mostly calibrated using real impedances, the power waves remain a useful concept. Due to the fact that the definition of the a and b waves is different, the transformation formulas used for conversion between S- and for instance Z-parameters must be different as well. Even changing the reference impedance of the S-matrix is different when Z is complex. Next, we will demonstrate two cases for which analysis based on power waves produces counterintuitive results. 3 In Eqs. (A.14) and (A.15) apply Re(p 0 ) = Re( v 0 2 /Z 0 ) = v 0 Re(Z 0 )/ Z 0.

168 Waveguide Circuit Theory 6 @ 4 6 @ / 6 @ + 6 @ @ Figure A.1: Equivalent circuit of a waveguide of length dz. Complex termination of a transmission line. Consider a transmission line (Z 0 is complex) of arbitrary length that is connected to a load (Z l ) at z = 0. The value of this load is such that: Z l v (A.23) i Using the travelling wave definition in Eqs. (A.14) and (A.15) we find for the reflection coefficient at z = 0: Γ(z = 0) b = v iz 0 = iz l iz 0 = Z l Z 0 (A.24) a z=0 v + iz 0 iz l + iz 0 Z l + Z 0 If we choose Z l = Z 0 we end up with the familiar result that there is no reflection if a transmission line is terminated with its characteristic impedance. If however, we use the definition of the power waves in Eqs. (A.20) and (A.21) we find: Γ(z = 0) b = v iz 0 = iz l iz0 = Z l Z0 a z=0 v + iz 0 iz l + iz 0 Z l + Z 0 (A.25) If we now set Z l = Z 0 we find that the reflection coefficient is not zero. Both definitions of the reflection coefficient are only equivalent when Z 0 is real. Time-delay. Consider a piece of transmission line with complex Z 0 of length l. Using Eqs. (A.14) and (A.15) we find the familiar result: S = ( e γl 0 0 e γl ) (A.26) Here we made explicit use of the fact that a and b are travelling waves. If we had used power waves this expression would be invalid as these waves are not travelling waves. A.4 The Transmission Line Model In this section we will develop an equivalent circuit model to describe a waveguide. The equivalent circuit we will investigate is illustrated in Figure A.1.

A.4 The Transmission Line Model 169 This model represents a portion of the waveguide with length dz. The voltage and current in this circuit represent the waveguide voltage and current. They are related by: dv dz = (jωl T + R T )i (A.27) and di dz = (jωc T + G T )v (A.28) We compare these relations with the derivatives of the waveguide voltage and current: dv dz = d(c+ e γz + c e +γz ) dz di dz = 1 d(c + e γz c e +γz ) Z 0 dz = γz 0 i (A.29) = γ Z 0 v (A.30) where Eqs. (A.1) and (A.2) were used. Combining Eqs. (A.27)-(A.30) yields: and γ = Z 0 = (jωl T + R T )(jωc T + G T ) (jωl T + R T )/(jωc T + G T ) The elements R T, L T, C T and G T can be computed from the modal fields using [1]: C T = 1 v 0 2 L T = 1 i 0 2 G T = R T = ω v 0 2 ω i 0 2 ɛ e t 2 da µ h z 2 da A A A A A µ h t 2 da ɛ e z 2 da A ɛ e t 2 da + µ h z 2 da A µ h t 2 da + ɛ e z 2 da A (A.31) (A.32) (A.33) (A.34) (A.35) (A.36) where h z and e z are the magnetic and electric fields along the z direction, respectively, ɛ = ɛ jɛ the complex electric permittivity, and µ = µ jµ the complex magnetic permeability. Metal conductivity is included in ɛ. If the waveguide supports TEM modes we can choose v 0 equal to the potential difference between two conductors. In this case, C T v 0 2 dz/2 gives the time-averaged stored electrical energy in a piece of transmission line of length dz. In other words, C T represents the capacitance per unit length. Similarly, L T is the inductance per unit length and G T the conductance per unit length, which is related to the dielectric losses. R T, the resistance per unit length, accounts for the magnetic and ohmic losses. All these parameters are equal to their low-frequency counterparts from electric circuit theory. This makes them susceptible to measurement. In chapter

170 REFERENCES 7 we made use of this fact when we measured C T using a low-frequency capacitance measurement. For non-tem modes, the similarity between electric circuit theory and the definitions in terms of modal fields is less obvious. For instance, the presence of a z-component in the integral above makes that the capacitance is not equal to the capacitance measured at low frequencies, especially when the measurement frequency is below the cut-off frequency of the mode. References [1] R.B. Marks and D.F. Williams, A General Waveguide Circuit Theory, Journal of Research of the National Institute of Standards and Technology, vol. 97, no. 5, p. 533, 1992. [2] D.F. Williams and B.K. Alpert, Causality and Waveguide Circuit Theory, IEEE Transactions on Microwave Theory and Techniques, vol. 49, no. 4, p. 615, 2001. [3] C.G. Montgomery, R.H. Dicke, and E.M. Purcell, Principles of Microwave Circuits. McGraw-Hill, 1948. [4] R.E. Collin, Foundations for Microwave Engineering. McGraw-Hill, 1966. [5] K. Kurokawa, Power Waves and the Scattering Matrix, IEEE Transactions on Microwave Theory and Techniques, vol. 13, no. 3, p. 194, 1965. [6] D.C. Youla, On Scattering Matrices Normalized to Complex Port Numbers, Proceedings IRE, vol. 49, p. 1221, 1961. [7] R.B. Marks, L.A. Hayden, and D.F. Williams, A Complete Multimode Equivalent- Circuit Theory for Electrical Design, Journal of Research of the National Institute of Standards and Technology, vol. 102, no. 4, p. 405, 1997.

Appendix B Processing of CPW Elements on AlN B.1 Properties of Ceramic AlN Table B.1: Properties of ceramic AlN substrates. Source: Stellar Industries data sheet. Property Units Grade AlN purity % > 97 Color Tan Density g/cm 3 3.28 Dielectric constant (25 0 C, 1GHz) 1 8.5-9.2 Dissipation factor (1GHz) 1.0005 Volume resistivity Ωcm > 10 14 Thermal conductivity (25 0 C) Wm 1 K 1 170 Thickness inch 0.02 Surface roughness nm 50 B.2 Process Flow Clean with BHF (2 ) and rinse in D.I. water (5MΩ). Clean with acetone and iso-propyl alcohol (spray bottle). Deposition of a thin (50nm) SiNx layer. AZ5214 recipe for definition of NiCr resistors, for lithography settings see table B.2. Ar:SF 6 etch to remove SiNx: RIE 105W, 40mTorr, 10:10sccm, t=90. Sputtering of NiCr layer. Use bare Si reference sample to tune process. Thickness on Si should be 125nm. 171

172 Processing of CPW Elements on AlN Table B.2: Process settings for resist types AZ5214, AZ4533 and AZ4562. process step AZ5214 AZ4533 AZ4562 spinning 5000rpm/30 5000rpm/30 5000rpm/30 bake 95 0 C/5 95 0 C/20 95 0 C/20 flood exposure UV300/2 N.A. N.A. bake 105 0 C/5 N.A. N.A. exposure UV300/45 UV400/30 UV400/60 develop (1:1) t=45 t=90 t=150 rinse in D.I.water 5MΩ 5MΩ 5MΩ bake N.A. 125 0 C/30 105 0 C/30 Ultrasonic lift-off in acetone (in beaker glass!). Clean with iso-propyl alcohol afterwards. AZ5214 recipe for definition of transmission lines, capacitors and metal interconnect for resistors. BHF etch to open the SiNx layer, tune for etch rate. This step could be omitted. In that case, all components except the resistor would be on a thin SiNx layer. The use of an Ar:SF 6 plasma to open the SiNx layer, has resulted in large resistances between the NiCr layer and the subsequent connect metal. Applying high voltages annihilates this interfacial layer. Ti/Au 50/200nm. Ultrasonic lift-off in acetone (using teflon holder). Clean with iso-propyl alcohol afterwards. Deposition of 200nm SiNx (dielectric layer for the capacitors). AZ5214 recipe for definition of the top plate of the capacitors. Ti/Au 50/200nm. Ultrasonic lift-off in acetone (using teflon holder). Clean with iso-propyl alcohol afterwards. AZ4533 recipe for Au electroplating. Ar:SF 6 plasma to open the SiNx layer: RIE 105W, 40mTorr, 10:10sccm, t=180. Ti/Au 50/200nm seed layer for Au electroplating. AZ4562 recipe for Au electroplating. No cleaning before applying resist!

B.2 Process Flow 173 Au electroplating for t=15. Current=80mA and 8.5 < ph < 9.5. Thickness should be 4µm. Rinse in D.I. water (5MΩ). Flood exposure for t=6 using UV400. Develop in AZ:DI=3:1 for at least 5. All the AZ4562 should be removed from the sample. Rinse in D.I. water (5MΩ). No cleaning afterwards with acetone as this might dissolve the AZ4533 underneath the seed layer and cause the metal to tear off! Degussa solution for t=90 to etch the Au part of the seed layer. Watch the color change as the Ti layer appears. Rinse in D.I. water (5MΩ). Oxalic acid for t=4 (use dummy for tuning as this solution is difficult to make!). Recipe: Dissolve 4g of C 2 H 2 O 4.2H 2 O (M=126.07g/mol) in 50ml H 2 O 2 (concentration 30%). Make a KOH solution (2M, i.e. 5.6g KOH per 50ml H 2 O) and add this to the previous solution so that the PH of the combined solution equals 8. Rinse in D.I. water (5MΩ). Ultrasonic lift-off in acetone (using teflon holder) to remove AZ4533 resist. Clean with iso-propyl alcohol afterwards. If the sample is not clean enough use RIE O 2 plasma (20W, 50sccm, 100mTorr, t=5 ) to clean.

174 Processing of CPW Elements on AlN

Appendix C Scalable Models C.1 Functions for the Adaptor L[pH] = 10 exp(2.05 0.0279w 0.5 + 1.93 10 7 s 3 ) (C.1) R[Ω] = 0.142 + 165w 2 2.56 10 5 exp( s) (C.2) with w and s in microns. C 1 = C 2 = 0.01pF. C.2 Functions for the Bend with w and s in microns. C[fF] = 16.6 + 4.57 w + 10 3 s 1.5 (C.3) L[nH] = 0.1 0.286 + 0.0514 w + 73.8/s (C.4) R[ΩHz 0.5 ] = 10 6 (2.36 0.161 ln(w) 8.12 10 3 s ) (C.5) C.3 Functions for the Taper with w 2 in microns. C[fF] = 1.267 52.27 w 1.5 2 (C.6) C.4 Functions for the Capacitor Capacitor in series C[pF] = w 2 (2.80 10 4 2.58 10 7 w ) (C.7) C 11 [ff] = 13.7 936/w 2 (C.8) 175

176 Scalable Models C 22 [ff] = 1.87 + 0.241w (C.9) L[pH] = 56.4 (C.10) R[Ω] = 1/w (29.5 0.214w) (C.11) with w in microns. Capacitor to ground C[pF] = w 2 (2.88 10 4 5.15 10 9 w 2) (C.12) C11[fF] = 2.0 (C.13) L[pH] = 18.7 (C.14) R[Ω] = 12.5/w (C.15) with w in microns. C.5 Functions for the Resistor Resistor in series with w in microns. Resistor adaptor with w in microns. 1.56 107 R T (Ω/m) = (C.16) w L T (H/m) = 10 7 (7.40 0.375w 1.5) (C.17) C T (F/m) = 10 12 ( 4.60 10 3 + 149w ) 0.5 (C.18) Resistor to ground (additional equations) R(Ω) = 164 (C.19) w L(pH) = 21.1 0.0119w 1.5 (C.20) C11(fF) = 10 (C.21) C22(fF) = 5 (C.22) with l and w in microns. L(pH) = l ( 4.4 + 1.85 10 5 w 3 ) w R(Ω) = l (0.38 + 90.8/w2 ) w (C.23) (C.24)

C.6 Finding a Suitable Multi-Variable Function 177 C.6 Finding a Suitable Multi-Variable Function In chapter 8 we had to solve the problem of finding a function F (w 1, s 1, w 3, s 3 ) that could describe the component values L, C and R. To find a suitable function we started off by inspecting the behavior of the components keeping w 1 and s 1 fixed. A fitting program called Tablecurve3D 1 was used to fit selected data, e.g. data with the same w 1 and s 1, to an extensive list of functions that depended on two variables. Not all of the available functions were used. For instance, higher order (>3) polynomials will provide a good fit to the data but are not suitable for scaling. The objective is to find a function that provides a reasonable fit for all subsets with constant w 1 and s 1. Let us assume that such a function looks like: F (w 3, s 3 ) = a + b/w 3 + cs 3 (C.25) with a, b and c constants. These constants depend on the subset that is used, i.e. on w 1 and s 1. We now expand this function into: F (w 1, s 1, w 3, s 3 ) = c(0) + c(1)/w 1 + c(2)/w 2 + c(3)/(w 1 w 2 ) + c(4)s 1 + c(5)s 3 + c(6)s 1 s 3 (C.26) where c(n) are constants. The coefficients of this function can be determined uniquely by a least-squares routine. The accuracy of this method can be improved by adding more terms. However, one should be careful that the resulting functions are smooth so that interpolation will yield realistic values. C.6.1 Functions for T-junctions and Crosses The technique described in the previous section was used to determine functions for L, C and R for the models of the T-junction and the cross. The equation used for modelling the inductances looks like: L(w 1, s 1, w 3, s 3 ) = c 0 + c 1 w 1 + c 2 s 1 + c 3 w 3 + c 4 s 3 + c 5 w 1 s 1 + c 6 w 1 w 3 + c 7 w 1 s 3 + c 8 s 1 w 3 + c 9 s 1 s 3 + c 10 w 3 s 3 + c 11 w 1 s 1 w 3 + c 12 w 1 s 1 s 3 + c 13 w 1 w 3 s 3 + c 14 s 1 w 3 s 3 + c 15 w 1 s 1 w 3 s 3 (C.27) For modelling the resistances the following equation is used: R(w 1, s 1, w 3, s 3 ) = c 0 + c 1 /w 1 + c 2 /s 1 + c 3 /w 3 + c 4 /s 3 + c 5 /(w 1 w 3 ) + c 6 /(w 1 s 3 ) + c 7 /(s 1 w 3 ) + c 8 /(s 1 s 3 ) The capacitances are described by: + c 9 /(w 1 w 3 s 3 ) + c 10 /(s 1 w 3 s 3 ) + c 11 /(w 1 s 1 w 3 ) + c 12 /(w 1 s 1 s 3 ) + c 13 /(w 1 w 3 s 1 s 3 ) (C.28) C(w 1, s 1, w 3, s 3 ) = c 0 + c 1 w 3 + c 2 (ln(s 3 )) 2 + c 3 w 1 + c 4 w 1 w 3 + c 5 w 1 (ln(s 3 )) 2 + c 6 (ln(s 1 )) 2 + c 7 w 3 (ln(s 1 )) 2 1 version 2, AISN Software. + c 8 (ln(s 3 ) ln(s 3 )) 2 (C.29)

178 Scalable Models The coefficients c n are determined using a least-square routine using the component values determined for each (w 1, s 1, w 3, s 3 ) combination. The results for the T-junction and the cross are given in tables C.1 and C.2, respectively. Table C.1: Coefficients for the T-junction. coefficients L2 L3 R2 R3 c0 7.87E-01-3.41E-01 8.97E-01 3.10E-01 c1-4.10e-03 1.81E-02-1.12E+01 1.35E+00 c2 9.80E-03 4.64E-02 1.12E+01-3.14E-01 c3 2.54E-03 7.87E-03-5.57E+00-1.07E+01 c4 3.19E-02 2.33E-02-2.47E+00 9.43E+00 c5 3.83E-05-1.98E-04 6.15E+02 1.10E+01 c6 9.42E-05-2.60E-04-5.58E+02-5.44E+02 c7-6.94e-05-2.23e-04 1.87E+02-9.74E+01 c8 1.42E-04-4.80E-04 2.43E+02-1.77E+02 c9 3.78E-04-8.34E-05 1.39E+04 2.97E+04 c10-1.06e-05-1.91e-04-1.84e+04 3.37E+04 c11-1.52e-06 4.91E-06-1.46E+04-7.66E+03 c12-1.83e-06 3.92E-06-5.97E+03-1.41E+04 c13 1.55E-07 3.83E-06 3.85E+05-5.86E+05 c14 8.80E-07 1.95E-06 c15-3.89e-09-6.05e-08 coefficients C1 C4 c0 4.31E-01-2.73E+00 c1 1.05E-02 2.62E-03 c2 4.10E-02 1.10E-01 c3 6.42E-03 2.08E-02 c4 1.56E-05-5.54E-05 c5 9.58E-04-1.07E-03 c6-1.33e-02 1.60E-01 c7-3.15e-04 1.05E-03 c8-6.24e-04-4.93e-03

C.6 Finding a Suitable Multi-Variable Function 179 Table C.2: Coefficients for the cross. coefficient C1 C4 L2 L3 c0-3.37e-01-8.25e-01 2.59E+00 3.03E+00 c1 8.20E-02-6.74E-02-1.99E-02-3.19E-02 c2-9.53e-02 2.06E-01 9.22E-05 1.02E-02 c3-5.86e-02 7.34E-02-2.95E-02-2.23E-02 c4-1.82e-04 2.27E-04 1.77E-02-7.46E-03 c5 4.24E-03-3.84E-03 2.11E-04 4.46E-04 c6 1.60E-01-5.05E-02 4.22E-04 3.95E-04 c7-3.67e-03 4.07E-03 1.36E-04 3.97E-04 c8-9.34e-04-3.69e-03 3.36E-04 1.96E-04 c9 5.30E-04 7.27E-04 c10 3.88E-04 2.69E-04 c11-5.07e-06-5.44e-06 c12-3.93e-06-5.16e-06 c13-5.34e-06-5.16e-06 c14-3.06e-06-6.03e-06 c15 4.98E-08 6.97E-08 coefficient L5 R2 R3 R5 c0-5.96e-01 9.25E-01 1.29E+00-2.33E+00 c1 1.39E-03 4.79E+00 3.93E+01 6.89E+00 c2-2.72e-03 2.55E+01-2.12E+01 1.27E+01 c3 1.39E-03 5.25E+01-6.37E+00 5.02E+00 c4-2.72e-03-2.25e+01 1.90E+01 1.68E+01 c5-1.62e-05-1.06e+03-3.44e+02 5.94E+01 c6-7.62e-05-5.10e+02-9.14e+02-1.98e+02 c7-1.33e-04-1.02e+03-6.03e+02-7.09e+01 c8-1.33e-04 6.02E+02 2.76E+02-7.78E+02 c9-3.10e-04 3.30E+04 2.32E+04-1.33E+03 c10-1.62e-05-1.80e+04 1.13E+04 2.42E+04 c11 1.28E-06 2.76E+04 2.77E+04-1.35E+03 c12 1.69E-06-5.72E+03-6.95E+03 2.75E+04 c13 1.28E-06-5.02E+05-8.32E+05-5.30E+05 c14 1.69E-06 c15-3.27e-08

180 Scalable Models

List of Symbols α Real part of the propagation constant m 1 α n Normalization constant 1 β Imaginary part of the propagation constant m 1 β F P Frenkel-Poole emission coefficent (mv) 0.5 χ s Semiconductor electron affinity J d Offset of the 2DEG w.r.t. AlGaN/GaN junction m E c Conduction band discontinuity J Metal shape correction factor m δ Interfacial layer thickness m a Potential drop over the AlGaN layer V i Potential drop over the interfacial layer V 0 i i under flat-band conditions V δ s Skin depth m ɛ Electric permittivity F/m ɛ 0 Electric permittivity of vacuum F/m ɛ AlGaN Dielectric constant of AlGaN F/m ɛ eff Effective relative dielectric constant 1 ɛ int Dielectric constant of the interfacial layer F/m ɛ i Strain in direction i 1 ɛ r Relative dielectric constant 1 ɛ s Dielectric constant of the semiconductor F/m η Wave impedance in vacuum Ω Γ Reflection coefficient 1 γ Propagation constant m 1 h Planck s constant divided by 2π Js λ Wavelength m µ Magnetic permeability H/m µ 0 Magnetic permeability of vacuum H/m µ e Low-field electron mobility m 2 /(Vs) µ r Relative magnetic permeability 1 ω Angular frequency rad/s ω p Valence-electron plasmon frequency rad/s n m Recession of wall m m Φ B0 Zero-bias barrier height J Φ B Barrier height J 181

182 List of Symbols Φ 0 B Flat-band barrier height J Φ CNL Charge neutrality level J Φ CNL Charge neutrality level referenced to E c J Φ m Metal workfunction J Φ sd Semiconductor dielectric workfunction J Φ t Energy barrier for electrons in SiNx J ψ Electron wave function 1 ρ Charge density C/m 3 ρ c Specific contact resistance Ωm 2 ρ s Semiconductor specific resistance Ωm σ Conductivity S/m σ 2 Electron sheet density in the 2DEG m 2 σ F P Frenkel-Poole conductivity S/m σ G Electron sheet density at GaN/sapphire interface m 2 σ M Electron sheet density in the metal m 2 σ P 1 Equiv. polarization charge carrier density (air/algan) m 2 σ P 2 Equiv. polarization charge carrier density (GaN/AlGaN) m 2 σ P 3 Equiv. polarization charge carrier density (GaN/sapphire) m 2 σ P Equiv. polarization charge density (general) m 2 σ SS Surface charge carrier density m 2 σ std Standard deviation 1 τ Channel transit time s υ Speed of electromagnetic wave m/s E t Transverse electric field V/m e t Transverse electric field of a single mode V/m H t Transverse magnetic field A/m ht Transverse magnetic field of a single mode A/m k Wavevector m 1 n Normal vector 1 r t Transverse position vector m r Position vector m ξ E c E f in the semiconductor bulk J A Area m 2 a Incident travelling wave W 0.5 A Effective Richardson s constant A/(K 2 m 2 ) a 0 Lattice constant to the c-plane under zero strain (300K) m a Lattice constant to the c-plane m A e Area of the driven electrode in a RIE system m 2 a g Width of a shared ground plane (CPW) m b Reflected travelling wave W 0.5 C Capacitance F c Speed of light in vacuum m/s c 0 Lattice constant to the c-plane under zero strain (300K) m C 2DEG Capacitance density in the charge-control regime F/m 2

List of Symbols 183 c Lattice constant to the c-plane m C Line capacitance for ɛ r = 1 F/m C dc DC-blocking capacitance F C ds Drain-source capacitance F C d Drift-region capacitance F C gd Gate-drain capacitance F C gs Gate-source capacitance F C ij Elasticity constants N/m 2 C T Line capacitance F/m d Thickness of the AlGaN layer m d c Width of the outer circular contact (CTLM) m d eff Effective gate-to-channel spacing m d l Length of an ohmic contact (LTLM) m D MIGS MIGS density 1/(m 2 J) D s Surface state density 1/(m 2 J) DE S-parameters of delay line 1 E Electric field V/m E c Conduction band energy J E fm Metal Fermi level J E f Fermi level J E gap Bandgap energy J E gate Electric field at the drain-side of the gate electrode V/m e ij Piezoelectric constants C/m 2 E max Maximum electric field at metal-semiconductor junction V/m E photon Photon energy J E s Electric saturation field V/m E vac Vacuum energy reference level J E v Valence band energy J e z Electric field of a single mode in the z direction V/m f Frequency s 1 f max Maximum frequency of oscillation s 1 f t Cut-off frequency s 1 G conductance S g m,extr Extrinsic transconductance S G max Maximum available gain 1 g m Intrinsic transconductance S G p Power gain 1 G T Line conductance S/m h Substrate thickness m h ij H-parameters 1 h z Magnetic field of a single mode in the z direction A/m I Current A i Waveguide current A i 0 Waveguide current normalization A I ac AC current A

184 List of Symbols I dc DC current A I ds,max Maximum drain-source current A I ds,pulsed I ds measured under pulsed conditions A I dss I ds at V gs = 0V A I ds Drain-source current A I e Electron current A I i Positive-ion current A I leak Gate leakage current A I pinchoff Drain-source current under pinchoff A J Current density A/m 2 J s Reverse saturation current density A/m 2 K Rollet stability factor 1 k Boltzmann s constant J/K K j Reciprocity factor for port j 1 L Inductance H l Length m L choke RF choke inductor H L drift Length of the drift region m L ds Drain inductance H L e Line inductance if conductors are perfect H/m L gs Gate inductance H L g Length of a transistor gate m L i Internal line inductance H/m L s Source inductance H L T Line inductance H/m L t Transfer length m M Ion mass kg M ij kl S kl of a measurement between ports i and j 1 n Ideality factor 1 N D N-type dopant atom density m 3 n e Electron density m 3 n + i Positive-ion density m 3 n T Impedance transformation ratio 1 P Polarization C/m 2 p Complex power through a waveguide W p 0 Power normalization W P dc DC power W P d Dissipated power W P in Input AC power W P loss,in Loss in input matching network 1 P loss,out Loss in output matching network 1 P out Output AC power W P P E Piezoelectric polarization C/m 2 P SP Spontaneous polarization C/m 2 q Elementary charge C

List of Symbols 185 R Resistance Ω r 1 Radius of the inner circular contact (CTLM) m r 2 Inner radius of the outer circular contact (CTLM) m R c Contact resistance Ωm R ds Drain-source resistance Ω R d Drain resistance Ω R g Gate resistance Ω R in Input resistance Ω R i Charging resistance Ω R sh,c Sheet resistance underneath an ohmic contact Ω R sh Sheet resistance Ω R s Source resistance Ω R T Line resistance Ω/m s Spacing between ground and signal line m s c Spacing between ohmic contacts (CTLM) m S ij S-parameters 1 s l Spacing between ohmic contacts (LTLM) m S X Slope parameter for Schottky contacts J T Temperature K t Time s t 2DEG Effective thickness of the 2DEG m T e Electron temperature K T ij T -parameters 1 t m Metal thickness m u b Bohm velocity m/s U pg Mason s unilateral gain 1 V Potential difference V v Waveguide voltage V v 0 Waveguide voltage normalization V V ac AC voltage V V a Applied bias V V BIAS DC bias voltage V V break,off Off-state breakdown voltage V V break,on On-state breakdown voltage V V d0 Zero-bias diffusion voltage V V dc DC voltage V V ds,max Maximum drain-source voltage V V ds Drain-source voltage V V d Diffusion voltage V v e Electron velocity m/s V gd Gate-drain voltage V V gs Gate-source voltage V V gs Voltage over C gs V V in DC input voltage to the gate V V k Knee voltage V

186 List of Symbols V p Pinchoff voltage V V rf RF voltage V v sat Saturated electron velocity m/s V sh Sheath voltage V V x Channel voltage V w Signal line width m w d Depletion layer width m W g Width of a transistor gate m w g Width of the ground plane (CPW) m W l Width of an ohmic contact (LTLM) m x d Depletion width in the channel gate-drain region m X m Metal electronegativity 1 X s Semiconductor electronegativity 1 Y ij Y -parameters S Z 0 Characteristic impedance Ω Z ij Z-parameters Ω Z in Input impedance Ω Z l Load impedance Ω Z out Output impedance Ω Z ref Reference impedance Ω tanδ Dielectric loss tangent 1

List of Acronyms 2DEG two-dimensional electron gas AFM atomic force microscopy AlGaAs aluminum gallium arsenide AlGaInP aluminum gallium indium phosphide AlGaN aluminum gallium nitride AlN aluminum nitride BCl 3 boron trichloride BeO beryllium oxide BHF buffered hydrofluoric acid CAIBE chemically assisted ion beam etching CBCPW conductor-backed coplanar waveguide CPW coplanar waveguide CTLM circular TLM CW continuous wave DLTS deep-level transient spectroscopy ECR electron cyclotron resonance EDS energy dispersive spectroscopy FET field-effect transistor FIB focussed ion beam GaAs gallium arsenide GaN gallium nitride GaCl gallium monochloride 187

188 List of Acronyms GaCl 3 H 3 PO 4 gallium trichloride phosphoric acid HBT heterojunction bipolar transistor HCl hydrochloric acid HF hydrofluoric acid HEMT high electron mobility transistor HNPSG high nitrogen pressure solution growth HPA high-power amplifier HVPE hydride vapor-phase epitaxy ICP inductively coupled plasma InAlAs indium aluminum arsenide InGaAlN indium gallium aluminum nitride InGaAs indium gallium arsenide InP indium phosphide IPA iso-propyl alcohol KOH potassium hydroxide LDMOS laterally diffused metal-oxide-semiconductor LED light emitting diode LNA low-noise amplifier LRM line-reflect-match LTLM linear TLM MBE molecular beam epitaxy MESFET metal-semiconductor field-effect transistor MgO magnesium oxide MIGS metal-induced gap states MIMCAP metal-insulator-metal capacitor MOVPE metal-organic vapor-phase epitaxy

List of Acronyms 189 Na 2 S sodium sulfide NH 3 ammonia NH 4 OH ammonium hydroxide (NH 4 ) 2 S 2 O 8 diammonium peroxodisulphate NiCr nickel chromium ONR office of naval research PAE power added efficiency PMMA poly(methyl methacrylate) RF radio frequency RIE reactive ion etching RMS root mean square RTA rapid thermal annealing Sc 2 O 3 scandium oxide SEM scanning electron microscopy SF 6 sulfur hexafluoride SiC silicon carbide SiCl 4 silicon tetrachloride SIMS secondary ion mass spectroscopy SiNx silicon nitride SKPM scanning kelvin probe microscopy SoI Si on insulator SOLT short-open-load-through TL tubular lighting TLM transfer length method TNO-FEL TNO Physics and Electronics Laboratory TRL through-reflect-line TSD through-short-delay

190 List of Acronyms TUE Eindhoven University of Technology UMTS universal mobile telecommunications system VSWR voltage standing wave ratio WBGS wide bandgap semiconductors

Summary The gallium nitride (GaN) semiconductor material system has unique properties that make this system extremely suitable for high-frequency, high-power applications. Compared to other material systems like gallium arsenide or silicon, GaN has the potential to produce more power using a smaller chip area. A possible application for this material system could be the power amplifiers used in transmit/receive modules for radar systems. These amplifiers consist of active components, which amplify the signals, and passive components, which provide impedance matching, interconnect and biasing. In each amplifier design, these two types of components have to be combined. This can be done by fabricating both types on the same material (monolithic integration) or by using bondwires or flip-chip techniques (hybrid integration). This thesis presents a study on the possibilities for using AlGaN/GaN high electron mobility transistors (HEMTs) as building blocks for high-frequency, high-power amplifiers. In addition to HEMTs, passive components were realized in coplanar waveguide (CPW) technology on ceramic aluminum nitride (AlN) substrates. This material was chosen for its excellent thermal and electrical properties. In a typical amplifier, more than 80% of the chip-area is used by passive components. Combining passive components on AlN and active components on GaN could therefore provide a more inexpensive but highly performing solution. Because GaN is relatively new, there was no experience with this material system at the start of this research. This meant that all the steps, which are needed to design, fabricate, and measure the HEMTs, had to be developed. One of the toughest problems in the development of AlGaN/GaN HEMTs is the socalled surface-related gate lag. It refers to the observation that the power output at RF frequencies does not correspond to the power output that can be expected judging from DC characteristics. This effect is related to the charging dynamics of surface states. These states donate electrons to the channel of the transistor, but are too slow to respond to the applied signal. Gate lag can partially be solved by passivating the devices with a thin layer of silicon nitride. Within the framework of this project, a process was developed that reduced the amount of gate lag even further. This process enabled the realization of submicron transistors that showed a power output density of 2.9W/mm at 4GHz. Achieving these power levels indicates that these devices do not significantly suffer from gate lag. At the start of this project, there was little experience with CPW technology. The objective of this part of the research was to construct a component library that contains 191

192 Summary models for all components needed for amplifier design. Each of these models had to be scalable, which means that these models must be able to predict the electrical characteristics of a component as a function of geometrical parameters like width or length. A large portion of this research was devoted to the development of the fabrication technology and measurement techniques for these components. Processing and measuring more than 500 devices has resulted in a complete library, which can be used in future amplifier or filter design. In this thesis, all aspects of this topic are described. In conclusion, all separate components needed to realize a GaN-based high-power amplifier have been developed. The experience and fabrication processes that came out of this work can also be used for the design of other types of circuitry.

Samenvatting Het gallium nitride (GaN) halfgeleider materiaalsysteem bezit unieke eigenschappen die dit systeem uitermate geschikt maken als uitgangsmateriaal voor toepassingen waarbij zowel hoge vermogens als hoge frequenties een rol spelen. Vergeleken met andere materiaalsystemen als gallium arsenide of silicium heeft GaN de potentie meer vermogen te generen op hogere frequenties met behulp van een kleiner chipoppervlak. Een voorbeeld van een mogelijke toepassing is de versterkereenheid in de zend/ontvangst module van een radar. Deze kan ruwweg worden opgesplitst in twee delen, de actieve componenten die de signaalversterking verzorgen en de passieve componenten die een optimale signaaloverdracht realiseren. In een uiteindelijk versterkerontwerp dienen deze componenten gecombineerd te worden. Dit kan door beide delen op hetzelfde materiaal te implementeren (monolithische integratie) of, indien de passieve componenten op een ander materiaalsysteem zijn vervaardigd, door gebruik te maken van bonddraden of flip-chip technieken (hybride integratie). Dit proefschrift beschrijft een studie naar de mogelijkheden om het GaN materiaalsysteem te gebruiken als uitgangsmateriaal voor hoog vermogensversterkers. Voor de actieve componenten is gekozen voor high electron mobility transistoren (HEMTs) op AlGaN/GaN materiaal. Deze transistoren zijn in staat om op hoge frequenties een hoge vermogensdichtheid te produceren. De passieve componenten zijn uitgevoerd in coplanar waveguide (CPW) technologie waarbij in tegenstelling tot de meer gangbare microstrip technologie zowel de aard als de signaallijnen op de bovenkant van het materiaal worden aangebracht. Als uitgangsmateriaal voor deze componenten is gekozen voor keramisch aluminium nitride (AlN). Dit materiaal heeft goede thermische en elektrische eigenschappen en is, zeker in vergelijking met GaN materiaal, zeer goedkoop. Ongeveer 80 procent van de totale oppervlakte van de versterker wordt gebruikt door de passieve componenten. Hierdoor biedt de combinatie van passieve componenten op AlN en actieve componenten op GaN mogelijk een goedkopere maar toch goed presterende oplossing. Doordat GaN relatief nieuw is was er bij aanvang van het onderzoek geen ervaring met dit materiaalsysteem. Dit had tot gevolg dat alle stappen die nodig zijn voor het ontwerp, de realisatie en karakterisatie van de transistoren ontwikkeld dienden te worden. Een van de grootste problemen in de ontwikkeling van op GaN gebaseerde transistoren is de aan het oppervlak gerelateerde gate lag. Deze term beschrijft het verschijnsel dat de vermogensdichtheid die behaald wordt als de transistor wordt bedreven op hoge frequenties (> 1GHz) sterk kan afwijken van datgene wat men zou verwachten als men uitgaat van de DC karakteristieken. Dit effect is gerelateerd aan zogenaamde oppervlakte toestanden die enerzijds verantwoordelijk zijn voor de elektronen die zorgen voor het stroomtransport 193

194 Samenvatting maar anderzijds te traag zijn om het opgedrongen stuursignaal te volgen. Dit probleem kan gedeeltelijk worden opgelost door de transistoren te bedekken met een dun laagje silicium nitride. Binnen het kader van dit onderzoek is een proces ontwikkeld dat dit effect verder verminderd en als gevolg een aanzienlijke verbetering van de transistoren oplevert. De belangrijkste prestatie parameter voor deze transistoren, een vermogensdichtheid van 2.9W/mm bij 4GHz, is een indicatie dat gate lag bij deze transistoren nauwelijks een rol speelt. Dit komt vooral door het ontwikkelde HEMT proces dat in de toekomst zeker het speerpunt zal worden van het onderzoek. Ook op het gebied van de coplanaire technologie was er bij aanvang van dit project geen ervaring. Het doel van dit stuk onderzoek was het opzetten van een bibliotheek van componenten die nodig zijn voor het versterkerontwerp. Elk van deze componenten moest schaalbaar zijn wat betekent dat de elektrische eigenschappen van deze componenten moeten kunnen worden voorspeld als functie van geometrische parameters als breedte en lengte. De fabricagetechnologie evenals de algoritmen voor het juist karakteriseren van deze componenten vormden een essentieel deel van dit onderzoek. Het maken en karakteriseren van meer dan 500 componenten heeft uiteindelijk geresulteerd in een complete bibliotheek die in toekomstig werk kan worden gebruikt voor het ontwerp van de versterker of voor allerlei soorten filters. In dit proefschrift worden alle facetten van dit werk beschreven. Concluderend kan gesteld worden dat alle afzonderlijke componenten voor de vervaardiging van een op AlGaN/GaN gebaseerde vermogensversterker zijn ontwikkeld. De opgebouwde ervaring met het GaN materiaalsysteem en de coplanaire technologie kan ook worden toegepast voor het ontwerp van andere schakelingen.

Dankwoord In 1998 stond ik voor de keuze, of promoveren of (echt) gaan werken. Op het kritieke moment, ik had het contract van Philips Lighting al ontvangen, bood Prof. Kaufmann mij een aantrekkelijke positie aan die uiteindelijk heeft geleid tot dit proefschrift. Ik wil hem, samen met Frank van den Bogaart van TNO-FEL, bedanken voor die unieke kans. Aangezien dit project voor alle betrokkenen iets nieuws was, ben ik trots op datgene wat bereikt is. Ik wil daarom ook iedereen bedanken die aan dit onderzoek heeft bijgedragen. In het bijzonder Erik-Jan en Ben voor het draaiend houden van de cleanroom en het bedienen van niet promovendus bestendige apparatuur. Barry, voor zijn adviezen over de wonderen der chemie en het ontnemen van mijn angst wat betreft waterachtige substanties die lakmoespapiertjes doen verkleuren. Fouad, voor zijn enthousiasme en het bijbrengen van het cleanroom principe haastige spoed is altijd goed. En tenslotte Tjibbe, voor het deponeren van SiNx, een voorbeeld van very remote-plasma deposition. Wat betreft het werk buiten de cleanroom wil ik graag Thieu bedanken voor zijn hulp met de elektrische metingen, een aspect wat vaak ten onrechte onderbelicht blijft. Hans en Hans voor het tolereren van mijn Windows en Unix experimenten. Gelukkig weet ik nu dat een Unix server aan moet blijven staan. Mijn kamergenoten van het eerste uur, Roger en Omar, wil ik bedanken voor de fijne sfeer, optie-adviezen en kweekavonturen. Gedurende het onderzoek heb ik een aantal studenten mogen begeleiden. Deze hebben stuk voor stuk een belangrijke bijdrage geleverd aan dit proefschrift. Bram, die de eerste stappen in de CPW wereld deed. Boris, die in verband met zijn onderzoek aan groot signaal transistormodellen een tropisch bos door de printer heeft gestuurd. Saverio, die het electroplaten Italian Style heeft uitgevonden; een sample in de ene hand en een vrouw in de andere. En Paul, die de Schottky contacten heeft geoptimaliseerd, alhoewel de grootste verbetering in deze contacten optrad toen hij zelf niets deed (zie hoofdstuk 4.4 van dit proefschrift). Bij deze wil ik ook stilstaan bij de bijdrage die Mark heeft geleverd aan dit proefschrift. Naast de inhoudelijke zaken wil ik hem graag bedanken voor de fijne samenwerking gedurende deze jaren. De periode waarin we aan het dispersieprobleem gewerkt hebben zou ik willen omschrijven met: Het duo was meer dan de som der individuen. Veel van het werk dat beschreven staat in dit proefschrift was niet mogelijk geweest zonder het gallium nitride materiaal van de universiteiten van Nijmegen en Gent. Verder ben ik veel dank verschuldigd aan de radar groep van TNO-FEL. Enerzijds voor de financiële steun aan het project, maar ook wat betreft de sturende rol van doctor Peter, Frank en Frank. Erwin, nog bedankt voor de enorme hoeveelheid metingen. Mijn ouders wil ik graag bedanken voor de steun die ik heb mogen ontvangen al die jaren. Het is een voorrecht als je ouders ook je beste vrienden zijn. Ook mijn schoonouders, familie en vrienden wil ik bedanken voor hun interesse en steun. Nwyvrici, het is tijd om een pilsje te pakken. En tot slot, lieve Jetsie, elke keer als ik je zie besef ik hoe speciaal je voor me bent en hoe ontzettend veel ik van je houd. 195

Curriculum Vitae April 25, 1973 Born in Valkenswaard, The Netherlands 1991-1998 Student Applied Physics Eindhoven University of Technology, The Netherlands Master s Thesis entitled: Physically-Based Modelling of Induction Lamps Philips Lighting Eindhoven 1992-1998 Student Electrical Engineering Eindhoven University of Technology Master s Thesis entitled: Modelling an Al 0.2 Ga 0.8 As-In 0.15 Ga 0.85 As-GaAs phemt using ATLASII Electronic Devices group, faculty of Electrical Engineering Eindhoven University of Technology 1998-2003 Ph.D. Student Eindhoven University of Technology Ph.D. Thesis entitled: Towards Integrated AlGaN/GaN Based X-Band High-Power Amplifiers Optoelectronic Devices Group, faculty of Electrical Engineering Eindhoven University of Technology 2003-present RF Design Engineer Market Sector Team RF PA/FEM, Business Line Cellular Systems Philips Semiconductors, Nijmegen, The Netherlands 196