Boole-WebLab-Deusto: Integration of a Remote Lab in a Tool for Digital Circuits Design

Boole-WebLab-Deusto: Integration of a Remote Lab in a Tool for Digital Circuits Design Javier García-Zubía (IEEE Senior Member), Ignacio Angulo, Luis Rodríguez-Gil Faculty of Engineering University of Deusto, Avd. Universidades 24 48007 Bilbao, Spain zubia@deusto.es Pablo Orduna (IEEE member), Olga Dziabenko Deusto Institute of Technology University of Deusto, Avd. Universidades 24 48007 Bilbao, Spain pablo.orduna@deusto.es Abstract This paper describes the integration of a remote lab in a tool for educational digital circuits. Boole-Deusto is an educational software tool featuring truth tables, Karnaugh maps, Boolean expressions, finite-state machines and digital circuits. After creating the design through Boole-Deusto, the user can implement the circuit in a remote lab (WebLab-Deusto) with only a few mouse clicks. The user does not need the technical knowledge, time, hardware equipment and specialized software that would normally be required. These conveniences benefit teachers and students alike, especially those involved in basic courses in digital electronics, both at the university and high school levels. Keywords remote labs, digital electronics, software design tools I. INTRODUCTION Current lessons on digital electronics are usually based on books, exercises, and lab practices. The learning process starts with theory. Then students design some exercises and finally some of these are implemented using different technologies (74XX IC, VHDL/Verilog, CPLD, FPGA...). With this approach, students learn how to design and implement different digital circuits. Simulators and other educational software tools help teachers and students. However, professional tools like Proteus [1], Pspice [2] or Electronics WorkBench, EWB [3] do not always cover all the educational requirements. Some areas (such as Karnaugh maps) are often neglected. On the other hand, educational tools tend to cover those neglected areas, but to have a very narrow scope. An example of such a tool is the Karnaugh Map Minimizer [4]. Though Boole-Deusto is also an educational software tool, it tries to cover a larger base of educational requirements, including the full design of basic bitlevel digital circuits. Nonetheless, Boole-Deusto should not be compared with professional tools, as their focus tends to be on the circuits rather than the design process itself. Whether they are using simulators or not, students should eventually implement the digital circuit using 74XX IC, VHDL/Verilog, etc. To do this this, students and teachers would typically move to a purposely-equipped laboratory to carry out this experience. However, for several years, there has been another possibility: to use a remote laboratory. These labs have been considered as part of the Five Major Shifts in 100 Years of Engineering Education [5]. There is a high amount of remote labs for digital electronics [6-9], but most often they are intended for a single, particular device such as a FPGA, CPLD or microcontroller, but without a more general, educational approach. The main objective of this work is to integrate Boole- Deusto [10][11] with the WebLab-Deusto [12] remote lab, both Open Source projects. Through this integration, teachers and students can design a basic digital circuit under the educational approach provided by Boole-Deusto (involving truth tables, Karnaugh maps, Boolean expressions ), and after this they can implement it in a remote lab with only a few mouse clicks, and requiring only Boole-Deusto and an Internet connection. The process is very straightforward, and no wiring, particular technical knowledge or hardware such as board programmers is needed, nor specialized software such as development studios. The paper describes in Section II the Boole-Deusto software for combinational and sequential bit-level digital systems. Section III is devoted to a general perspective on the WebLab-Deusto remote laboratory. The integration of Boole- Deusto and WebLab-Deusto is illustrated with examples in Section IV. The paper finishes with the conclusions and future work in Section V. II. BOOLE-DEUSTO SOFTWARE TOOL FOR DIGITAL ELECTRONICS DESIGN Digital electronics circuits can be classified in two groups: combinational circuits and sequential circuits, depending on whether they have memory (and are hence sequential) or not. Depending on the complexity of the circuits, they can be divided in bit-level and word-level circuits (see Fig. 1). In the first case the circuit is described bit by bit using a truth table (combinational circuits) or a Finite State Machine (sequential circuits). 978-1-4673-5261-1/13/$31.00 2013 IEEE

Since 2003, Boole-Deusto has been downloaded thousands of times [14]. Fig. 3 shows the download statistics from the official Boole-Deusto web page (since 2007 only more download sources exist, so the full download count would be significantly higher). Fig. 1. Digital circuits classification The Boole-Deusto open-source tool was deployed for the first time in 2000 [13] for designing bit-level digital circuits, both of the combinational and sequential types. The design of these circuits can be seen as a transformation along different representations of the system. These representations can be of textual, numerical, logical, graphical or mathematical nature. In the design of a combinational circuit (see Fig. 2), the student reads the statement and after understanding it, fills the truth table. It is then converted to Karnaugh maps that are solved to obtain minimized Boolean expressions. These Boolean expressions are converted to digital circuits that can be implemented using AND-OR (or NAND/NOR) logic gates in 74xx IC or using a VHDL/Verilog approach. Fig. 3. Statistics of the Boole-Deusto downloads. A. Combinational circuit example with Boole-Deusto Figs 4-7 describe the design of a combinational circuit through its different representations. The description statement is: Design the circuit that switches on a led if the four bits of the input are not a BCD combination. The combinational circuit has four inputs (BCD) and one output (LED). Fig. 4. Name, inputs and outputs of the example Fig. 2. Design process of a bit-level combinational circuit. The process with bit-level sequential circuits is similar. Students will start by reading the problem statement and obtaining a FSM. After using an algorithm they will minimize that FSM. It will then be transformed into a truth table from which the K maps will be obtained. Based in the K maps, the minimized Boolean expressions will be obtained to be implemented with logic gates or in VHDL/Verilog. Boole-Deusto focuses only on the design process. A student cannot use Boole-Deusto to see how a digital circuit evolves through time. Simulation is already covered in depth by tools such as Proteus, EWB, etc. Boole-Deusto helps freshmen in digital electronics to design and implement real and basic digital circuits. Boole-Deusto was developed as an Open Source project [11] by the University of Deusto after being unable to find an existing educational tool of this kind. The truth table in Fig.5 shows that the led must be on when the inputs are 1010 1111. 0000 1001 are proper BCD, so the led will be off.

Fig. 5. Truth table of the system When the student has filled the truth table, the Karnaugh map and the solved Karnaugh map become available. This map can be solved automatically by Boole-Deusto (Fig. 6), or the student can instead try to solve it manually using the Learning Mode. Fig. 9. FSM truth tables The next step is to obtain the digital circuit (Fig. 10). Fig. 6. Solved Karnaugh map for the BCD-ERROR problem Finally, the student can obtain the matching digital circuit in both the AND-OR and the NAND/NOR versions. Fig. 10. FSM digital circuit with JK flip-flops Fig. 7. AND/OR and NAND digital circuits B. Sequential circuit, Finite State Machine In this case, the student can draw the Moore or Mealy FSM using a graphical interface, displayed in Fig. 8. The statement for this example is a sequence detector: Design the FSM that switches on the led in the output, if three or more 1s are received in the input signal Finally, the student can obtain and download the VHDL program of the FSM. C. Boole-Deusto Characteristics Boole-Deusto allows the student to control the step-by-step design of bit-level digital circuits. The student will manage FSM, truth tables, K maps, digital circuits, VHDL code, etc. When comparing Boole-Deusto with other software tools, the main difference is that Boole-Deusto takes the user through each step in the design process. Other tools focus only on the final result, neglecting aspects which are important from an educational perspective but not so much from a practical one. For instance, Proteus software, though certainly complete and professional, does not give students the opportunity of solving the Karnaugh maps themselves. Fig. 8. Moore Finite State Machine After drawing the FSM, the student can minimize it or obtain the truth tables (Fig. 9). III. WEBLAB-DEUSTO REMOTE LAB WebLab-Deusto is a remote lab created by the University of Deusto and released and developed as an Open Source project. A remote lab is a hardware & software platform that allows students to experiment remotely through the Internet as if they were in a classical lab.

WebLab-Deusto offers different remote experiments. Though it is a generic framework, currently the majority of them are related to electronics. There are also several which are connected to physics and biology (See Fig. 11). Educational Tool [15] has been deployed in different universities, including the MIT (USA). Fig. 12. WebLab-Deusto-Box for FPGA Fig. 11. WebLab-Deusto experiments (screenshot) WebLab-Deusto supports several generic advanced capabilities [16], which are shared by all experiments. These include but are not limited to federation (experiments and hardware can be shared among different WebLab-Deusto instances, in different institutions and universities), escalation and load-balancing (the number of servers can be increased very easily) and optional integration with different technologies, such as Facebook or LMSs such as Moodle. From a technical point of view, WebLab-Deusto experiments support any web browser (Chrome, Explorer, Mozilla, Opera, Safari ) in any OS (Linux, Windows ) and any device (tablet, laptop, smart phone ). Users do not need to install anything on their devices, and thus there are no local security issues. Some experiments are currently restricted and the user will require a user/password combination. For others, no registration is required. IV. BOOLE-WEBLAB-DEUSTO The main objective of this paper is to show readers the potential of the connection between Boole-Deusto and WebLab-Deusto. Fig. 13 shows the checkbox to tick when implementing in Boole-Deusto a system for WebLab-Deusto. A. Bit-level combinational circuits Fig. 13 shows the checkbox that should be checked by users when they wish to create a WebLab-compatible system easily. A. WebLab-Deusto-FPGA hardware description WebLab-Deusto offers different experiments. One of them is a FPGA: The experiment is based in a FPGA Digilent Board. The inputs (switches, buttons and clock) are controlled with a PIC Microcontroller of Microchip. A webcam and a lighting system are included to provide the user with a video stream of the behavior of the digital circuit. A FIT PC (small computer) and a modem are also included, on which the web service which interfaces with the remote laboratory framework is deployed. All these parts are integrated in a compact, purpose-built professional box. Fig. 12 shows the WebLab-Deusto-Box where the FPGA experiment is deployed. The same type of box is used to deploy other experiments, such as a CPLD. This WebLab- Deusto-Box was awarded in ICELIE/IECON 2009 for Best Fig. 13. WebLab Mode for combinational systems When users are in WebLab Mode they may then assign, for instance, switches as inputs and leds or seven_seg (sevensegment displays) as outputs. After this, users should: Define the system: name, inputs and outputs (see Fig. 14). Describe the system using the truth table or the Karnaugh maps (or other means). Save the system to VHDL code. Click in Open WebLab-FPGA (see Fig. 13). After this, Boole-Deusto will reach WebLab-Deusto through the Internet, directing your default web browser to the right WebLab-Deusto page. A user/pass combination for authentication is required, though it is only necessary to login once per session.

When the process finishes, users will have full control of the switches, buttons and clock. Fig. 16 shows that with 0000 as input, the led output is off because 0000 is a BCD combination. Fig. 14. WebLab-Deusto access web page Comment for the reviewer: please use fie2013/fie2013 as the user/pass combination. After accessing WebLab-Deusto by this means, users will be prompted to upload a file. This file should be the.vhd file they generated previously. Fig. 17. BCD-ERROR system in the WebLab-Deusto If the inputs are: 1010, then the led will be on because the combination 1010 is not BCD, as shown in Fig. 18. Fig. 15. Uploading the VHDL code to WebLab-Deusto Then, WebLab-Deusto will synthesize the VHDL code with an internally provided UCF (User Constraints File) to obtain the BIT (BITSTREAM) file that will be loaded into the FPGA (see Section III.A). It is noteworthy that it generally does not matter for students if the designed system is implemented in a FPGA, a CPLD or even a microcontroller. What matters to students is to see the system running, with its inputs (switches and buttons) and outputs (leds and sevensegment displays). During the uploading process, users will see a process bar as shown in Fig. 16. Fig. 18. BCD-ERROR system in the WebLab-Deusto Figs. 19 and 20 show the truth table of a BCD-seven segment decoder and the remote experience with it for the input 0011. Fig. 16. Synthesizing VHDL in WebLab-Deusto Fig. 19. BCD to seven segment decoder truth table

Fig. 23 shows the lit led after introducing four 1s in through the Switch 0. Fig. 20. BCD to seven segment decoder remote experimentation Using this approach any basic combinational circuit can be designed and experimented with through a remote lab in just a few minutes. B. Bit-level sequential circuits: Finite State Machine With a sequential circuit, users start the process with a FSM (see Fig. 8). Then they must save the FSM to VHDL code. They can choose among four clocks (see Fig. 21): Internal clock. The FPGA will be controlled by its internal clock of 50 MHz. WebLab clock. The FPGA will be controlled by a clock offered in the web page. Its frequency can be specified within a range that goes from 100 Hz to 10 KHz. Switch and Button clock. The FPGA will be controlled by a clock connected to a switch (switch 9) or to a button (Button 3). The first two options leave the system to run automatically, and the other two let the user control the speed of the system to witness its evolution in detail. The selection will depend on the particular needs of the student or teacher. Fig. 22. FPGA board through the experiment s webcam Other sequential systems can be designed and implemented in few minutes following the same order: FSM design, VHDL code generation, and WebLab-Deusto. C. Boole-Deusto and WebLab-Deusto Integration Fig. 23. Boole-Deusto and Weblab-Deusto integration Fig. 21. Clock options After saving the VHDL code, the user will repeat the process: Access to the WebLab-Deusto web page, upload the VHDL code, synthesize the VHDL, and finally load the bit file into the FPGA. After this, the user will interact with the system using the provided switches and buttons. The aim has been to integrate WebLab-Deusto and Boole- Deusto in a single, mostly seamless workflow. Certain challenges had to be overcome. Fig. 23 shows how it has been implemented and deployed. Back when Boole-Deusto was created, remote experimentation support was not an anticipated feature. Several additions to Boole-Deusto have been done. The most noteworthy is probably the capability to generate specialized VHDL code compatible with Weblab-Deusto. Weblab-compatible VHDL code has certain requirements, such as a fixed set of inputs and outputs which matches the physical setup of Weblab-Deusto FPGA boards.

This match is described in UCF files (which, for security reasons, are fixed and located on the Weblab server itself). As fig. 23 shows, once the VHDL code for a certain design has been generated, eventually the VHDL file reaches the Xilinx Synthesizing Tools within the WebLab-Deusto servers. Though WebLab-Deusto has long had the capability of experimenting with FPGA or CPLD boards remotely by providing a BIT file, this was not enough, due to several reasons. Firstly, obtaining a BIT file from VHDL is not a trivial process, especially for an inexperienced user. Specialized development software is required, and it has to be set up appropriately for the specific board that the remote experiment uses. And secondly, in order to obtain a BIT a UCF file is also required, linking the logical inputs and outputs to the physical ones. Apart from an inconvenience, allowing users to provide their own UCF files can be a security issue. Misuse can lead to physical damage to the experiment s hardware board. To prevent these issues the WebLab servers would have to be able to synthesize provided VHDL code themselves. This is done using the Xilinx Synthesizing command-line. The server also links it against the correct UCF file, which it chooses after finding (or not) certain specific preprocessor switches on the VHDL. If the process succeeds, a BIT file is obtained and programmed on the physical board. As depicted on fig. 23, once the physical board has been programmed by the Xilinx board-programming tools, remote experimentation may begin. The board, which will be running the designed system, is now displayed and can be controlled. V. CONCLUSIONS AND FUTURE WORK Through the use of Boole-WebLab-Deusto students can design a bit-level digital circuit and test it in a real board straightaway. Traditionally, this process often required hours, guidance, and access to a local laboratory with specialized equipment. Now only a few minutes and a standard Internet browser are required. Students do not need access to specialized hardware (FPGA boards) and they do not need specialized software (such as Xilinx ISE tools), as WebLab-Deusto provides both remotely. Previous remote-lab approaches [16] did handle the hardware requirements, but they still required the user to install the software tools on their machines and to configure and synthesize the digital circuit logic themselves. Doing this was far from trivial, as the tools were several gigabytes big, required registrations and administrator privileges to install, and were significantly hard to configure appropriately. Because Boole-WebLab-Deusto has made the process relatively simple, it does no longer need to be restricted to universities. We believe that it should be just as effective in secondary and high schools. Students can create and test their own designs easily, promoting creativity and autonomous work. This does not mean that it is less useful for more advanced users, because Boole-WebLab-Deusto does not make the circuit design process itself different. Simply, teachers and students can now focus on the circuit design and testing itself. They do not need to dedicate their limited time to auxiliary activities which were previously required, such as reserving and moving to a laboratory, setting up the hardware, the development environment, etc. They may still want to dedicate some time to them, but it can now be done only at their discretion. They are no longer forced to. Boole-WebLab-Deusto is now a reality, and the functionalities described here are already available [10][12]. It is expected that next year, several digital-electronics classes at the University of Deusto will start using it regularly. In the future, one of our goals is to gather usage data from real students, to analyze the results, and to improve the system based on the findings. Another goal is to include augmented reality in remote experiments, so as to improve the learning experience of the student by improving the quality, interest, and variety of experiments in a cost-effective way. This would be done by allowing the student to use a real FPGA to control a virtual model. REFERENCES [1] http://www.labcenter.com/index.cfm [2] http://www.interactiv.com/ [3] http://www.electronics-lab.com/ [4] http://k-map.sourceforge.net/ [5] Froyd, J.; Wankat, P.; Smith K., Five Major Shifts in 100 Years of Engineering Education Proceedings of the IEEE, Special Centenial Issue, VOL:100, pp:1344 1360, 2012. [6] Gomes, L.; Bogosyan, S. Current trends in remote laboratories, Trans. on Industrial Electronics, VOL. 56, Issue. 12, pp: 4744 4756, 2009. [7] Gomes, L.; Garcia-Zubia, J. (eds) Advances on Remote Laboratories and e-learning Experiences, Ed. University fo Deusto, 300 pp. 2007. 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