CILOMAG & SPIN Projects Spintronics Platform for Innovative Nanotechnology CMOS / Magnetic Integration Developments and results at CMP
Introduction : The MTJ structure
CMOS - MTJ Process CMOS process done at the foundry (stop at the top metal layer) CMOS
CMOS - MTJ Process CMOS process done at the foundry (stop at the top metal layer) Magnetic post-process + metallization + passivation + pad openings Magnetic CMOS
MTJ above-ic on CMOS process CILOMAG Consortium Silicon Foundries MTJ Postprocess 0.35µ STMicroelectronics 130nm
11 partners Spintronics Platform for Innovative Nanotechnology Démonstrateur 1 Filière Spin-valve Capteurs pour la la Santé et et l électronique de puissance Technologie BE >250nm Spintronics Platform for Innovative Nanotechnologies Conception / design ( Plateforme Saclay) Layout/ assemblage / gestion MPW FE CMOS BE magnétique ( Plateforme Grenoble) Packaging Démonstrateur 2 Filière JTM Système de calcul basse consommation Technologie BE 120nm
Spintronics Platform for Innovative Nanotechnology LIRMM SPEC LIST LETI-DCIS MENTA Design Sensor / Logic + ASIC design for Sensors SPINTEC IEF CMP CROCUS Magnetic Process Design Kit Digital PDK+ PDK for sensors LETI/DIHS LTM Ligne BE magnétique + Dépôt 200mm IBS AVIZA + Carac magnéto-transport CAPRES + Four de recuit 200mm + Gravure RIE pour Spintronique
CMOS-MTJ First Prototype Designer : LIRMM (Montpellier) Application : Non Volatile FPGA test structures prototype. CMOS process : Austriamicrosystems 0.35um CMOS CMP MPW run : A35C7-2 Magnetic Post-Process : INESC (Portugal) First CMOS / MTJ Prototype in a MPW run
CMOS-MTJ Second Prototype Designers : All CILOMAG partners Application : Different blocks architectures. CMOS process : Austriamicrosystems 0.35um CMOS CMP MPW run : A35C8-2 Magnetic Post-Process : LIMN / LETI (Grenoble) Embedded MTJ/CMOS sub-mpw run
CMOS-MTJ 3rd Prototype Designers : All SPIN partners Application : CMOS/Magnetic blocks and test structures. CMOS process : STMicroelectronics 130nm CMOS CMP MPW run : S13C09-4 Magnetic Post-Process : LIMN / LETI (Grenoble)
CMOS-MTJ 4th Prototype Designers : SPIN partners LIRMM Application : CMOS/Magnetic FPGA. (25mm 2 ) CMOS process : STMicroelectronics 130nm CMOS CMP MPW run : S13C10-3 Magnetic Post-Process : LIMN / LETI (Grenoble)
CMOS-MTJ 5th Prototype Designers : All SPIN partners Application : CMOS/Magnetic blocks and test structures. CMOS process : STMicroelectronics 130nm CMOS CMP MPW run : S13C10-3 Magnetic Post-Process : LIMN / LETI (Grenoble)
ANR / P2N DIPMEM Project Project just starting addressing : Hybrid Magnetic/CMOS design and manufacturing Resistive RAM like circuitry for non-volatile logics. ANR / P2N DIPMEM
Perspectives Complete Hybrid CMOS/Magnetic design-kits. DIPMEM project target 28nm CMOS. External users may interact with the consortium to have the access.