Engineer-to-Engineer Note

Engineer-to-Engineer Note EE-220 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our on-line resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port Contributed by Brin M., Divy S. nd Mtt W. Rev 2 Mrch 8, 2005 Introduction The ddressing functionlity of the Prllel Port on the third genertion SHARC fmily of processors hs chnged gretly when compred to the other SHARC fmily DSPs tht hve n Externl Port. This EE-Note describes externl memory ddressing nd how to use the VisulDSP++ development tools to hndle ddress trnsltion nd dt reorgniztion vi the LDF PACKING commnd. A mcro tht helps the Symbol Mnger convert logicl nd physicl ddresses is lso explined. This EE-Note pplies to the following processors: ADSP-21261 ADSP-21363 ADSP-21262 ADSP-21364 ADSP-21266 ADSP-21365 ADSP-21267 ADSP-21366 ADSP-21362 Externl Memory Addressing One significnt difference between the Prllel Port nd the previous Externl Port is tht the Prllel Port no longer ccepts logicl ddresses from the core, insted requiring the physicl word ddress to be supplied to the DMA engine. This chnge requires specil considertions by softwre developers wishing to use externl memory with Prllel Port. Previous SHARC DSPs hve lwys ccessed the externl memory using logicl (32-bit) ddressing (i.e., ech externl ddress in the memory mp corresponds to exctly one complete word of dt). The trnsltion of ech logicl ddress into the four corresponding physicl ddresses is hndled trnsprently by the hrdwre of the port. For exmple, if 32-bit word is fetched from n externl byte-wide device, the core only needs to specify the single 32-bit logicl ddress; then, the Externl Port utomticlly clcultes the four physicl ddresses nd performs the four fetches needed to cquire the entire 32-bit word. In contrst, the Prllel Port does not hve the ddress trnsltion built-in, lthough it will still perform the dt pcking (e.g., building 32-bit word from four 8-bit words). The Prllel Port opertes on physicl ddresses only. Note tht ech externl ddress in the memory mp does not correspond to complete word of dt. Insted, ech logicl (32-bit) word of dt consumes multiple ddresses in the externl rnge of the memory mp. To illustrte this fct, compre the hndling of two consecutive 32-bit fetches on ADSP-21161 SHARC processor versus the sme trnsction on n ADSP-21262 SHARC processor. Tble 1 shows the corresponding physicl ddresses generted by the Externl Port bsed on the logicl ddresses from which dt is fetched. (Agin, this ssumes 32/8 bit pcking). Note tht Copyright 2005, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

consecutive logicl ddresses correspond to seprte words externlly. Logicl Address Physicl (Byte) Address Dt 0x200000 0x200000 Word0 Byte1 0x200001 0x200002 0x200003 Word0 Byte2 Word0 Byte3 Word0 Byte4 0x200001 0x200004 Word1 Byte1 0x200005 0x200006 0x200007... Word1 Byte2 Word1 Byte3 Word1 Byte4 0x200100 0x200400 Word256 Byte1 0x200401... Word256 Byte2 Tble 1. ADSP-21161 logicl-to-physicl Address Trnsltion by the Externl Port. Tble 2 highlights the difference in opertion on the Prllel Port nd illustrtes the lck of ddress trnsltion between the logicl (32-bit) ddress nd the physicl (8-bit in this cse) ddress. Logicl Address Physicl (Byte) Address Dt 0x200000 0x200000 Word0 Byte1 0x200001 0x200002 0x200003 Word0 Byte2 Word0 Byte3 Word0 Byte4 0x200001 0x200001 Word0 Byte2 0x200002 0x200003 0x200004... Word0 Byte3 Word0 Byte4 Word1 Byte1 0x200100 0x200100 Word32 Byte1 0x200101... Word32 Byte2 Tble 2. ADSP-21262/ADSP-21364 Logicl to Physicl ddress mpping (not comptible with previous SHARC ddressing schemes). Fetching from consecutive logicl ddresses does not properly ccess unique dt in externl memory. The rest of this EE-Note describes how to del with this new functionlity in softwre. The second chnge from previous SHARC DSPs is tht it is necessry to lwys use the Externl Index register (EIPP) to ccess externl memory; there is no direct core ccess to externl memory vi the Dt Address Genertors. The ddress in the EIPP register is supplied directly to the AD pins in the ddress cycle. (This buffered-ccess rchitecture effectively decouples the core from the Prllel Port, enbling the core clock speed to be doubled. It lso uses fewer pins, significntly reducing both DSP nd system cost.) Orgnizing Dt for plcement in Externl Memory using the LDF The first problem tht the new Prllel Port introduces is tht it uses physicl word ddress, rther thn logicl word ddress. Becuse of this, it is necessry to perform ddress trnsltion nd dt reorgniztion in softwre. In VisulDSP++, the LDF must include the PACKING() commnd, enbling the linker to generte ddresses tht the Prllel Port cn use. Listings 1 nd 2 provide exmple pcking commnds for vriety of possible cses when pcking into 8-bit memory nd 16-bit memory, respectively. The only cse where PACKING() commnd would not be required is when initilizing 16-bit externl memory with 16-bit dt. In this one cse, it so hppens tht the logicl ddresses directly mtch the physicl ddresses, so no trnsltion/pcking is needed. The PACKING() commnd directs the linker to reformt the dt s it is plced into the DXE. For memory section of TYPE(DM RAM), ech memory ddress holds five bytes in the DXE (regrdless of whether the dt is 40-, 32-, or 16- bit logicl dt). For TYPE(PM RAM) section, ech ddress corresponds to six bytes (regrdless of whether the dt is 48-, 40-, 32-, or 16-bit logicl dt). Before ech word of dt is ssigned n ddress by the linker, the PACKING() commnd reorgnizes the order of the bytes in Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 2 of 11

the DXE, nd cn dd null bytes to the DXE, if needed. The loder nd debugging tools (simultor nd emultor) expect the externl memory sections DXE to be in certin formt to initilize externl memory correctly. For exmple, when DM (5-byte) word is mpped into n ddress in memory segment tht is WIDTH(8), only the dt in the fourth most significnt byte is plced t tht externl ddress. Similrly, for DM (5-byte) words mpped to memory segment tht is WIDTH(16), only the dt in the third nd fourth most significnt bytes re plced into the externl ddress. (See Listings 1 nd 2 for exmples.) This mens tht if 32-bit dt is mpped into externl 8-bit memory, 3 bytes of dt re uninitilized. To remedy this, trnslte the 32-bit word into four words, plcing the vlid dt into the 4 th most significnt byte of ech new word, s shown in Tble 3. (Refer to the Prllel Port chpter of ADSP-2126x SHARC DSP Peripherls Mnul [1] for informtion bout how dt is pcked in externl memory.) The DSP s internl memory is orgnized s four 16-bit-wide by 64K-deep columns which re ddressble s vriety of word sizes: 64-bit long word dt (four columns) 48-bit instruction words or 40-bit extendedprecision norml word dt (3 columns) 32-bit norml word dt (2 columns) 16-bit short word dt (1 column) The four-columned memory rchitecture of the third genertion SHARC fmily llows ech loction in internl memory to be ccessed in ny of the bove formts, depending on the ddress used. However, every ccess to the Prllel Port is 32-bits (ccesses re to 32-bit norml word spce, nd counted in number of 32-bit words). Externl Width Corresponding Address DM Pcked for Externl Memory PM Pcked for Externl Memory 32-bit Word Trnsferred by the Processor WIDTH(8) 0x01000000 0x0000001100 0x000000110000 0x44332211 0x01000001 0x0000002200 0x000000220000 0x01000002 0x0000003300 0x000000330000 0x01000003 0x0000004400 0x000000440000 WIDTH(16) 0x02000000 0x0000112200 0x000011220000 0x33441122 0x02000001 0x0000334400 0x000033440000 Tble 3. Pcking in the DXE file for externl memory. When trnsferring words tht re not 32-bits long, the Externl Count register must contin whole number of 32-bit words (i.e. it must be multiple of four). If it is not, the reminder bytes re not trnsferred s expected. It is lso necessry to trnslte the internl ddress to 32- bit word spce. Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 3 of 11

48-bit Address Trnsltion The following exmple trnsltes the 48-bit ddress 0x82694 to its 32-bit equivlent. Trnslting from 16- or 64-bit spce to 32-bit spce is s simple s shifting the entire ddress by one bit (left-shift for 16-bit ddresses, nd right-shift for 64-bit ddresses). For 40/48-bit ddresses, which lso use the norml word spce ddresses, 48-bit ddresses re offset from the bse ddress (0x80000 or 0xC0000) by twothirds of the offset of the 32-bit word. Word spce msk = 0x80000 or 0xC0000 (0x80000 in this cse) First remove the word spce msk. 48-bit Offset = 0x82694-0x80000 = 0x2694 Then multiply the offset by 3/2. 32-bit Offset = 0x2694 * 3/2 = 0x39DE Finlly, reinsert the word spce msk. 32-bit equivlent ddress = 0x839DE When trnslting from 48-bit to 32-bit ddress, only even 48-bit ddress trnsltions re vlid. Odd 48-bit ddresses fll in the middle of 32- bit word, nd cnnot be ccessed properly. See the ADSP-2126x or ADSP-2136x Core Mnul for more informtion. Opertion of the Prllel Port DMA Count (ECPP, ICPP) Registers The Prllel Port trnsfers dt between internl nd externl memory using the DMA controller. As ech trnsfer occurs, the DMA controller first decrements the count register vlues (ECPP nd ICPP), performs the requested trnsfer, then checks the left over count. The trnsfers continue to tke plce until the count registers decrement to zero (ECPP ICPP=0). At this point, the Prllel Port will stop trnsferring dt, but both the Prllel Port nd its DMA will remin enbled until explicitly disbled by the user. Due to the bove mentioned sequence of events by the DMA controller, problem rises when enbling DMA with count registers set to zero. With the count registers vlue set to zero, enbling DMA decrements ICPP to 0xFFFF nd ECPP to 0xFFFF nd check is mde on these vlues which llows 64 K 32-bit trnsfers. Therefore, it is undvisble to enble DMA with ECPP or ICPP=0; This behvior does not pply to core-driven ccesses, since the count register is ignored by the Prllel Port. (Core driven ccesses re hrdwired to operte single 32-bit word trnsfers, regrdless of the vlue of the count register. Multiple trnsfers in core driven mode re bsed on loops rther thn the vlue of count register. ) Using the Emultor to View the Contents of Externl Memory VisulDSP++ includes support for viewing the contents of externl memory. By chnging the ddress to the loction of your externl memory, the Externl Byte Memory window cn be used for 8-bit externl memory, nd the Short Word Memory window for 16-bit externl memory is used. (In the Short word memory window ech ddress represents 16-bit dt word wheres in Externl Byte Memory ech ddress vlue points to n 8-bit dt word.) Figure 1. Exmple Externl Byte Memory Window t n Externl Address. Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 4 of 11

Figure 1 shows n exmple of the Externl Byte memory window displying n externl ddress, nd Figure 2 shows the sme for Short Word memory window. Figure 2. Exmple Short Word Memory Window t n Externl Address. Since there is no direct core ccess to the externl memory, the emultor must the Prllel Port to disply the contents of externl memory. This my hve n impct on settings from softwre tht exist when the window is opened or updted. To populte the memory windows, the emultor uses the Prllel Port in core driven mode. For core driven ccess the externl DMA prmeter registers (EIPP, ECPP, EMPP) of the prllel port provide n interfce to externl memory. Therefore, populting the vlues in memory window consists of three steps: 1. The emultor stores the current stte of prllel port prmeter (EIPP, ECPP, EMPP) nd control (PPCTL) registers tht will be chnged during the popultion process. 2. The emultor enbles the prllel port in core driven mode for receiving dt nd reds enough dt to populte the entire window. 3. The prllel port is disbled gin nd then the stored vlues of the prllel port prmeter nd then control registers re restored. Since the emultor uses the prllel port to disply the externl memory vlues, it is dvisble to view externl ddress vlues in memory window only fter the prllel port ccesses re completely executed nd the Prllel Port hs been disbled. Even though the count is zero, if the PPDEN nd PPEN bits in PPCTL re set, there is possibility of dt corruption fter the emultor reds the contents of the memory s described in the Opertion of the Prllel Port DMA Count Registers. When the Emultor restores the vlues of the ECPP nd PPCTL registers under these conditions (ECPP=0 nd PPDEN nd PPEN re set), the Prllel Port will begin n undesired DMA opertion which will overwrite vlues in either internl or externl memory depending upon the vlue of the PPTRAN bit. The only wy to void possible dt corruption is to ensure tht PPDEN is not set before you view the contents of externl memory in window in VisulDSP++. Strting from VisulDSP++ 4.0, we hve dded check for this condition to void the corruption of vlues in the externl memory. To void this issue, the emultor will utomticlly disble the PPDEN bit nd provide wrning tht the setting of the PPCTL register hs been chnged. Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 5 of 11

8-bit Externl Memory Exmples MEMORY seg_ext8 TYPE(DM RAM) WIDTH(8) START(0x1200000) LENGTH(0x3FFF) seg_extpm8 TYPE(PM RAM) WIDTH(8) START(0x1204000) LENGTH(0x3FFF) PROCESSOR p0 LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) SECTIONS seg_ext40into8 INPUT_SECTIONS( $OBJECTS(seg_ext40into8)) PACKING(5 B0 B0 B0 B5 B0 B0 B0 B0 B4 B0 B0 B0 B0 B3 B0 B0 B0 B0 B2 B0 B0 B0 B0 B1 B0) > seg_ext8 seg_ext32into8 INPUT_SECTIONS( $OBJECTS(seg_ext32into8)) PACKING(5 B0 B0 B0 B4 B0 B0 B0 B0 B3 B0 B0 B0 B0 B2 B0 B0 B0 B0 B1 B0) > seg_ext8 seg_ext16into8 INPUT_SECTIONS( $OBJECTS(seg_ext16into8)) PACKING(5 B0 B0 B0 B2 B0 B0 B0 B0 B1 B0) > seg_ext8 seg_extpm8 INPUT_SECTIONS( $OBJECTS(seg_extpm8)) PACKING (6 B0 B0 B0 B6 B0 B0 B0 B0 B0 B5 B0 B0 B0 B0 B0 B4 B0 B0 B0 B0 B0 B3 B0 B0 B0 B0 B0 B2 B0 B0 B0 B0 B0 B1 B0 B0) > seg_extpm8 Listing 1. Pcking Exmples for 8-bit Externl Memory Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 6 of 11

16-bit Externl Memory Exmples MEMORY seg_ext16 TYPE(DM RAM) WIDTH(16) START(0x1000000) LENGTH(0x3FFF) seg_extpm16 TYPE(PM RAM) WIDTH(16) START(0x1004000) LENGTH(0x3FFF) PROCESSOR p0 LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) SECTIONS seg_ext40into16 INPUT_SECTIONS( $OBJECTS(seg_ext40into16)) PACKING(5 B0 B0 B5 B0 B0 B0 B0 B3 B4 B0 B0 B0 B1 B2 B0) > seg_ext16 seg_ext32into16 INPUT_SECTIONS( $OBJECTS(seg_ext32into16)) PACKING(5 B0 B0 B3 B4 B0 B0 B0 B1 B2 B0) > seg_ext16 seg_ext16into16 INPUT_SECTIONS( $OBJECTS(seg_ext16into16)) > seg_ext16 seg_extpm16 INPUT_SECTIONS( $OBJECTS(seg_extpm16)) PACKING (6 B0 B0 B0 B5 B6 B0 B0 B0 B0 B3 B4 B0 B0 B0 B0 B1 B2 B0) > seg_extpm8 Listing 2. Pcking Exmples for 16-bit Externl Memory Symbols in Externl Memory The Symbol Mnger in VisulDSP++ supports the use of logicl ddresses only. Therefore, ny symbol tht resides in externl memory, except for the first in declred memory section, will be incorrect by vlue dependent upon the width of the externl memory nd the ddress decoder setup. As explined bove, the Prllel Port uses physicl ddresses. The difference between the logicl nd physicl ddress depends on memory type used (PM or DM), the width of the externl memory (8- or 16-bits), nd the pcking. Since this difference is predictble, it is possible to use preprocessor mcro to obtin the correct ddress. (Declring seprte memory section in the LDF for ech externl buffer would lso void this problem, since ech buffer would be Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 7 of 11

the first in its declred memory section. Becuse this method requires pre-build knowledge of the desired externl buffers nd hrd coding the sizes into the LDF, it my be undesirble.) The pcking commnds in Listings 1 nd 2 clerly shows the reltionship between the logicl nd physicl ddress. Ech pcking commnd represents one logicl word, nd ech line within the pcking commnd represents one physicl ddress. In the exmples in Listings 3 nd 4, one 32-bit logicl word is pcked into four 8-bit physicl words. If two contiguous symbols re declred, the second symbol will overlp with the first by 3 bytes (e.g., if the first resides physiclly t 0x1002000 nd the second t 0x1002004, the logicl ddresses stored by the Symbol Mnger will be 0x1002000 nd 0x1002001, respectively). If these symbols re used s presented by the Symbol Mnger, ccess to the second word would begin t the second byte of the first word nd end with the first byte of the second word. If third 32-bit word is lso declred, ccess to this word would begin t the third byte of the first word nd end with the second byte of the second word. Therefore, simple mcro is necessry to correct the inccurcy of the Symbol Mnger (see the EXTERNAL_ADDRESS() mcro in Listing 3). Address Trnsltion Mcro Use Exmple //Width of Externl Memory to be ccessed (either 8 or 16 bits) #define EXTERNAL_MEMORY_WIDTH 8 //Msk for ddress bits used by the ddress decoder #define DECODER_MASK 0xFFFFFC00 //Msk for ddress bits used on the memory chip #define ADDRESS_MASK 0x000003FF //Define mcro to perform the clcultion #define EXTERNAL_ADDRESS(ADDR) ((ADDR & DECODER_MASK) \ ((ADDR & ADDRESS_MASK)*(32 / EXTERNAL_MEMORY_WIDTH))) #include <def21262.h>.section/dm seg_dm32;.vr ext8holder[5]; // ****************************************************************** // Externl.section/dm seg_ext8;.vr ext8zeros[95];.vr ext8[5] = 0xE0811111, 0xE0822222, 0xE0833333, 0xE0844444, 0xE0855555; // ******************************************************************.globl _min; //Min code section.section/pm seg_pmco; _min: //Enble the Prllel Port interrupt. bit set lirptl PPIMSK; bit set mode1 IRPTEN; Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 8 of 11

//Red in the Externl DM sections on vrible t time r4=0; dm(ppctl)=r4; r0=ext8holder; dm(iipp)=r0; r0=1; dm(impp)=r0; dm(empp)=r0; r0=@ext8holder; dm(icpp)=r0; /*Clculte the correct loction of the externl buffer (The symbol mnger does not correctly clculte externl loctions) r0=(ext8&0xfffffc00) ((0x3FF&ext8)*4); dm(eipp)=r0; So use the Externl Address Mcro. */ r0=external_address(ext8); dm(eipp)=r0; //Externl Count is 4x the internl count r0=@ext8*4; dm(ecpp)=r0; //Enble the Prllel Port ustt1= PPBHC PPDUR4 PPEN PPDEN; dm(ppctl)=ustt1; nop; idle; r0=0; dm(ppctl)=r0; r0=ext8zerosholder; dm(iipp)=r0; r0=1; dm(impp)=r0; dm(empp)=r0; r0=@ext8zerosholder; dm(icpp)=r0; /*Use the externl ddress mcro gin.*/ r0=external_address(ext8zeros); dm(eipp)=r0; //Externl Count is 4x the internl count r0=@ext8zeros*4; dm(ecpp)=r0; //Enble the Prllel Port ustt1= PPBHC PPDUR4 PPEN PPDEN; dm(ppctl)=ustt1; nop; idle; _min.end: jump(pc,0); Listing 3. Using the Address Trnsltion Mcro Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 9 of 11

Memory Lyout for Listing 3 MEMORY seg_rth TYPE(PM RAM) START(0x00080000) END(0x000800ff) WIDTH(48) seg_pmco TYPE(PM RAM) START(0x00080100) END(0x000803ff) WIDTH(48) seg_dm32 TYPE(DM RAM) START(0x000c0400) END(0x000c2fff) WIDTH(32) seg_ext8 TYPE(DM RAM) WIDTH(8) START(0x1200000) LENGTH(0x3FF) PROCESSOR p0 LINK_AGAINST( $COMMAND_LINE_LINK_AGAINST) OUTPUT( $COMMAND_LINE_OUTPUT_FILE ) SECTIONS seg_rth INPUT_SECTIONS( $OBJECTS(seg_rth)) >seg_rth seg_pmco INPUT_SECTIONS( $OBJECTS(seg_pmco)) >seg_pmco seg_dm32 INPUT_SECTIONS( $OBJECTS(seg_dm32)) > seg_dm32 seg_ext8 INPUT_SECTIONS( $OBJECTS(seg_ext8)) PACKING(5 B0 B0 B0 B4 B0 B0 B0 B0 B3 B0 B0 B0 B0 B2 B0 B0 B0 B0 B1 B0) > seg_ext8 Listing 4. LDF Memory Section for Exmple in Listing 3 Listing 3 shows the EXTERNAL_ADDRESS() mcro s it pplies to the ADSP-21262 EZ-KIT Lite development bord. It is not sufficient to simply multiply the vlue of the symbol by the rtio of logicl to physicl words. Msk off the rnge tht is used by the ddress decoder before the clcultion, nd OR it bck in fter the lower bits hve been trnsformed. For this exmple, the ddress decoder rnge consists of the upper 3 ddress bits tht re physiclly connected to the ddress decoder on the ADSP-21262 EZ-KIT Lite nd the ddress rnge tht memory sections defined in the LDF hve in common. The vlues of the msks in the EXTERNAL_ADDRESS() mcro chnge, depending upon the specific memory lyout in use. Using the EXTERNAL_ADDRESS() Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge10 of 11

mcro does not ffect the performnce of the DSP, s the clcultions re performed t buildtime by the preprocessor. Conclusion When using the Prllel Port of the third genertion SHARC fmily, specil considertions must be mde regrding externl ddresses. The mcro provided in this document llows the symbols provided in VisulDSP++ to be useful when developing code tht uses externl memory. Plese review the VisulDSP++ documenttion for more informtion on the linker, PACKING commnd, nd the preprocessor. See ADSP-2126x SHARC DSP Peripherls Mnul [1] for more informtion on using the Prllel Port. References [1] ADSP-2126x SHARC DSP Peripherls Mnul. Revision 2.0, Jnury 2004. Anlog Devices, Inc. [2] VisulDSP++ 3.0 Linker nd Utilities Mnul for SHARC DSPs. Fourth Revision, Jnury 2003. Anlog Devices, Inc. Document History Version Rev 2 Mrch 8, 2005 by Brin M. nd Divy S. Rev 1 Jnury 12, 2004 by Brin M. Description Added relevnt ADSP-2136x processors to discussion. Added Externl Memory Window section. Initil Relese Using Externl Memory with Third Genertion SHARC Processors nd the Prllel Port (EE-220) Pge 11 of 11