Engineer-to-Engineer Note

Transcription

1 Engineer-to-Engineer Note EE-178 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t dsp.support@nlog.com nd t dsptools.support@nlog.com Or visit our on-line resources nd The ADSP-TS101S TigerSHARC On-chip SDRAM Controller Contributed by Mikel Kokly-Bnnourh & Robert Hoffmnn Rev 2 December 19, Introduction In systems where Digitl Signl Processor (DSP) is used to ddress Synchronous Dynmic Rndom Access Memory (SDRAM), dditionl hrdwre nd softwre is needed to hndle the multiplexed row nd column ddressing, s well s the refresh nd prechrge requirements of the SDRAM. The ADSP- TS101S TigerSHARC processor uses hrdwre intensive solution, n on-chip SDRAM controller. This Engineer-to-Engineer Note introduces the ADSP-TS101S on-chip SDRAM controller s chrcteristics. The internl signl chin is shown with the necessry ddress-mpping scheme. The commnd truth tble gives detiled informtion bout execution in the SDRAM. The importnt power-up sequence summrizes detil informtion to strt successful designs. A timing overview demonstrtes the performnce for different ccess modes. For bsic understnding of SDRAM memories, refer to The ABC of SDRAMemory (EE-126) [3]. Copyright 2003, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices Applictions nd Development Tools Engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 2 Tble of Contents 1 Introduction Tble of Contents Signl Chin of SDRAM On-Chip Controller Architecture Controller Commnd Interfce TigerSHARC Output FIFO Controller Address Multiplexer Controller Dt Dely Buffer SDRAM Types Commnd Coding Controller s Pin Definition Controller Commnd Truth Tble Setup nd Hold Times Simplified Stte Digrm SDRAM Controller Properties Address Mpping Scheme TigerSHARC SDRAM Bnk Select (~MSSD) Burst Stop (BST) Dt Msk Function ([H:L]DQM) SDRAM Bnk Select Controller Address 10 (SDA10) Burst Mode Prechrge All (PREA) Circulr Access Auto-Refresh (REF) Self-Refresh (SREF) Mode Register Set (MRS) SDRAM Progrmming SYSCON Register SDRCON Register SDRAM Mode of Opertion ADSP-TS101S EZ-KIT Lite SDRAM Setting Overview Power-up Sequence Hrdwre Initiliztion Softwre Initiliztion SDRAM Initiliztion Exmple SDRAM Interfce After Reset DMA Trnsfers Internl Memory nd SDRAM Externl Device nd SDRAM (FLY-BY) SDRAM Interfce in Host Mode...22 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 2 of 44

3 11 Multiprocessing Commnd Decoding MRS Decoding REF Decoding SREF Decoding Bus Trnsition Cycle SDRAM nd Booting Loder Kernel Booting Modes SDRAM Interfce Throughput Sequentil Reds without Interruption Non Sequentil Reds without Interruption Sequentil Reds with minimum Interruption Sequentil Writes without Interruption Non Sequentil Writes without Interruption Sequentil Writes with minimum Interruption Reds between Pge/Bnk Writes between Pge/Bnk Minimum Red to Write Intervl Minimum Write to Red Intervl Chined DMA Trnsfers Auto-Refresh Self-Refresh nd Host Accesses SDRAM Performnce Tble Optimizing SDRAM Performnce Externl Buffering Using PC Modules Generl Rules for Optimized Performnce References Document History...44 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 3 of 44

4 3 Signl Chin of SDRAM The signl chin between the ADSP-TS101S, the on-chip SDRAM controller, nd the externl memory device is illustrted in Figure 1 for 64-bit bus configurtion: ADSP-TS101S Core DMA SCLK int. RD int. WR int. Reset int. ACK busy ~MSSD Commnd Logic SDCKE ~RAS ~CAS ~SDWE [H:L]DQM SDA10 ~MSSD SCLK CLK CKE ~RAS ~CAS ~WE DQM A10 ~CS SDRAM Externl Port Buffers A25:0 Pipe depth Address Multiplexer A14 A13 A1:10, A12 Dt buffer BA0 BA1 A0:9, A12, DQ31:0 A31:0 D63:0 (non SDRAM) Figure 1. ADSP-TS101 to SDRAM Signl Chin (64-bit bus configurtion) The 3 prts for the signl flow to be considered re: ADSP-TS101S (core, DMA engine, I/O-Processor nd the ddress buffer The SDRAM Controller (control interfce, dely buffer, nd ddress multiplexer). SDRAM device. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 4 of 44

5 4 On-Chip Controller Architecture The synchronous interfce between the ADSP-TS101S nd the on-chip controller cn be described in 4 bsic prts: 4.1 Controller Commnd Interfce Becuse of the 2 different timing protocols, the internl TigerSHARC commnds re converted to comply with the JEDEC stndrd for SDRAMs. The externl clock, 100 MHz mximum, is used for synchronous opertion. The TigerSHARC s internl request lines or strobes re used to ccess the SDRAM with pulsed commnds. The controller s internl ACK line inserts vrible wit sttes to the DSP during overhed cycles, cused by DRAM technology. 4.2 TigerSHARC Output FIFO The TigerSHARC s output FIFO is ctive for externl port ddresses like SDRAM. With the FIFO depth 6, ddress pipelining for high-speed non-sequentil red opertions (CAS ltency=3) is supported without performnce losses. 4.3 Controller Address Multiplexer Every first red or write ction is issued in multiplexed mode. A mximum of 8192 rows (64-bit bus configurtion) nd rows (32-bit bus configurtion) within 1024 columns cn be ddressed. 4.4 Controller Dt Dely Buffer If systems incorporte hevy buslod, n dditionl dt buffers is used to decouple the input from the cpcitive lod. This dely buffer in conjunction with n externl buffer for SDRAM control nd ddress lines reduces dditionl logic to minimum. 4.5 SDRAM Types The ADSP-TS101S on-chip SDRAM controller interfce supports vrious LVTTL SDRAM devices depending on size nd internl orgniztion (I/O cpbility, number of rows, nd pge size). The following tble summrizes ll the supported types: Size I/O cpbility Row x Pge Size I/O cpbility Row x Pge 1M x 16 2k x 256 8M x 32 8k x Mbits 2M x 8 2k x Mbits 16M x 16 8k x 512 4M x 4 2k x M x 8 8k x M x 32 2k x 256 8M x 32 8k x 256 4M x 16 4k x Mbits 64 Mbits 16M x 16 8k x 512 8M x 8 4k x M x 8 8k x M x 4 4k x M x 32 4k x Mbits 8M x 16 4k x M x 8 4k x 1024 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 5 of 44

6 5 Commnd Coding 5.1 Controller s Pin Definition Pin Type Description ~MSSD I/O/T (pu) Memory select signl ~RAS I/O/T (pu) Row select signl ~CAS I/O/T (pu) Column select signl ~SDWE I/O/T (pu) Write enble signl HDQM O/T (pu) Msk dt high lne signl LDQM O/T (pu) Msk dt low lne signl SDA10 O/T (pu) Address10 /commnd select signl SDCKE I/O/T (pu/pd) Clock enble signl A[1:10,:12-15] I/O/T ddresses for 64-bit A[0:9,11-15] I/O/T ddresses for 32-bit A[11:15] I/O/T Bnk select signl D[63:0] I/O/T Dt signls I = input, O = output, T = Hi-Z, pd = pull-down, pu = pull-up 5.2 Controller Commnd Truth Tble This section provides tble to get n overview of ll commnds provided by the SDRAM controller. These commnds re utomticlly hndled by the interfce. SDCKE = high CMD SDCKE(n-1) SDCKE(n) ~MSSD ~RAS ~CAS ~SDWE SDA10 ADDR MRS V V ACT V V RD V WR V SDCKE = high, no vlidity of ddress CMD SDCKE(n-1) SDCKE(n) ~MSSD ~RAS ~CAS ~SDWE SDA10 ADDR NOP x x x x x BST x x REF x PREA x Commnds with SDCKE trnsition CMD SDCKE(n-1) SDCKE(n) ~MSSD ~RAS ~CAS ~SDWE SDA10 ADDR SREF E x x SREF M 0 0 x x x X x x SREF X x x x x x X = don t cre, v = vlid dt input, 0 = logic 0, 1 = logic 1, E = entry, M = mintin, X = exit Although the SDCKE line toggles in n synchronous mnner, the commnds re smpled synchronous to the CLK signl. Note tht Power-down nd Suspend modes re not supported, nd tht the controller does not llow uto prechrge. Lstly, keep in mind tht ll SDRAM commnds re fully trnsprent to the user. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 6 of 44

7 5.3 Setup nd Hold Times The synchronous opertion uses the externl clock s reference. Commnds, ddresses, nd dt re ltched t the rising edge of clock. The vlid time mrgin round the rising edge is defined s setup time (time before rising edge) nd hold time (time fter rising edge) to gurntee tht both the controller nd the SDRAM re working relibly together. Signl s slew rtes, propgtion delys (PCB), nd cpcitive lods (devices) influence these prmeters nd should be tken into considertion. The SDRAM interfce AC Signl Specifictions cn be found in the ADSP-TS101S Dt Sheet [2]. 5.4 Simplified Stte Digrm The following stte digrm (Figure 2) shows ll possible SDRAM commnds sequences to help nlyze the controller s functionlity. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 7 of 44

8 Mode Register MRS tmrd=2 Idle Stte SREF Exit txsr=2+trc Self Refresh (Host) ACT REF Core DMA MMS Host BST Row ctivte BST Refresh Counter expired Auto Refresh only one bnk t the time cn be ctive trcd=cl RD trcd 1-3 WR trcd 1-3 BST BST CL 1-3 Red burst Write burst SDRAM burst: full pge ( words) PREA Controller burst: Qud-word (128-bits) 32-bit => 4 words 64-bit => 2 words set bit "SDRAM enble" Trigger MRS Sequence Prechrge ll tras 2-8 Automtic sequence Controller input trp 2-5 Figure 2 ADSP-TS101S SDRAM Controller Simplified Stte Digrm The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 8 of 44

9 6 SDRAM Controller Properties Following, the ADSP-TS101S on-chip SDRAM controller properties re exmined: 6.1 Address Mpping Scheme There re vrious possibilities when ccessing the SDRAM. For instnce, ll rows in bnk cn be ccessed sequentilly, or ll bnks in row. PC DIMM modules re ccessed in different mnner compred to typicl DSP ppliction. The ADSP-TS101S controller uses hrdwre mp scheme optimized for digitl signl processing. The ddress mpping scheme is decoded from the pge size nd the bus width (both configurble by softwre in the SDRCON nd SYSCON registers respectively; refer to section 7 SDRAM Progrmming). For more informtion regrding the ddress mpping scheme, refer to the SDRAM chpter of the ADSP- TS101 TigerSHARC Processor Hrdwre Reference [1]. Figure 3 reproduces n exmple of the controller s ddress mpping for 64-bit dt. In bnk A, the SDRAM s columns re sequentilly ccessed until the end of the row. Similrly, the SDRAM s rows re sequentilly selected until the bnk s end. Exmple: Address Multiplexing of 128MBits SDRAM (4k x 512 x 4 Bnks x 16bit) (64-bit bus configurtion) Bnk Row Column 31 ~MSSD Row Input: Controller ddress 1. Output: Row ddress ~CS Column Output: Column ddress Figure 3 ADSP-TS101S SDRAM Controller Mpping Scheme Exmple Note tht only one bnk t time cn be ctive, which results in some overhed cycles when switching between bnks (off-bnk ccesses). Similrly, moving from one row to nother (off-pge ccess) results in the sme overhed cycles. Figure 4 shows how the ADSP-TS101S TigerSHARC on-chip SDRAM controller ccesses SDRAM. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 9 of 44

10 4M x 4bit x 4 Bnks, 4096 Rows, Pge size 1024 words Column 0 On Pge Access Column 1023 Row 0 Row 1 Off Pge Access Row 4095 Off Bnk Access Bnk A Bnk B Bnk C Bnk D Figure 4 ADSP-TS101S SDRAM Controller Access Structure 6.2 TigerSHARC SDRAM Bnk Select (~MSSD) The fixed dedicted bnk ~MSSD (A[31:26]=0x0b000001) must be used for SDRAM ccesses only. In this memory region, the controller s ddress multiplexer will be ctive. 6.3 Burst Stop (BST) Although the controller works in burst mode, there is one wy to interrupt the burst with the burst stop commnd. BST is issued if the next instruction is: Non externl SDRAM ccess (ccess to nother TigerSHARC bnk) Core ccess (depending on the number of ccesses, dely nd externl port FIFOs stte) DMA opertion (externl port DMA to SDRAM interrupted by higher priority DMA) Refresh counter expired (refresh period counter) SDRAM red to write nd write to red trnsitions SDRAM off pge/bnk ccess ~HBR sserted (host interfce) The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 10 of 44

11 During Bus Trnsition Cycle (multiprocessing) 6.4 Dt Msk Function ([H:L]DQM) The [H:L]DQM pins re used by the controller to msk write opertions. HDQM msks the SDRAM DQ buffers when performing 32-bit writes to even ddresses in 64-bit bus configurtion. LDQM msks the SDRAM DQ buffers when performing writes to odd ddresses in 64-bit bus configurtion. This dt msk function does not pply for red opertions, where the LDQM nd HDQM pins re lwys low (inctive). This is summrized in the following tble: Bus Width* 64-bit 32-bit Access type 32-bit Even 32-bit Odd 64-bit 32-bit Even/Odd HDQM x LDQM x = don t cre 0 = logic 0, 1 = logic 1 *Bus Width bit setting in SYSCON 6.5 SDRAM Bnk Select The next tbles show the ddress lines selection for the different bnks: 2-bnked ccess Bnks A[11:15] SDA10 Bnk_A 0 0 Bnk_B 1 0 Bnks A/B x 1 x = don t cre, 0 = logic 0, 1 = logic 1 Note: Any ddress line from ddress rnge A[11:15] cn be used for bnk select s long s they re not driven s row or column ddress. 4-bnked ccess Bnks A[11,13,15] A[12,14] SDA10 Bnk_A Bnk_B Bnk_C Bnk_D All Bnks X X 1 x = don t cre, 0 = logic 0, 1 = logic 1 Note: Any ddress line pir from ddress rnge A[11:15] cn be used for bnk select s long s they re not driven s row- or column ddress. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 11 of 44

12 6.6 Controller Address 10 (SDA10) This pin provides specil solution to gin control of the SDRAM, even when the DSP opertes s slve (multiprocessing). The SDA10 pin llows ccess to ll bnks simultneously during refresh nd prechrge-ll commnd. This pin must be connected to the A10 pin of the SDRAM. Note tht the SDA10 pin replces the DSP s A[10] nd A[11] pins in 32-bit nd 64-bit bus width configurtion, respectively. Also, during ccess to the ~MSSD spce, these pins re inctive. 6.7 Burst Mode Although the SDRAM device is progrmmed for full pge burst, the controller uses qud-word (128-bits) burst mode. For 32-bit bus width, the burst length is 4 words, nd for 64-bit width, the burst length is 2 words. Only the first red or write commnd is ccompnied with n externl ddress, which is driven by the controller until the burst is interrupted by nother ddress. It s lso importnt to note tht the SDRAM Controller burst mode cnnot be chnged. 6.8 Prechrge All (PREA) This commnd prechrges ll SDRAM bnks simultneously (SDA10 high to select ll bnks), which brings the bnks into idle stte. Although only one bnk t time cn be ctive, the controller does not support single bnk prechrge. 6.9 Circulr Access The controller supports circulr ccesses during sequentil red or writes within pge, performing fixed throughput of 1 cycle/word. At the end of the pge (defined in the SDRCON register), the instructions xr3:0=q[j1+=lst_word];; followed by xr7:4=q[j1+=first_word];; re lso executed with 1 cycle/word throughput. This functionlity is similr to the IALU s circulr buffering mode supported by the TigerSHARC core Auto-Refresh (REF) After the SDRAM registers the uto-refresh commnd, it internlly sserts CAS nd delys RAS to execute row s refresh. The row intervl is typiclly trc=15,625 µs, which is good compromise between dt ccess time nd the refresh relibility. The limit of refresh period is given through the trefmx spec. Note tht the controller does not support burst refresh Self-Refresh (SREF) The self-refresh is very effective wy of reducing the ppliction s power consumption to minimum. When host processor gins control of the cluster bus, the TigerSHARC SDRAM controller brings the SDRAM into self-refresh mode before the bus is relinquished to the host. The SDRAM strts refreshing itself triggered by n internl timer. The controller does not llow bringing the SDRAM into self-refresh mode by softwre, only during host ccesses. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 12 of 44

13 6.12 Mode Register Set (MRS) During the MRS commnd, the SDRAM controller initilizes the SDRAM with the following fixed settings: Burst length is hrdwired to full pge burst Burst type is hrdwired to sequentil burst Red Ltency (CL) is user specified (1-3 cycles) The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 13 of 44

14 7 SDRAM Progrmming Before externl bus trnsctions to SDRAM strt, the system nd SDRAM control registers must be configured ccordingly. 7.1 SYSCON Register The SYSCON register is the system configurtion register nd must be configured fter hrdwre reset t the beginning of the source code. This register my only be configured once, nd dditionl write to SYSCON fter the first re ignored. This register is composed of different fields, lthough only the following pplies for SDRAM: Bus Width: 0: 32-bit bus 1: 64-bit bus For proper opertion, ensure tht the dedicted bus width bits settings is: Note tht if either the host or memory bus width is 64-bits, the multiprocessing width must lso be 64-bits. Also, using 64-bit mode, the DSP ddress 0 pin becomes redundnt, since its informtion is contined in the strobes. Therefore, this pin is not connected for SDRAM ccesses in 64-bit mode (see Figure 1). The following digrm shows the ADSP-TS101S externl port dt lignment for both, 32 nd 64-bit bus configurtions: Figure 5 ADSP-TS101S Externl Port Dt Alignment 7.2 SDRCON Register The SDRAM progrmming is done by the SDRCON register. Similr to SYSCON, it cn only be progrmmed once fter reset nd its vlue should remin unchnged during norml opertion. In systems where more thn one DSP is used, this register must be progrmmed to the sme setup in every processor. The SDRCON bit fields re: SDRAM Enble: set whenever n SDRAM is present in the system. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 14 of 44

15 CAS Ltency: this bit is used to define the red ltency (CLmin) relted to the vendor s device. This vlue cn be set from 1 to 3 cycles, depending on the SDRAM chrcteristics nd the clock frequency. Pipe depth: this bit llows the SDRAM ddress nd control lines to be pipelined. Setting this bit introduces one-cycle dely during red nd write ccesses. Pge Boundry: this bit determines the pge size of the SDRAM, which cn be set to 256, 512, or 1024 words. Refresh Counters: these bits enble coordintion of the clock rte with the SDRAM s required refresh rte. It is used to select between 4 different refresh rtes clculted with the following eqution: Cycles = Clock tref Rows = ( Clock refresh _ rte ) The ADSP-TS101S supports refresh rtes of 600, 900, 1200 or 2400 cycles. The following tble illustrtes how to select between the different rtes bsed on the formul bove. Clock frequency (MHz) Refresh rte (cycles) SDRCON Bits [8:7] f < f < f <150* f 150* * Note tht the mximum externl port frequency supported by the ADSP-TS101S is 100 MHz. Prechrge to RAS dely (trp): this bit defines the prechrge time (trpmin) relted to the vendor s device. This vlue cn be set from 2 to 5 cycles. Note tht this prmeter is defined in most SDRAMs in nnoseconds dely rther thn number of cycles. RAS to prechrge dely (tras): this bit is used to define the row ctive time (trasmin) relted to the vendor s device. This vlue cn be progrmmed from 2 to 8 cycles. Note tht this prmeter is lso defined in nnoseconds rther thn number of cycles. Initiliztion Sequence: this bit determines the order of the MRS (Mode Register set) nd refresh sequences. When set, MRS follows refresh in the SDRAM initiliztion sequence. Otherwise, the MRS precedes refresh: Init Sequence = 0 PREA commnd - brings the SDRAM in the defined idle stte. 8 REF commnds - chrges SDRAM s internl nodes. MRS commnd - initilizes the SDRAM s working mode. Init Sequence = 1 PREA commnd - brings the SDRAM in the defined idle stte. MRS commnd - initilizes the SDRAM s working mode. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 15 of 44

16 8 REF commnds - chrges SDRAM s internl nodes. tras nd trp re used for the refresh cycle, which cn be expressed s: trfc=tras+trp. Also, the specifiction requires tht trasmin, trpmin, nd CLmin re defined s integer frction of the SCLK period. 7.3 SDRAM Mode of Opertion During the MRS, ddress bits ADDR[13:0] of the SDRAM re used to progrm the device. The MRS is executed during power-up only nd it is lwys issued by the TigerSHARC with ID=000. MRS initilizes the following prmeters: A[2:0] - Burst length is hrdwired to full pge burst. A[3] - Burst type is hrdwired to sequentil burst. A[6:4] - Ltency mode set ccording to the CAS ltency progrmmed in SDRCON (1-3 cycles). A[13:7]- hrdwired to zero (reserved mode of opertion for future needs). 7.4 ADSP-TS101S EZ-KIT Lite The ADSP-TS101S TigerSHARC Processor EZ-KIT Lite includes n SDRAM PC-DIMM module, which is either 128-Mbyte or 32-Mbyte, depending on the EZ-KIT revision used. The following tble shows the different SDRAM control register settings depending on the module used: EZ-KIT Rev. SDRAM Module SDRAM CLK SDRAM Settings SDRCON Mbyte 83.3 MHz SDRAM Enble = Mbyte 83.3 MHz CAS Ltency = 2 Pipe Depth = 0 Pge size = 1k Refresh rte = 1200 trp = 3, tras = 4 Init Sequence = 1 SDRAM Enble = 1 CAS Ltency = 2 Pipe Depth = 0 Pge Size = 256 Refresh rte = 1200 trp = 3, tras = 4 Init Sequence = 1 0x5323 0x5303 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 16 of 44

17 7.5 SDRAM Setting Overview Timing spec Controller Description tck MHz clock cycle time, hrdwre trefmx cycles refresh period CLmin 1-3 cycles red ltency trasmin 2-8 cycles ctivte to prechrge trpmin 2-5 cycles prechrge period trcd trcd = CL (fixed) RAS to CAS dely trfcmin trfc = tras+ trp (fixed) Auto-refresh period tmrd 2 cycles (fixed) mode register to commnd txsr trfc + trp (fixed) Exit self refresh to ctive SDRAM (Mode Register Set) Power up Mode PREA-MRS-REF or PREA-REF-MRS Burst Mode sequentil (fixed) Burst Length full pge (fixed) CL 1-3 cycles The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 17 of 44

18 8 Power-up Sequence The power-up procedure for the SDRAM interfce is shown in figure 6: HW- Reset required to strt power up mode SDCKE Self refresh enbled CLOCK ~MSSD Controller Initiliztion SDRAM's commnd decoder enbled [H:L]DQM SDRAM Initiliztion DQ Buffers enbled SDA10 CMD strt of power up sequence 8 x REF PREA NOP REF REF MRS NOP ACT VDD, VDDQ nd clock stble Commnd decoder disbled trp 8 x trcmin tmrd strt norml opertion 1. Hrdwre init. 2. Softwre init. Figure 6 Power-up nd Initiliztion: PREA-REF-MRS 8.1 Hrdwre Initiliztion After hrdwre reset of the ADSP-TS101S, the clock nd the SDRAM s power supply pins (VDD nd VDDQ) must provide stble signl for typicl minimum time of 200µs. The SDRCON register cn be ccessed only fter this time hs elpsed. 8.2 Softwre Initiliztion The SDRAM controller is initilized by writing to the SDRCON register. As soon s ~MSSD is sserted, the SDRAM s commnd decoder is enbled. The Init Sequence bit in SDRCON strts the initiliztion sequence (refer to section 7.2 SDRCON Register). During this time, the [H:L]DQM lines sty high, three-stting the SDRAM DQ buffers. Once The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 18 of 44

19 the initiliztion sequence is completed, the buffers re enbled nd the SDRAM is redy for norml opertion. The time elpsed before the first ccess to SDRAM cn be represented s: tccess trp + 8(tRAS + trp) + tmrd (SCLK cycles) Note tht in order to properly initilize the SDRAM, the first ccess is delyed with the internl cknowledge until the power up sequence hs finished. 8.3 SDRAM Initiliztion Exmple This section shows how to initilize the SDRCON register ccording to the following device specifictions. 2M x 32 bit SDRAM: 4 bnks, pge size: 256 words SDRAM Clock: 60 MHz Speed grde: 70 Refresh cycles: 4096/64ms Power-up mode: PRE - MRS - REF trasmin=42 ns, trpmin=20 ns No self refresh No buffering Therefore, the SDRAM initiliztion code would look s follows: j1 = j31 + 0x ;; SDRCON = j1;; // ENA=1, CL=2, pipedepth=0, pge=256w // refresh rte=900, trp=2, trs=3, init=1 Note tht the minimum timing specifictions for tras, trp, nd CL must be gurnteed. Setting these vlues lrger thn the minimum required cuses loss of performnce. (e.g. longer dely cycles or unnecessry refresh cycles). 8.4 SDRAM Interfce After Reset After power up nd when the ADSP-TS101S reset pin is desserted, the SDRAM-lines re in the following stte: Pin Stte Description SDCKE 1 SDRAM Clock enbled ~MSSD 1 commnd decoder disbled ~RAS 1 Deselected ~CAS 1 Deselected ~SDWE 1 Deselected [H:L]DQM 1 SDRAM dt buffers disbled SDA10 1 Access ll bnks simultneously The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 19 of 44

20 9 DMA Trnsfers Direct Memory Access (DMA) is mechnism for trnsferring dt without core involvement. Trnsfers cn be between internl nd externl memory, or between externl memory nd n externl peripherl. 9.1 Internl Memory nd SDRAM The TigerSHARC DMA controller cn be used to trnsfer dt from the DSP s internl memory to externl SDRAM. Similrly, the SDRAM cn be used s the source nd the internl memory s the destintion. 9.2 Externl Device nd SDRAM (FLY-BY) ADSP-TS101S SDCKE controlled by host ccess mx. 100 MHz int. CLK int. RD int. WR int. Reset int. ACK busy SDCKE ~RAS ~CAS ~SDWE [H:L]DQM CKE ~RAS ~CAS ~WE [H:L]DQM CLK Core DMA int. MSSD Externl Port Buffers disbled D63:0 Address Multiplexer SDA10 ~MSSD A12:13 A1:11 A10 ~CS BA0:1 A0:9,11 SDRAM Dely buffer DQ63:0 Inctive ~HBR ~HBG ~FLYBY ~IOEN ~DMAR0 ~CS ~OE I/O Device Figure 7 Signl chin: Fly-by DMA nd SDRAM Dt trnsfers between externl SDRAM nd externl I/O device is lso supported. In this mode, there is no core intervention, nd only the TigerSHARC DMA controller is used to perform the correspondent dt trnsfer between the two externl devices. This is clled fly-by mode. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 20 of 44

21 When the I/O-device wnts to trnsfer dt, it sserts the ~DMAR0 pin only DMA chnnel 0 cn be used for fly-by trnsctions. Note tht the ~DMAR0 is edge sensitive. Ech ssertion (flling edge) of the ~DMAR0 signl represents one trnsction. The ~FLBY is used s chip select for the I/O device nd ~IOEN llows red trnsction (output enble) from the I/O. For more detils on the TigerSHARC DMA controller nd Fly-by Mode, refer to the Direct Memory Access nd the Cluster Bus chpters of the ADSPTS101 TigerSHARC Processor Hrdwre Reference Mnul [1]. Also, Understnding DMA on the ADSP-TS101S (EE-143) [4] is vilble. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 21 of 44

22 10 SDRAM Interfce in Host Mode Figure 8 shows possible signl chin between the ADSP-TS101S, SDRAM, nd host processor. ADSP-TS101S SDCKE controlled by host ccess mx. 100 MHz Core DMA int. CLK int. RD int. WR int. Reset int. ACK int. MSSD busy disbled A31:0 SDCKE ~RAS ~CAS ~SDWE [H:L]DQM SDA10 ~MSSD A12:13 CKE ~RAS ~CAS ~WE [H:L]DQM A10 ~CS BA0:1 CLK SDRAM Externl Port Buffers D63:0 A0:9, 11 Dely buffer DQ63:0 Inctive ~HBR ~HBG ~FLYBY ~IOEN ~DMAR0 I/O Device Host ~CS ~OE Figure 8 Signl Chin: Host to ADSP-TS101S Host ccesses re initited by hving the host ssert ~HBR to request the externl bus to the TigerSHARC. Therefter, the TigerSHARC responds to this request by sserting ~HBG, grnting the bus to the host. The host becomes bus mster nd cn now ccess the internl TigerSHARC resources through its multiprocessor memory spce. Note tht during ~HBG low, the SDRAM is in self-refresh mode. This limits the host device to not being ble to ccess the SDRAM using the TigerSHARC s SDRAM controller (fly-by mode). Thus, during host trnsctions, the SDRAM cn only be ccessed by host using its own SDRAM controller. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 22 of 44

23 However, workround for this my be possible if the host follows the given sequence: 1. Initilly, the TigerSHARC is current bus mster. To gin control of the bus, the host sserts ~HBR nd wits for the TigerSHARC to grnt the bus (~HBG) 2. The host becomes bus mster nd is now ble to ccess the internl resources of the TigerSHARC. 3. The host sets up DMA trnsfer to hve the TigerSHARC trnsfer dt to SDRAM upon host requests (DMA request line ~DMAR0). 4. The host relinquishes the bus (de-sserts ~HBR), which brings the SDRAM out of self-refresh mode 5. Finlly, the host strts toggling ~DMAR0, indicting to the TigerSHARC to strt trnsmitting dt to the SDRAM. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 23 of 44

24 11 Multiprocessing This section covers the rbitrtion logic used to gurntee multiprocessing systems Commnd Decoding The ADSP-TS101S cn be connected to multiprocessor cluster of eight DSPs. Only one TigerSHARC cn drive the bus t the time. To build glueless hrdwre, the interfce works in slve mode s well to detect commnds. These commnds re MRS, REF, nd SREF. Following pins re necessry for detection: Pin Type Description SDCKE I/O/T SDRAM Clock Enble ~MSSD I/O/T Memory Select SDRAM (commnd input) ~RAS I/O/T Row Address Select (commnd input) ~CAS I/O/T Column Address Select (commnd input) ~SDWE I/O/T SDRAM Write Enble (commnd input) I=input, O=output, T=three-stte 11.2 MRS Decoding In TigerSHARC multiprocessor systems where SDRAM is used, the Mode Register Set sequence is only issued by the DSP with ID=000. Therefore, DSP with ID=000 must be present in every multiprocessor system. The MRS sequence is only issued once before ccessing the SDRAM for the first time. It is lso importnt to note tht the set-up vlue initilized in the SDRCON register must be identicl for ll DSPs in the cluster REF Decoding This detection helps to synchronize ll eight refresh counters. The slve s refresh counter will be decremented ech time the interfce detects refresh. This feture gurntees periodic refresh nd, similrly to the MRS sequence, it requires the exct sme settings of SDRCON registers SREF Decoding This detection helps to synchronize the self-refresh bse. When host requests the bus, the system mster brings the SDRAM into self-refresh mode. The slve DSPs recognize the SREF freezing the refresh counters until the self-refresh mode is exited Bus Trnsition Cycle The bus trnsition or turn-over cycle is issued when bus mstership chnges between the different TigerSHARCs shring the cluster bus. This lso implies mstership trnsition between the SDRAM controllers. Since the new bus mster is not ble to determine which row in the SDRAM is currently open, the current bus mster utomticlly issues prechrge-ll commnd (PREA) before the bus is The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 24 of 44

25 relinquished to the new bus mster. This wy, the new bus mster cn sfely strt ccessing the SDRAM by simply issuing n ctivtion commnd (ACT). This sequence is shown in Figure 9: SCLK /BR0 /BR1 DSP ID 0 Requests the Bus nd it wits for Bus Mster to finish current trnsction DSP ID 1 Requests the Bus nd it becomes Bus Mster DSP ID 0 is now Bus Mster nd strts ccessing SDRAM (ACT) CMD ACT NOP WR NOP WR NOP BST PREA ACT NOP WR NOP DSP ID 1 Relinquishes the Bus fter issuing PREA Figure 9 Bus Trnsition Cycle during SDRAM Accesses The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 25 of 44

26 12 SDRAM nd Booting 12.1 Loder Kernel Dt must be loded in SDRAM before runtime. This requires n initilized SDRAM before downloding the dt during the boot scenrio. The VisulDSP++ loder utility provides this cpbility. Three stndrd loder executbles re vilble for booting either n EPROM (vi link ports) or host processor. Note tht independently from the selected boot mode, the SDRAM control register (SDRCON) must be initilized before the user s ppliction strts writing dt to it. This must be done during the first 256-loder kernel words; otherwise the dt plced in the SDRAM will get corrupted. The steps re: 1. ~RESET must be desserted, ~BMS is smpled 2. Kernel (256 x 32 bit) is trnsmitted vi DMA into the DSP (0x00-0xFF) (~BMS or ~HBG continuously sserted) 3. Interrupt genertion strts kernel execution, SDRAM nd controller is initilized (~MSSD sserted for SDRAM setup) 4. User s dt is loded into the DSP/SDRAM (~BMS, ~HBG nd ~MSSD re toggling requesting the bus) 5. Kernel is now overwritten with user s code (~BMS or ~HBG continuously sserted) 6. DSP strts code execution t strt ddress 0x Booting Modes The boot mode is selected t the end of reset by smpling the ~BMS pin. At this stge, four options for beginning opertion cn be selected: Mode ~BMS DMA chnnel EPROM 0 (Defult) Hrdwired DMA Chnnel 0 Link Port 1 Link Port DMA Chnnels 8-11 Host 1 AutoDMA Chnnels 0-1 No boot 1 - If ~BMS is smpled low during reset, EPROM boot is selected. However, if ~BMS is smpled high during reset, the DSP will go into n IDLE stte, witing for host or link boot. Refer to ADSP-TS101S TigerSHARC Processor Boot Loder Kernels Opertion (EE-174) [5], which describes ech mode of opertion in more detil. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 26 of 44

27 13 SDRAM Interfce Throughput This section investigtes the SDRAM controller s performnce during dt trnsfers, where the SDRAM is used s either source or destintion. The following settings will be used: Silicon = ADSP-TS101S Rev0.0 SCLK = 60 MHz (externl port nd SDRAM clock) LCLK = 180 MHz (core clock) SYSCON = 0x3A79E7, for 64-bit bus configurtion SDRCON = 0x4883, where Pge Boundry = 256 words, Refresh rte = 900 cycles, t RAS =3 cycles, t RP =2 cycle, CL=2 cycles, The following digrms correspond to the different types of core/iop ccesses to SDRAM. Additionlly, listing of the instructions nd SDRAM commnds executed during ech memory ccess re listed. Note tht the externl bus is configured to 64-bits wide. Therefore, every dt word red/written from/to the SDRAM will be 64-bits (i.e. DA1, DA2, DB1, etc.). The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 27 of 44

28 13.1 Sequentil Reds without Interruption As shown below, uninterrupted sequentil reds hve throughput of 1 word per cycle fter the first word is red. SCLK 4 Qud-word Sequentil Uninterrupted on Pge Reds trcd CL CMD ACT NOP RD NOP RD NOP RD NOP RD NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=j4];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 xr7:4=q[j1+=j4];; RD DA1 6 int. ACK NOP DA2 7 xr11:8=q[j1+=j4];; RD DB1 8 int. ACK NOP DB2 9 xr15:12=q[j1+=j4];; RD DC1 10 int. ACK NOP DC2 11 int. ACK DD1 12 int. ACK DD2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 28 of 44

29 13.2 Non Sequentil Reds without Interruption Similr to uninterrupted sequentil reds, non-sequentil reds lso give 1 word/cycle throughput. SCLK 4 Qud-word Non-sequentil Uninterrupted on Pge Reds trcd CL CMD ACT NOP RD NOP RD NOP RD NOP RD NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=j4];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 xr7:4=q[j1+=j4];; RD DA1 6 int. ACK NOP DA2 7 xr11:8=q[j1+=j4];; RD DB1 8 int. ACK NOP DB2 9 xr15:12=q[j1+=j4];; RD DC1 10 int. ACK NOP DC2 11 int. ACK DD1 12 int. ACK DD2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 29 of 44

30 13.3 Sequentil Reds with minimum Interruption In this cse, n dditionl core ccess is performed during core red from SDRAM, interrupting the dt trnsfer. Similrly, n IOP red is interrupted by higher priority request to IOP. In this cse, the throughput is 1 word every 8 cycles. SCLK 3 Qud-word Sequentil Interrupted on Pge Reds trcd CL CL CMD ACT NOP RD NOP BST NOP NOP RD NOP RD NOP Burst 6 NOPs Burst ADDR Row Col Col Col DATA DA1 DA2 DB1 DB2 DC1 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=j4];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 xr0=r1+r2;; BST DA1 6 int. ACK NOP DA2 7 int. ACK NOP 8 int. ACK NOP 9 int. ACK NOP 10 int. ACK NOP 11 int. ACK NOP 12 xr7:4=q[j1+=j4];; RD 13 int. ACK NOP 14 xr15:12=q[j1+=j4];; RD DB1 15 int. ACK NOP DB2 16 int. ACK NOP DC1 17 int. ACK NOP DC2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 30 of 44

31 13.4 Sequentil Writes without Interruption As shown below, uninterrupted sequentil writes hve throughput of 1 word per cycle. 4 Qud-word Sequentil Uninterrupted on Pge Writes SCLK trcd CMD ACT NOP WR NOP WR NOP WR NOP WR NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=j4]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 q[j1+=j4]=xr7:4;; WR DB1 6 int. ACK NOP DB2 7 q[j1+=j4]=xr11:8;; WR DC1 8 int. ACK NOP DC2 9 q[j1+=j4]=xr15:12;; WR DD1 10 int. ACK NOP DD2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 31 of 44

32 13.5 Non Sequentil Writes without Interruption Similr to uninterrupted sequentil writes, non-sequentil writes lso give 1 word/cycle throughput. SCLK trcd 4 Qud-word Non-sequentil Uninterrupted on Pge Writes CMD ACT NOP WR NOP WR NOP WR NOP WR NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=j4]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 q[j1+=j4]=xr7:4;; WR DB1 6 int. ACK NOP DB2 7 q[j1+=j4]=xr11:8;; WR DC1 8 int. ACK NOP DC2 9 q[j1+=j4]=xr15:12;; WR DD1 10 int. ACK NOP DD2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 32 of 44

33 13.6 Sequentil Writes with minimum Interruption In this cse, n dditionl core ccess is performed during core/iop write to SDRAM. As shown below, the SDRAM ccess does not get interrupted, nd it opertes s for un-interrupted writes, 1 word/cycle. Note tht higher number of core ccesses during write to SDRAM my cuse throughput decrese depending upon system speed nd core ctivity. SCLK trcd 4 Qud-word Sequentil Interrupted on Pge Writes CMD ACT NOP WR NOP WR NOP WR NOP WR NOP Burst ADDR Row Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=j4]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 q[j1+=j4]=xr7:4;; WR DB1 6 xr0 = r1 + r2;; NOP DB2 7 q[j1+=j4]=xr11:8;; WR DC1 8 int. ACK NOP DC2 9 q[j1+=j4]=xr15:12;; WR DD1 10 int. ACK NOP DD2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 33 of 44

34 13.7 Reds between Pge/Bnk Core/IOP reds from SDRAM interrupted by off-bnk/pge ccesses. Crossing bnk/pge boundries hve gret impct in performnce, giving 1 word per 12 cycles throughput. Sequentil Reds between Pges or Bnks SCLK CL trp trcd CL CMD RD NOP BST NOP NOP PREA NOP ACT NOP Burst RD Burst NOP BST ADDR Col 6 NOPs Row Col DATA DA1 DA2 DB1 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=260];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 int. ACK BST DA1 6 int. ACK NOP DA2 7 int. ACK NOP 8 int. ACK NOP 9 int. ACK NOP 10 int. ACK NOP 11 int. ACK NOP 12 int. ACK PREA 13 int. ACK NOP 14 xr7:4=q[j1+=j4];; ACT 15 int. ACK NOP 16 int. ACK RD 17 int. ACK; NOP 18 int. ACK; BST DB1 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 34 of 44

35 13.8 Writes between Pge/Bnk Core/IOP writes to SDRAM interrupted by off-bnk/pge ccesses. Like for red ccesses, lthough smller, crossing bnk/pge boundries hve gret impct in performnce, giving 1 word per 6 cycles throughput. Sequentil Writes between Pges or Bnks SCLK trp trcd CMD WR NOP BST PREA NOP ACT NOP Burst WR Burst NOP ADDR Col Row Col DATA DA1 DA2 DB1 DB2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=260]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 int. ACK BST 6 int. ACK PREA 7 int. ACK NOP 8 q[j1+=j4]=xr7:4;; ACT 9 int. ACK NOP 10 int. ACK WR DB1 11 int. ACK NOP DB2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 35 of 44

36 13.9 Minimum Red to Write Intervl The following digrm shows n SDRAM red to write trnsction. As shown below, the trnsition from one ccess to nother introduces some cycles of overhed, resulting in loss of performnce, 1 word per 6 cycles. SCLK On Pge Red to Write Trnsction trcd CL CMD ACT NOP RD NOP BST NOP NOP NOP NOP NOP NOP WR NOP Burst Burst ADDR Row Col Col DATA DA1 DA2 DB1 DB2 SDA10 Nr. Cycles Core Controller Dt 1 xr3:0=q[j1+=j4];; ACT 2 int. ACK NOP 3 int. ACK RD 4 int. ACK NOP 5 int. ACK BST DA1 6 int. ACK NOP DA2 7 int. ACK NOP 8 int. ACK NOP 9 int. ACK NOP 10 int. ACK NOP 11 int. ACK NOP 12 q[j1+=j4]=xr7:4;; WR DB1 13 int. ACK NOP DB2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 36 of 44

37 13.10 Minimum Write to Red Intervl The following digrm shows n SDRAM write to red trnsction. As for red to write trnsitions, some cycles of overhed re introduced, resulting in loss of performnce, 1 word per 4 cycles. SCLK On Pge Write to Red Trnsction trcd CL CMD ACT NOP WR NOP BST RD NOP Burst Burst BST ADDR Row Col Col DATA DA1 DA2 DB1 DB2 SDA10 Nr. Cycles Core Controller Dt 1 q[j1+=j4]=xr3:0;; ACT 2 int. ACK NOP 3 int. ACK WR DA1 4 int. ACK NOP DA2 5 int. ACK BST 6 xr7:4=q[j1+=j4];; RD 7 int. ACK NOP 8 int. ACK BST DB1 9 int. ACK NOP DB2 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 37 of 44

38 13.11 Chined DMA Trnsfers When using chined DMAs, higher throughput cn be chieved. However, s shown below, performnce difference cn be seen between chined DMA writes nd reds to nd from SDRAM. Loding of the TCB for chined red DMAs requires dditionl core cycles. Chined DMA Reds SCLK CL trp trcd CL 6 CMD RD NOP RD NOP BST PREA NOP ACT NOP NOPS RD NOP RD NOP ADDR Col Loding of TCB Row Col DATA DA1 DA2 DB1 DB2 DC1... SDA10 Chined DMA Writes SCLK trcd CMD ACT NOP WR NOP WR NOP WR NOP WR NOP WR NOP Burst ADDR Row Col Col Col Col Col DATA DA1 DA2 DB1 DB2 DC1 DC2 DD1 DD2 DE1 DE2 SDA10 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 38 of 44

39 13.12 Auto-Refresh The refresh counter triggers refresh requests when expired. The following digrm shows the refresh sequence. All bnks re prechrged (SDA10 sserted high) right fter the internl counter issues the refresh. A REF commnd strts n internl row refresh with CAS before RAS. During refresh, no other commnds cn be executed. The rtio between ppliction time nd refresh time is given by: t RC =15,625µs/rows e.g. 8 cycles/900 cycles x 100 = 0.88% This mens tht the refresh sequence requires 0.88 % of the whole performnce t 60 MHz. Auto refresh with µs/row gives the best performnce rtio. This rtio cn be modified ccordingly to the system needs by chnging the refresh rte progrmmed in SDRCON. Auto Refresh 60 MHz tras=3 cycles, trp=2 cycles SCLK CMD BST PREA NOP REF NOP NOP NOP NOP ACT NOP Refresh counter expired trp trc continue norml opertion SDA10 The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 39 of 44

40 13.13 Self-Refresh nd Host Accesses The following digrms show rndom host ccess during red from SDRAM: Host Bus Request during SDRAM Reds - Host Entry SCLK ~HBR Host requests the bus to the DSP ~HBG Host is grnted the bus SDCKE Burst trp CMD RD NOP RD NOP BST 6xNOP PREA NOP SREF ADDR Col Col BST issued to grnt the host ccess Enter Self-refresh mode SDA10 Host Bus Grnt during SDRAM Reds - Host Exit SCLK ~HBR Host relinquishes the bus ~HBG SDCKE CMD SREF txsr = trc + trp SREF NOP NOP PREA NOP REF NOP ACT NOP Open bnk nd continue with norml opertion RD ADDR Exit Self-refresh mode trc = trp + tras trp trc Row Col SDA10 After the detection of host request, the current burst opertion of the SDRAM controller is interrupted nd frozen. The TigerSHARC DSP enters self-refresh mode, in response to host bus request (~HBR), before the bus is relinquished to the host. As shown bove, the controller issues BST commnd, The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 40 of 44

41 stopping the current ction. In order to provide current informtion, ll bnks re prechrged. During the PREA nd the SREF commnd, the SDCKE pin trnsitions from high to low, thus enbling the selfrefresh mode. After dessertion of ~HBG, the controller ends the self refresh function nd the SDCKE line trnsits high. Following, the controller issues refresh sequence. The bnk is then ctivted nd it continues with norml opertion, reding dt from where it left off. Note tht only the SDCKE pin keeps control of the device in self-refresh mode. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 41 of 44

42 13.14 SDRAM Performnce Tble The following tble gives summry of ll the different SDRAM ccesses previously explored. Accesses Opertions Pge Sequentil Uninterrupted Red Sme 1 word/1 cycle Non-sequentil Uninterrupted Red Sme 1 word/1 cycle Sequentil Interrupted Red Sme Throughput per SDRAM Clock (64-bit words) 1 1 word/ 8 cycles (6 + CL) Sequentil Uninterrupted Write Sme 1 word/1 cycle Non-sequentil Uninterrupted Write Sme 1 word/1 cycle Sequentil Interrupted Write Sme 1 word/1 cycle Both Red to Write Sme 1 word/6 cycles Both Write to Red Sme Nonsequentil Reds Different Nonsequentil Writes Different Autorefresh before red Reds Different Autorefresh before write Writes Different 1 word/4 cycles (2 + CL) 1 word/12 cycles (6+ t RP + t RCD +CL) 1 word/6 cycles (2+ t RP + t RCD ) 1 word/17 cycle (6+ 2t RP + t RAS + t RCD +CL) 1 word/11 cycle (2+ 2t RP + t RAS + t RCD ) CAS ltency (CL) = 2 cycles, Prechrge (t RP ) = 2 cycles, t RAS = 3 cycles, t RCD = CL = 2 cycles 1 SYSCON Externl bus width configurtion: 64-bit bus. The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 42 of 44

43 14 Optimizing SDRAM Performnce There re severl wys in which the SDRAM performnce cn be optimized depending on the system set up nd ppliction. Some of these re explined below: 14.1 Externl Buffering In prllel connections, one ddress nd control bus feeds ll the system devices. In order to meet the timing requirements nd help ginst cpcitive lod, the TigerSHARC controller provides feture to cope with this sitution. The controller hs the cpbility of pipelining the SDRAM ccesses by mking use of the internl dely buffer. In SDRCON, setting the pipe depth bit to 1 inserts this dely buffer, llowing ddress nd commnd pipelining. It is recommended to set this bit if the cpcitive lod of 30 pf/pin is exceeded. The dt sheet s timing is bsed on nominl lod of 30 pf/pin. Figure 10 shows possible system set-up where n externl buffer is used in conjunction with the dely buffer provided by the TigerSHARC controller. The externl buffer reduces cpcitive lod nd power dissiption but increses the pipeline effects. ADSP-TS101S Clock Core DMA int. CLK int. RD int. WR int. Reset int. ACK int.~mssd Externl Port Buffers busy enbled A31:0 D63:0 Control Interfce Address Multiplexer SDCKE ~RAS ~CAS ~SDWE [H:L]DQM Dely buffer SDA10 ~MSSD A13 A12 A1:9, 11:12 A10 CLK CKE ~RAS ~CAS ~WE [H:L]DQM Registered Buffer ~CS A13/BANK A12/BANK A11:0 DQ63:0 SDRAM A31:1 D63:0 Figure 10 Signl chin: ADSP-TS101S to SDRAM Using Externl Buffer The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 43 of 44

44 14.2 Using PC Modules The mximum ddressble size is 64Mx32-bit or 32Mx64-bit. The use of unbuffered PC DIMM modules (typicl I/O sizes x32, x64, or x72 bits) is efficient, becuse most vendors offer size of x64 bits, which is commonly used for PCs. Moreover, depending on the size, the need for externl ddress- nd control buffers (pipelining) is required Generl Rules for Optimized Performnce Depending on the SDRAM s pge size nd number of bnks, plce your dt segments to minimize off pge nd off bnk ccesses. Use prllel connection for SDRAMs with big pge size in order to obtin 32-bit or 64-bit I/O (SDRAM: the bigger the pge size, the smller the I/O structure). Use the optimized settings for the controller s stte mchine (tras, trp, CL) depending on the speed grde nd on the ppliction s speed 15 References [1] ADSP-TS101S TigerSHARC Processor Hrdwre Reference Mnul. Revision 1.0, April Anlog Devices Inc. [2] ADSP-TS101S Dt Sheet. Rev. A, Februry Anlog Devices Inc [3] The ABC of SDRAMemory (EE-126). Rev 1, Mrch Anlog Devices Inc. [4] Understnding DMA on the ADSP-TS101S TigerSHARC (EE-143). October Anlog Devices Inc. [5] ADSP-TS101S TigerSHARC Processor Boot Loder Kernels Opertion (EE-174). April Anlog Devices Inc. 16 Document History Revision Rev 2 December 19, 2003 by Mikel Kokly-Bnnourh nd Robert Hoffmnn Rev 1 December 6, 2002 by Mikel Kokly-Bnnourh nd Robert Hoffmnn Description Generl Updte nd modified Address Mpping Scheme Initil Relese The ADSP-TS101S TigerSHARC On-chip SDRAM Controller (EE-178) Pge 44 of 44