Instruction Set Architecture

Transcription

1 Instruction Set Architecture Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras ISA- 1

2 Instruction Set... the attributes of a [computing] system as seen by the programmer, i. e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls of logic design, and the physical implementation. Amdahl, Blaaw, Brooks, Arquitectura de Computadoras ISA- 2

3 Instruction Set Design software instruction set hardware Which is easier to change/design? Arquitectura de Computadoras ISA- 3

4 Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i. e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls of logic design, and the physical implementation. Amdahl, Blaaw, Brooks, Organization of programmable storage Data types & data structures: encodings and representations Instruction formats Instruction (or Operand Code) Set Modes of addressing and accessing data items and instructions Exceptional conditions Arquitectura de Computadoras ISA- 4

5 ISA: What Must be Specified? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Instruction Format or Encoding how is it decoded? Location of operands and result where other than memory? how many explicit operands? how are memory operands located? which can or cannot be in memory? Data type and Size Operations what are supported Successor instruction jumps, conditions, branches fetch-decode-execute is implicit! Arquitectura de Computadoras ISA- 5

6 Evolution of Instruction Sets Single Accumulator (EDSAC 1950) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953 Separation of Programming Model from Implementation High-level Language Based (B ) Concept of a Family IBM General Purpose Register Machines Complex Instruction Sets (Vax, Intel ) Load/Store Architecture (CDC 6600, Cray ) RISC: MIPS, Sparc, 88000, IBM RS6000, Arquitectura de Computadoras ISA- 6

7 Basic ISA Classes Accumulator: 1 address add A acc acc + mem[a] 1+x address addx A acc acc + mem[a + x] Stack 0 address add tos tos + next General Purpose register 2 address add A B EA(A) EA(A) + EA(B) 3 address add A B C EA(A) EA(B) + EA(C) Load/Store 3 address add Ra Rb Rc Ra Rb + Rc load Ra Rb store Ra Rb Ra mem[rb] mem[rb] Ra Most real machines are hybrids of those Arquitectura de Computadoras ISA- 7

8 Comparing Number of Instructions Comparison: Bytes per instruction? Number of Instructions? Cycles per instruction? Code sequence for (C = A + B) for four classes of instruction sets: Stack Accumulator Register (register-memory) Register (load-store) Push A Load A Load R1,A Load R1,A Push B Add B Add R1,B Load R2,B Add Store C Store C, R1 Add R3,R1,R2 Pop C Store C,R3 Arquitectura de Computadoras ISA- 8

9 General Purpose Registers Dominate x all machines use general purpose registers Advantages of registers registers are faster than memory registers are easier for a compiler to use» e.g., (A*B) (C*D) (E*F) can do multiplies in any order vs. stack registers can hold variables» memory traffic is reduced, so program is sped up (since registers are faster than memory)» code density improves (since register named with fewer bits than memory location) Arquitectura de Computadoras ISA- 9

10 Caches vs. Registers Registers advantages Faster (no addressing mode, no tags) Deterministic (no misses) Can duplicate for two ports Short identifier (3-8 bits) Register disadvantages Must save/restore on procedure calls Can t take the address of a register Fixed size (FP, strings, structures) Compiler must control (?) Arquitectura de Computadoras ISA- 10

11 Caches vs. Registers (cont d) How many registers? More means + Hold operands longer (reducing memory traffic & potentially execution time) - Longer register specifiers (except with register windows) - Slow registers - More state slows context switches Arquitectura de Computadoras ISA- 11

12 MIPS I Registers Programmable storage 2 32 x bytes of memory 31 x 32-bit GPRs (R0 = 0) 32 x 32-bit FP regs (paired DP) HI, LO, PC r0 r1 r31 PC lo hi 0 Arquitectura de Computadoras ISA- 12

13 Typical Operations Data Movement Arithmetic Shift Logical Load (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) integer (binary + decimal) or FP Add, Subtract, Multiply, Divide shift left/right, rotate left/right not, and, or, set, clear Arquitectura de Computadoras ISA- 13

14 Typical Operations Control (Jump/Branch) Subroutine Linkage Interrupt Synchronization String Graphics (MMX) unconditional, conditional call, return trap, return test & set (atomic r-m-w) search, translate parallel subword ops (4 16bit add) little change since 1960 Arquitectura de Computadoras ISA- 14

15 Top 10 80x86 Instructions Rank instruction Integer Average Percent total executed 1 load 22% 2 conditional branch 20% 3 compare 16% 4 store 12% 5 add 8% 6 and 6% 7 sub 5% 8 move register-register 4% 9 call 1% 10 return 1% Total 96% Simple instructions dominate instruction frequency Arquitectura de Computadoras ISA- 15

16 Operation Summary Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, return; Arquitectura de Computadoras ISA- 16

17 Operands for ALU instructions ALU instructions combine operands (e.g. ADD) Number of explicit operands Two - destination equals one source Three - orthogonal Operands in registers or memory Any combination -- VAX» (orthogonal, but variable instr. formats) At least one register -- much of 360» (not orthogonal) All registers -- CRAY, DLX, RISCs» (orthogonal, but needs loads/stores) Arquitectura de Computadoras ISA- 17

18 Memory Addressing Since 1980 almost every machine uses addresses to level of 8-bits (byte) 2 questions for design of ISA: Since could read a 32-bit word as four loads of bytes from sequential byte addresses or as one load word from a single byte address,» How do byte addresses map onto words?» Can a word be placed on any byte boundary? Arquitectura de Computadoras ISA- 18

19 Addressing Objects: Endian Wars Big Endian: address of most significant byte = word address (xx00 = Big End of word) IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian: address of least significant byte = word address (xx00 = Little End of word) Intel 80x86, DEC Vax, DEC Alpha (Windows NT) Mode selectable becoming more common: PowerPC, MIPS R10000 msb little endian byte 0 lsb big endian byte 0 Arquitectura de Computadoras ISA- 19

20 Addressing Objects: Alignment Alignment: require that objects fall on address that is multiple of their size. Aligned Not Aligned Arquitectura de Computadoras ISA- 20

21 Alignment No restrictions Simpler software Hardware must detect misalignment and make 2 memory accesses expensive logic, slows down all references sometimes required for backward compatibility Restrictred alignment software must guarantee alignment hardware only detecs misalignment and traps trap handler does it Middle group misaligned data ok but requires multiple instructions compiler must skill know still trap on misaligned access Arquitectura de Computadoras ISA- 21

22 A typical RISC 32-bit fixed format instruction (3 formats) bit GPR (R0 contains zero, DP take pair) 3-address, reg-reg arithmetic instruction Single address mode for load/store: base+displacement no indirection Simple branch conditions Delay branch see: SPARC, MIPS MC88100, AMD2900, i960, i860, PARisc, DEC Alpha, Clipper, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3,... Arquitectura de Computadoras ISA- 22

23 VAX-11 Byte 0 1 n m OpCode A/M A/M A/M Variable format, 2 and 3 address instruction 32-bit word size, 16 GPR (four reserved) Rich set of addressing modes (apply to any operand) Rich set of operations bit-field, stack, call, case, loop, string, poly, system) Rich set of data types (B, W, L, Q, O, F, D, G, H) Condition codes Arquitectura de Computadoras ISA- 23

24 VAX-11: Addressing Modes 1. Register Ri 2. Base + Displacement M[Ri + v] 3. Immediate v 4. Register Indirect M[Ri] 5. Direct (absolute) M[v] 6. Base + Index M[Ri + Rj] 7. Scaled Index M[Ri + Rj*d + v] 8. Autoincrement M[Ri++] 9. Autodecrement M[Ri--] 10. Memory Indirec M[ M[Ri] ] 11. [Indirection chains] Register File Memory Modes 1-4 account for 93 % of all operands on the VAX Arquitectura de Computadoras ISA- 24

25 Addressing Mode Usage 3 programs measured on machine with all address modes (VAX) --- Displacement: 42% avg, 32% to 55% --- Immediate: 33% avg, 17% to 43% --- Register deferred (indirect): 13% avg, 3% to 24% --- Scaled: 7% avg, 0% to 16% --- Memory indirect: 3% avg, 1% to 6% --- Misc: 2% avg, 0% to 3% 75% displacement & immediate 85% displacement, immediate & register indirect 75% 85% Arquitectura de Computadoras ISA- 25

26 Displacement Address Size? Int. Avg. FP Avg. 30% 25% 20% 15% 10% 5% 0% Address Bits Avg. of 5 SPECint92 programs v. avg. 5 SPECfp92 programs 1% of addresses > 16-bits bits of displacement needed Arquitectura de Computadoras ISA- 26

27 Immediate Size? 50% to 60% fit within 8 bits 75% to 80% fit within 16 bits Arquitectura de Computadoras ISA- 27

28 Addressing Summary Data Addressing modes that are important: Displacement, Immediate, Register Indirect Displacement size should be 12 to 16 bits Immediate size should be 8 to 16 bits Arquitectura de Computadoras ISA- 28

29 Generic Example of Instruction Format Widths Variable: Fixed: Hybrid: Arquitectura de Computadoras ISA- 29

30 Instruction Formats If code size is most important, use variable length instructions If performance is most important, use fixed length instructions Recent embedded machines (ARM, MIPS) added optional mode to execute subset of 16-bit wide instructions (Thumb, MIPS16); per procedure decide performance or density Some architectures actually exploring on-the-fly decompression for more density. Arquitectura de Computadoras ISA- 30

31 Instruction Format If have many memory operands per instruction and/or many addressing modes: =>Need one address specifier per operand If have load-store machine with 1 address per instr. and one or two addressing modes: => Can encode addressing mode in the opcode Arquitectura de Computadoras ISA- 31

32 MIPS Addressing Modes/Instruction Formats All instructions 32 bits wide Register (direct) op rs rt rd register Immediate op rs rt immed Base+index op rs rt immed Memory register + PC-relative op rs rt immed Memory Register Indirect? PC + Arquitectura de Computadoras ISA- 32

33 Most Popular ISA of all time: Intel 80x : Intel invents microprocessor 4004/8008, 8080 in : Gordon Moore realized one more chance for new ISA before ISA locked in for decades hired CS people in Oregon weren t ready in 1977 (CS people did 432 in 1980) started crash effort for 16-bit microcomputer 1978: 8086 dedicated registers, segmented address, 16 bit 8088; 8-bit external bus version of : IBM selects 8088 as basis for IBM PC 1980: 8087 floating point coprocessor: adds 60 instructions using hybrid stack/register scheme 1982: bit address, protection, memory mapping 1985: bit address, 32-bit GP registers, paging Arquitectura de Computadoras ISA- 33

34 Intel x86 (IA-32) 1989: & Pentium in 1992: faster + MP few instructions 1997: MMX multimedia extensions 200X: Superseded by IA-64 (Merced, McKinley, Itanium, etc.) Difficult to explain and impossible to love See H&P Appendix D.8 Eight 32-bit registers (EAX, EBX,..., but also ESP, EBP) Also 16- and 8-bit version (AX, AH, AL) Most instructions have two operands, one possibly from memory One super-duper addressing mode w/ effective address = base_reg + (index_reg * scaling_factor) + displacement Many formats: see H&P fig. D.8 Arquitectura de Computadoras ISA- 34

35 Intel MMX MultiMedia extension to IA-32 [Peleg & Weiser, IEEE Micro, 8/96] Multimedia data values often need much less than 32 bits But are organized in groups (e.g. red/green/blue) So in 64-bit FP registers: 2x32, 4x16, 8x8 E.g. ADDB (for byte) more more more MMX takes 16-element dot product (a 0 *b 0 + a 1 *b a 15 *b 15 ) from 200 to 16 instructions & from 76 to 12 cycles (6x) Arquitectura de Computadoras ISA- 35

36 Typical Operations Control (Jump/Branch) Subroutine Linkage Interrupt Synchronization String Graphics (MMX) unconditional, conditional call, return trap, return test & set (atomic r-m-w) search, translate parallel subword ops (4 16bit add) little change since 1960 Arquitectura de Computadoras ISA- 36

37 Control Instructions Conditional branches Jumps Procedure calls Procedure returns Taken or not taken? X Where is the target? X X Link return address Save or restore state X X X O.S. calls X X X O.O. returns X X X X Arquitectura de Computadoras ISA- 37

38 (1) Taken or not taken? Compare and branch instruction + No extra compare instruction + No state passed between instructions - Requires ALU operation - Restricts code scheduling opportunities Implicitly set condition codes (Z, N, V, C) + Can be set for free - Constrains code reordering - Extra state to save and restore Explicitly set condition codes (Z, N, V, C) + Can be set for free + Decouples branch/fetch from pipeline - Extra state to save and restore Arquitectura de Computadoras ISA- 38

39 (1) Taken or not taken?, cont. Condition in general-purpose register + No special state to save and implement but uses up a register - branch condition separated from branch logic in pipeline Some data for MIPS > 80 % of compares for branches use immediates > 80 % of these immediates are zero 50 % compares for branches are =0 or!= 0 Compromise used in MIPS Have branch-if = 0 and branch-if!= 0 Have compare instructions (r1=r2, r1!= r2, r1 < r2, r1 <= r2, etc.) With pipelining, can we predict whether taken? Statically? Dynamically? Arquitectura de Computadoras ISA- 39

40 (2) Where is the target? Could use Arbitrary Specifier? + Orthogonal and powerful - More bits to specify, more time to decode - branch execution and target separated in pipeline PC-relative with immediate + Position independence (helps linking), target computable in branch unit + Short immediate sufficient. MIPS word immediate: <= 4 bits: 47 % <= 8 bits: 94 % <= 12 bits: 100 % - Target must be known statically (to link) - Can t jump arbitrarily far - Other techniques are required for returns and distance jumps Arquitectura de Computadoras ISA- 40

41 (2) Where is the target?, cont. Register + Short specification + Can jump anywhere + Dynamic target okay (returns) - Extra instruction to load register (Vectored) Trap Critical for O.S. calls + Protection. - Implementation headache Common compromise (Conditional) branches (pc-rel) (Unconditional) jumps (pc-rel, reg) Procedure calls (pc-rel, reg) Procedure returns (reg) O.S. calls (trap) O.S. returns (reg) Arquitectura de Computadoras ISA- 41

42 (3) Link return address? Required for procedure calls and O.S. calls Implicit register + Fast, simple - SW must save register before next call - Surprise traps or interrups? Processor stack + Recursion supported directly - Complex instruction Explicit register - No important advantages over above - Register must be specified Many recent architectures use implicit register Arquitectura de Computadoras ISA- 42

43 (4) Save or restore state? What state? Procedure calls: registers O.S. calls: registers and PSW (incl. CCs) Hardware need not save registers Caller can save registers in use Callee can save registers it will use Hardware register save Which (IBM STM, VAX CALLS)? Is the above faster? Register windows Many recent architectures do no register saving or do implicit saving with register windows Arquitectura de Computadoras ISA- 43

44 MIPS: Register State 32 integer registers $0 ishardwaredto0 $31 is the return address register software convention for other registers 32 single-precision FP registers or 16 doubleprecision FP registers PC and other special registers Arquitectura de Computadoras ISA- 44

45 MIPS I Operation Overview Arithmetic Logical: Add, AddU, Sub, SubU, And, Or, Xor, Nor, SLT, SLTU AddI, AddIU, SLTI, SLTIU, AndI, OrI, XorI, LUI SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access: LB, LBU, LH, LHU, LW, LWL,LWR SB, SH, SW, SWL, SWR Arquitectura de Computadoras ISA- 45

46 Multiply / Divide Start multiply, divide MULT rs, rt MULTU rs, rt DIV rs, rt DIVU rs, rt Move result from multiply, divide MFHI rd MFLO rd Move to HI or LO MTHI rd MTLO rd Why not third field for destination? Registers (Hint: how many clock cycles for multiply or divide vs. add?) HI LO Arquitectura de Computadoras ISA- 46

47 Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word Character: ASCII 7 bit code UNICODE 16 bit code Decimal: digits 0-9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Integers: 2's Complement Floating Point: Single Precision Double Precision Extended Precision M x R E mantissa exponent base How many +/- #'s? Where is decimal pt? How are +/- exponents represented? Arquitectura de Computadoras ISA- 47

48 Operand Size Usage Doubleword 0% 69% Word 31% 74% Int Avg. Halfword 0% 19% FP Avg. Byte 7% 0% 0% 20% 40% 60% 80% Frequency of reference by size Support for these data sizes and types: 8-bit, 16-bit, 32-bit integers and 32-bit and 64-bit IEEE 754 floating point numbers Arquitectura de Computadoras ISA- 48

49 MIPS arithmetic instructions Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible subtract sub $1,$2,$3 $1 = $2 $3 3 operands; exception possible add immediate addi $1,$2,100 $1 = $ constant; exception possible add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions subtract unsigned subu $1,$2,$3 $1 = $2 $3 3 operands; no exceptions add imm. unsign. addiu $1,$2,100 $1 = $ constant; no exceptions multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 $3, Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 $3, Unsigned quotient & remainder Hi = $2 mod $3 Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo Arquitectura de Computadoras ISA- 49

50 MIPS logical instructions Instruction Example Meaning Comment and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND or or $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical OR xor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XOR nor nor $1,$2,$3 $1 = ~($2 $3) 3 reg. operands; Logical NOR and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant or immediate ori $1,$2,10 $1 = $2 10 Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable Arquitectura de Computadoras ISA- 50

51 MIPS data transfer instructions Instruction SW 500(R4), R3 SH 502(R2), R3 SB 41(R3), R2 LW R1, 30(R2) LH R1, 40(R3) LHU R1, 40(R3) LB R1, 40(R3) LBU R1, 40(R3) Comment Store word Store half Store byte Load word Load halfword Load halfword unsigned Load byte Load byte unsigned LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16) LUI R5 R Arquitectura de Computadoras ISA- 51

52 When does MIPS sign extend? When value is sign extended, copy upper bit to full value: Examples of sign extending 8 bits to 16 bits: When is an immediate value sign extended? Arithmetic instructions (add, sub, etc.) sign extend immediates even for the unsigned versions of the instructions! Logical instructions do not sign extend Load/Store half or byte do sign extend, but unsigned versions do not. Arquitectura de Computadoras ISA- 52

53 Methods of Testing Condition Condition Codes Processor status bits are set as a side-effect of arithmetic instructions (possibly on Moves) or explicitly by compare or test instructions. ex: add r1, r2, r3 bz label Condition Register Ex: cmp r1, r2, r3 bgt r1, label Compare and Branch Ex: bgt r1, r2, label Arquitectura de Computadoras ISA- 53

54 Conditional Branch Distance Int. Avg. FP Avg. 40% 30% 20% 10% 0% Bits of Branch Dispalcement 25% of integer branches are 2 to 4 instructions Arquitectura de Computadoras ISA- 54

55 Conditional Branch Addressing PC-relative since most branches are relatively close to the current PC At least 8 bits suggested (±128 instructions) Compare Equal/Not Equal most important for integer programs (86%) LT/GE GT/LE EQ/NE 7% 7% 23% 40% 37% 86% Int Avg. FP Avg. 0% 50% 100% Frequency of comparison types in branches Arquitectura de Computadoras ISA- 55

56 MIPS Compare and Branch Compare and Branch BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch BNE rs, rt, offset <> Compare to zero and Branch BLEZ rs, offset BGTZ rs, offset > BLT < BGEZ >= if R[rs] <= 0 then PC-relative branch BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31) BGEZAL >=! Remaining set of compare and branch ops take two instructions Almost all comparisons are against zero! Arquitectura de Computadoras ISA- 56

57 MIPS jump, branch, compare instructions Instruction Example Meaning branch on equal beq $1,$2,100 if ($1 == $2) go to PC Equal test; PC relative branch branch on not eq. bne $1,$2,100 if ($1!= $2) go to PC Not equal test; PC relative set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; 2 s comp. set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; 2 s comp. set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; unsigned numbers set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; unsigned numbers jump j go to Jump to target address jump register jr $31 go to $31 For switch, procedure return jump and link jal $31 = PC + 4; go to For procedure call Arquitectura de Computadoras ISA- 57

58 Signed vs. Unsigned Comparison R1= R2= R3= After executing these instructions: two two two slt r4,r2,r1 ; if (r2 < r1) r4=1; else r4=0 slt r5,r3,r1 ; if (r3 < r1) r5=1; else r5=0 sltu r6,r2,r1 ; if (r2 < r1) r6=1; else r6=0 sltu r7,r3,r1 ; if (r3 < r1) r7=1; else r7=0 What are values of registers r4 - r7? Why? r4 = ; r5 = ; r6 = ; r7 = ; Arquitectura de Computadoras ISA- 58

59 Calls: Why Are Stacks So Great? Stacking of Subroutine Calls & Returns and Environments: A: CALL B B: CALL C C: RET RET A A B A B C A B A Some machines provide a memory stack as part of the architecture (e.g., VAX) Sometimes stacks are implemented via software convention (e.g., MIPS) Arquitectura de Computadoras ISA- 59

60 Memory Stacks Useful for stacked environments/subroutine call & return even if operand stack not part of architecture Stacks that Grow Up vs. Stacks that Grow Down: Next Empty? SP Last Full? c b a How is empty stack represented? Little --> Big/Last Full POP: Read from Mem(SP) Decrement SP inf. Big grows up 0 Little 0 Little grows down inf. Big Little --> Big/Next Empty Memory Addresses POP: Decrement SP Read from Mem(SP) PUSH: Increment SP Write to Mem(SP) PUSH: Write to Mem(SP) Increment SP Arquitectura de Computadoras ISA- 60

61 Call-Return Linkage: Stack Frames High Mem ARGS Callee Save Registers Reference args and local variables at fixed (positive) offset from FP (old FP, RA) FP SP Local Variables Grows and shrinks during expression evaluation Low Mem Many variations on stacks possible (up/down, last pushed / next ) Compilers normally keep scalar variables in registers, not memory! Arquitectura de Computadoras ISA- 61

62 MIPS: Software conventions for Registers 0 zero constant 0 1 at reserved for assembler 2 v0 expression evaluation & 3 v1 function results 4 a0 arguments 5 a1 6 a2 7 a3 8 t0 temporary: caller saves... (callee can clobber) 15 t7 16 s0 callee saves... (callee must save) 23 s7 24 t8 temporary (cont d) 25 t9 26 k0 reserved for OS kernel 27 k1 28 gp Pointer to global area 29 sp Stack pointer 30 fp frame pointer 31 ra Return Address (HW) Arquitectura de Computadoras ISA- 62

63 MIPS / GCC Calling Conventions fact: addiu $sp, $sp, -32 sw $ra, 20($sp) sw $fp, 16($sp) addiu $fp, $sp, sw $a0, 0($fp)... lw $31, 20($sp) lw $fp, 16($sp) addiu $sp, $sp, 32 jr $31 First four arguments passed in registers. FP SP ra FP SP ra FP SP ra old FP ra old FP low address Arquitectura de Computadoras ISA- 63

64 Details of the MIPS instruction set Register zero always has the value zero (even if you try to write it) Branch/jump and link put the return addr. PC+4 or 8 into the link register (R31) (depends on logical vs physical architecture) All instructions change all 32 bits of the destination register (including lui, lb, lh) and all read all 32 bits of sources (add, sub, and, or, ) Immediate arithmetic and logical instructions are extended as follows: logical immediates ops are zero extended to 32 bits arithmetic immediates ops are sign extended to 32 bits (including addu) The data loaded by the instructions lb and lh are extended as follows: lbu, lhu are zero extended lb, lh are sign extended Overflow can occur in these arithmetic and logical instructions: add, sub, addi it cannot occur in addu, subu, addiu, and, or, xor, nor, shifts, mult, multu, div, divu Arquitectura de Computadoras ISA- 64

65 Delayed Branches li r3, #7 sub r4, r4, 1 bz r4, LL addi r5, r3, 1 subi r6, r6, 2 LL: slt r1, r3, r5 In the Raw MIPS, the instruction after the branch is executed even when the branch is taken? This is hidden by the assembler for the MIPS virtual machine allows the compiler to better utilize the instruction pipeline (???) Arquitectura de Computadoras ISA- 65

66 Branch & Pipelines Time li r3, #7 sub r4, r4, 1 execute ifetch execute bz r4, LL ifetch execute Branch addi r5, r3, 1 ifetch execute Delay Slot LL: slt r1, r3, r5 Branch Target ifetch execute By the end of Branch instruction, the CPU knows whether or not the branch will take place. However, it will have fetched the next instruction by then, regardless of whether or not a branch will be taken. Why not execute it? Arquitectura de Computadoras ISA- 66

67 Filling Delayed Branches Branch: IF execute successor even if branch taken! Then branch target or continue DEC & OP fetch Execute IF DEC & OP fetch Execute IF Single delay slot impacts the critical path Compiler can fill a single delay slot with a useful instruction 50% of the time. try to move down from above jump move up from target, if safe add r3, r1, r2 sub r4, r4, 1 bz r4, LL NOP... LL: add rd,... Is this violating the ISA abstraction? Arquitectura de Computadoras ISA- 67

68 Miscellaneous MIPS I instructions break A breakpoint trap occurs, transfers control to exception handler syscall A system trap occurs, transfers control to exception handler coprocessor instrs. Support for floating point TLB instructions Support for virtual memory: discussed later restore from exception Restores previous interrupt mask & kernel/user mode bits into status register load word left/right Supports misaligned word loads store word left/right Supports misaligned word stores Arquitectura de Computadoras ISA- 68

69 MIPS: Instruction Set Format load/store architecture with 3 explicit operands (ALU ops) fixed 32-bit instructions 3 instruction formats» R-Type» I-Type» J-Type 6 instruction set groups:» load/store - data movement operations» computational - arithmetic, logical, and shift operations» jump/branch - including call and returns» coprocessor - FP instructions» coprocessor0 - memory management and exception handling» special - accessing special registers, system calls, breakpoint instructions, etc. Arquitectura de Computadoras ISA- 69

70 R2000/3000 Instruction Formats R-type (register) e.g. add $8, $17, $18 # $8 = $17 + $ OpCode rs rt rd shamt funct Arquitectura de Computadoras ISA- 70

71 R2000/3000 Instruction Formats I-type (immediate) e.g. addi $8, $17, -44 # $8 = $17-44 lw $8, -44($17) # $8 = M[$17-44] beq $17, $8, label # if( $8 == $17) go to label: OpCode rs rt immediate op Arquitectura de Computadoras ISA- 71

72 R2000/3000 Instruction Formats J-type (jump) e.g. jump label # call label: ; $31 = $pc OpCode target Arquitectura de Computadoras ISA- 72

73 Bhandarkar and and Clark: RISC vs. CISC Compares the VAX 8700 vs MIPS M/2000 (R3000 chip) Combines three fractors: Architecture Implementation Compilers and OS Argues that: Implementation effects are second order Compilers are similar RISCs are better than CISCs Is it a fair comparison of RISCs vs CISCs? Arquitectura de Computadoras ISA- 73

74 Bhandarkar and Clark, cont. RISC factor Instr Risc Factor = CPI vax CPI Instr vax mips mips Bechmark Inst. Ratio CPI MIPS CPI VAX Ratio RISC factor spice2g matrix nasa fpppp tomcatv dudoc espresso eqntott li geo. mean Arquitectura de Computadoras ISA- 74

75 Bhandarkar and Clark, cont. Compensation Factors Increase VAX CPI but decrease VAX instruction count Increase MIPS instruction count Example 1: Loads and stores vs. operand specifiers Example 2: Necessary complex operations, e.g. loop branches Factors favoring VAX Big immediate values Not-taken branches incur no delay Arquitectura de Computadoras ISA- 75

76 Bhandarkar and Clark, cont. Factors favoring MIPS Operand specifier decoding Number of registers Separating floating point unit Simple jumps and branches (lower latency) Fancy VAX instructions: Unnecessary functionality Instruction scheduling Translation buffer Branch displacement size Arquitectura de Computadoras ISA- 76

77 Homework Assignment 3 Make a review of the ISA for a specific processor Write a three page report explaining the following: 1. Kind of IS Architecture (RISC, CISC or other, 16-bit, 32- bit, 64-bit) 2. Classes of instructions (ALU, Memory Movement, Branches, etc.) 3. Addressing Modes (immediate, base+displacemente, indirect, etc.) 4. Displacements in branches and control flow instructions (call, ret) 5. Special instructions: system calls, traps, access to special purpose registers 6. Instructions formats Arquitectura de Computadoras ISA- 77

78 Hw3: : List of Processors 1 Claudia Méndez Garza Xscale o ARM 2 José Alberto Ramírez Uresti Opteron AMD 64 bits 3 Víctor Echeverría Ríos Texas Instruments TMS320DM64x o un DSP Due date: September 26th, Arquitectura de Computadoras ISA- 78

79 Láminas complementarias no expuestas en la clase que pueden servir de soporte Arquitectura de Computadoras ISA- 79

80 VAX-11 Introduced by DEC in 1977: VAX- 11/780 Upward compatible from PDP bit word and addresses Virtual memory is first-class 16 GPRs (r15 is PC, r14 is SP), CCs Extremely orthogonal, memorymemory Decode as byte stream Opcode: operation, number of operands & operand type Variable-length address specifiers Arquitectura de Computadoras ISA- 80

81 VAX-11, cont. Data types 8-, 16-, 32-, 64-, 128-bit integers F (32 bits), D (64), G (64), H (128) FP Character string (8-bits/char) Decimal (4-bits/digit) Numeric string (8-bits/digit) Addresing modes include Literal (6 bits) 8-, 16-, 32-bit immediates Register, register deferred 8-, 16-, 32-bit displacements 8-, 16-, 32-bit displacement deferred Indexed Autoincrement Autodecrement Autoincrement deferred Arquitectura de Computadoras ISA- 81

82 VAX-11, cont. Operations Data Transfers (including string move) Arithmetic and Logical (2 and 3 operands) Control (Branch, Jump, etc. )» AOBLEQ (Add one and Branch if Less than or EQual) Procedure (CALLs save state) Bit Manipulation Floating Poing (Add/Sub/Mult/Divide) POLYF -- Polynomial Evaluation System (Exception, VM) Other» CRC -- Cycle redundant chech» INSQUE -- Insert entry in queue Arquitectura de Computadoras ISA- 82

83 VAX-11, cont. PC+0 PC+1 8 bits New instruction: opcode calls for three operands Specifier 1: four bits + register VAX has too many modes & formats PC+6 PC+9 + four byte displacements Specifier 2 + two byte displacements Specifier 3: index Specifier 3: indexed mode Serial semantics limit parallel execution PC+15 + four byte displacement next instruction The big deal with RISC is not REDUCED number of instructions; it s few modes & formats to facilitate pipelining Arquitectura de Computadoras ISA- 83

84 DEC Alpha Introduced by DEC in 1992 Ability to emulate VAX instructions important Strongly influenced by Cray-1 64-bit architecture Load/Store -- only displacement addressing Standard datatypes No byte loads/stores Registers bit GPRs (r31 = 0) bit FPRs VAX and IEEE floating point Arquitectura de Computadoras ISA- 84

85 DEC Alpha, cont. Four fixed-length instruction formats Sub-formats for computation instructions 32-bit instructions Designed with multiple-issue in mind No delayed branches Precise exceptions not automatic PAL code Arquitectura de Computadoras ISA- 85

86 DEC Alpha Instructions Formats Memory Format OpCode src/dest base displacement 0 PC-Relative Format OpCode src displacement 0 PAL-call Format OpCode PAL argument Arquitectura de Computadoras ISA- 86

87 DEC ALPHA Instruction Instruction Formats,, cont. Three-Register Integer Format OpCode src1 src function dest 0 Eight-bit Immediate Integer Format OpCode src1 const 1 function dest 0 Eight-bit Immediate Integer Format OpCode src1 src2 function dest 0 Arquitectura de Computadoras ISA- 87

88 DEC Alpha Instruction Set Operate Instructions Integer Arithmetic Logical (AND, OR, conditional MOV) Byte-manipulation Floating-point arithmetic Miscellaneous (memory prefetching, trap and memory barriers Load/Store Instructions Load/Store Quadwords (64-bits) Load-Linked/Store Conditional (for MP synchronization) Arquitectura de Computadoras ISA- 88

89 DEC Alpha Instruction Set,, cont. Control/Branching Instruction Branch on condition (8 conditions) in integer register Branch on condition (6 conditions) in FP register Unconditional branches Calculated jumps Branch Hints Different hint/rule type of branch Supervision Instructions PAL code for needed task Arquitectura de Computadoras ISA- 89