Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications

Transcription

1 Technische Universität Berlin Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications eyed aeed Fazel von der Fakultät IV- Elektrotechnik und Informatik der Technischen Universität Berlin Institut für Energie- und Automatisierungstechnik Zur Erlangung des akademischen Grades eines Doktoringenieurs (Dr.-Ing.) genehmigte Dissertation Vorsitzender: Gutachter: Prof. Dr.-Ing. C. Boit Prof. Dr.-Ing.. Bernet Prof. Dr.-Ing. U. chäfer Prof. Dr.-Ing. M. Michel Tag der Einreichung:.7.7 Tag der Verteidigung: Berlin 7 D 83

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3 eyed aeed Fazel Investigation and Comparison of Multi-Level Converters for Medium Voltage Applications

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5 Preface I would like to express my sincere gratitude to my supervisor, Professor Dr.-Ing. teffen Bernet for his professional guidance, interesting discussion and encouragement throughout the period of this research. I would also like to thank my friends and colleagues in the Power Electronics Group of Berlin University. In particular, I would like to acknowledge Dietmar Krug and Kamran Jalili. The author wishes to acknowledge the financial support of Iran Ministry of cience, Research and Technology scholarship. Finally, my personal thanks are extended to my family and friends for their support. eyed aeed Fazel Berlin, July 7

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7 - i - TABLE OF CONTENT Glossary of ymbols and Acronyms... iv List of Figures... x List of Tables... xvii. Introduction.... Overview of Medium Voltage Converter Topologies..... tate of the Art in Medium Voltage Converters..... tate of the Art in Medium Voltage Power emiconductors Basic tructure and Function of Multi-Level Voltage ource Converter Topologies Two-Level Voltage ource Converter (L-VC) tructure of Two-Level Voltage ource Converter (L-VC) witch tates and Commutations ine-triangle Modulation Output Waveforms and pectrum Diode Clamped Voltage ource Converter (DC VC) tructure Three-Level Neutral Point Clamped Voltage ource Converter (3L- NPC VC) witch tates and Commutations ine-triangle Modulation Flying Capacitor Voltage ource Converter (FLC VC) Flying Capacitor Converter tructure Three-Level Flying Capacitor Voltage ource Converter (3L-FLC VC) witch tates and Commutations ine-triangle Modulation Four-Level Flying Capacitor Voltage ource Converter (4L-FLC VC) eries Connected H-Bridge Voltage ource Converter (CHB VC) ingle-phase Full-Bridge (H-Bridge) Topology Circuit Configuration witch tates and Commutations ine-triangle Modulation Three-Phase Two-Level H-Bridge (L-H-Bridge) Topology Circuit Configuration witch tates and Commutations ine-triangle Modulation

8 - ii Introduction to the eries Connected Two-Level H-Bridge Voltage ource Converter (CLHB VC) eries Connected Two-Level H-Bridge Voltage ource Converter with Two Power Cells per Phase Leg (5L-CLHB VC) Circuit Configuration witch tates and Commutations ine-triangle Modulation eries Connected Two-Level H-Bridge Voltage ource Converter with Three Power Cells per Phase Leg (7L-CLHB VC) Circuit Configuration witch tates and Commutations ine-triangle Modulation eries Connected Two-Level H-Bridge Voltage ource Converter with Four Power Cells per Phase Leg (9L-CLHB VC) N-Level eries Connected Three-Level H-Bridge Voltage ource Converter (NL- C3LHB VC) Circuit Configuration of Five-Level eries Connected 3-Level H- Bridge Voltage ource Converter (5L-C3LHB VC) witch tates and Commutations ine-triangle Modulation Conclusion Modelling and imulation Load and Grid Models Load Model Grid Model Converter Model Inverter Modulation Method Compact Power emiconductor Model 4... Power emiconductor Losses Loss Approximation based on Datasheets Description of the Loss imulation Model Agreement Calculation Measurement DC Link Capacitor Models Capacitor Aluminium Electrolytic Capacitors Film Capacitors Rectifier Model Isolation Transformer Modelling and imulation Transformer Model Transformer Winding Model MATLAB/PELEC Implementation

9 - iii Medium Voltage Converter Application Three-Level Neutral Point Clamped Voltage ource Converter imulation Results Nine-Level eries Connected H-Bridge Voltage ource Converter imulation Results Design Criteria and Converter Data Design Criteria 5... Power emiconductor Devices DC Link Capacitor 5... DC Link Voltage Ripples DC Link Capacitor tored Energy Design of the Flying Capacitors 5.. Definition of the Converter Data Power emiconductor Devices witching Frequency DC Link Voltage Rectifier General Data for the elective Medium Voltage Converter Converter Comparison Comparison of Power emiconductor Utilization and Loss Distribution Comparison at Constant Installed witch Power and Constant Carrier Frequency Comparison of Maximum Carrier Frequency at Constant Installed witch Power and Constant Apparent Converter Output Power Comparison of Converter Power and Loss Distribution at for Constant Installed witch Power and Constant Frequency of the First Carrier Band Comparison of 4.6kV, 4.3MVA Multi-Level Converters at Constant Efficiency Comparison of Power emiconductor Utilization and Power Loss Distribution for.3kv-6kv Multi-Level Converters (3L-NPC VC and CLHB VCs) Comparison of the DC Link Capacitor for a 4-pulse, 4.6kV, 4.3MVA, 3L-NPC VC and 9L-CLHB VC Conclusion and Discussion 43 Appendix A.. 47 Bibliography

10 - iv - GLOARY OF YMBOL AND ACRONYM Variable Meaning a, b, c AC terminals of the converter A on,x On state resistance for device x A sw,off,x, B sw,off,x Turn-off curve-fitting constants for device x A sw,on,x, B sw,on,x Turn-on curve-fitting constants for device x B con,x Curve-fitted constant for device x C jx Flying capacitor (j =,.., N-), (x = a, b, c) C min,npc Minimum size of the dc link capacitance for NPC converter C min,chb Minimum size of the dc link capacitance for CHB converter C x DC link capacitance (x =,.., N-) cosϕ Load power factor D jkx, D H-bridge diodes (j =,,... p), (k = L, R), (x = a, b, c) jkx D jx NPC diodes (j =,.., N-), (x = a, b, c) D jx,d eries connected three-level H-bridge NPC diodes (j =, ), (x = a, b, i jxi c), (i =, ) D Tjkx,D 3L-H-Bridge freewheeling diodes (j =,,... p), (k =, ), (x = a, b, c), i Tjkxi (i =, ), D Tjx, D freewheeling diodes (x = a, b, c), (j =,.., N-) Tjx E C tored energy in the dc link capacitor E on, E off, E rec Turn-on, turn-off energy in IGBT and recovery energy in diode E sw,x witching energy loss for device x e x Load electromotive force (x = a, b, c) f Fundamental output frequency f C Carrier frequency f C,max Maximum carrier frequency f Cb Frequency of the first harmonics carrier band f h Frequency of harmonics order f o Converter output frequency f rec Rectifier output frequency f tri Frequency of triangle carrier signal g H-bridge negative dc rail g s Gate signal h Ordinal number of harmonic i(t) Instantaneous value of current I sx Transformer secondary windings current referred to the primary side (x =,.., 4) I C Collector current I C,n Collector current in IGBT I F,n Forward current in diode I h Amplitude of the harmonic current I ph,max Maximum value of the output phase current I ph,rms, Effective value of the output phase current Î ph,rms, Peak value of the output phase current I px Transformer primary winding current (x =, ) I sx Transformer secondary winding current (x =,, 3, 4) i C Rating capacitor current

11 - v - i C,j DC link capacitor current (j =,.., N-) i C,rip Effective ripple current in the capacitor i C,rms Effective current of flying capacitor cells i Cj,x Flying capacitor current (j =,,..), (x = a, b, c), i dc,j Current at any node of the capacitor bank (j =,.., N-) i dcjx Capacitor current at each H-bridge (j =,,... p), (x = a, b, c) i Lx Load current (x = a, b, c) i o Transformer no-load primary current î Peak value of the phase current ph i ph Output phase current i ph,a a-phase current i sx Utility grid phase current (x = A, B, C) k, k, k Transformer turn ratio between secondary windings L Transformer primary inductance L ER Equivalent series inductance L L Load inductance L m Transformer magnetization inductance L my, L md Transformer equivalent inductance with star and delta connections L s Utility grid inductance L xjy, L xjd Transformer primary leakage inductance (x = U, V, W), (j =, ) L xjy, L xjd Transformer secondary leakage inductance (x = U, V, W), (j =,, 3, 4) M, M j Converter midpoint (j =,.., N-) N Number of level voltage per phase leg m a Amplitude modulation ratio m f Frequency modulation ratio n Load star point n Converter star point n Number of primary turn winding n jx Number of secondary turn windings (j =, ), (x = Y, D) n c Number of series capacitors n C Number of series connected flying capacitor cells n jyd Transformer secondary windings turn ratio between delta and star connections (j =, ) n sw Number of switch states n T, n D Number of semiconductors and diodes in the converter n tr Transformer open circuit turns ratio P C Converter output active power P con,x Conduction losses in device x P cond Conduction losses of diodes P cont Conduction losses of IGBT P loss Power dissipation loss P loss,d Power dissipation loss in a freewheeling diode P loss,t Power dissipation loss in an IGBT P offd Turn-off losses of diode P offt Turn-off losses of IGBT P ont Turn-on losses of IGBT P sw,x Average switching loss in device x p Number of single-phase H-bridge cell per phase leg ph Number of phase Transformer primary resistance R

12 - vi - R jd Transformer primary winding resistance (j =, ) R jx Transformer secondary winding resistance (j =, ), (x = Y, D) R EPR Bypass resistance R ER Equivalent series resistance R L Load resistance R m Transformer magnetization resistance R s Utility grid resistance R T Transformer resistance R th Thermal resistances R th,ch Thermal resistances from junction to case R th,ch,t, R th,ch,d Thermal resistances of the IGBT and diode from junction to case R th,ha Thermal resistances from heat sink to ambient R th,jc Thermal resistances from case to heat sink R th,jc,t, R th,jc,d Thermal resistances case to heat sink of IGBT and diode C Converter three-phase apparent power C,max Maximum apparent converter output power CR Relative apparent converter output power in Inner switches jkx, Two-level H-bridge switches (i =,...p), (k = L, R), (x = a, b, c), jx, jkxi jx jkx jkxi Three-level H-bridge switches (j =,...p), (k =, ), (x = a, b, c), (i =, ) witches (j =,.., N-), (x = a, b, c) kx, kx eries connected H-bridge switches (k = L, R), (x = a, b, c) N Transformer apparent rated power out Outer switches Installed switch power R Relative installed switch power T Fundamental period T a Ambient temperature tanδ Dissipation factor of capacitor T C Period of carrier frequency T h Heat sink temperature T j, T j(x) Junction temperature (x = T, D) T j,max Maximum junction temperature T j,sp pecified junction temperature T jkx, T jkx Two-level H-bridge transistor (j =,...p), (k = L, R), (x = a, b, c) T jkx,t Three-level H-bridge transistors (j =,...p), (k =, ), (x = a, b, c), (i = i jkxi, ) T jx, T jx Transistors (j =,.., N-), (x = a, b, c) T kx, T kx, T k, T k H-bridge transistor (k = L, R), (x = a, b, c) t Time U ab, U bc, U ca pecific line-to-line voltages U ax, U n x pecific output leg voltages (x = g, M ) U C Capacitor operating voltage Collector-emitter voltage U CE U CE,n On-state saturation voltage in IGBT U Cjx Flying capacitor voltage (j =, ), (x = a, b, c) U com Commutation voltage

13 - vii - U com@fit Commutation voltage for a device reliability of FIT U con, U con,x Reference voltage per phase (x = a, b, c) Û con, Peak value of the desired fundamental component of the reference voltage U Cx DC link capacitor voltage (x =,,...) DC link voltage for L-VC, 3L-VCs, and 4L-FLC VC,3L-HB DC link voltage of one H-bridge in C3LHB VC,HB DC link voltage of one H-bridge in CLHB VC,min Minimum dc link voltage,n Nominal dc link voltage,tv Total virtual dc link voltage for CLHBVCs, and C3LHBVCs jx H-bridge dc link voltage (j =,.., p), (x = a, b, c) U F,n On-state voltage in diode U jxn H-bridge output voltage (j =,.., p), (x = a, b, c) U jxn pecific line-to-ground x-phase voltage for H-bridge (j =,.., p) U k Transformer short-circuit voltage U ky, U kd Transformer short-circuit voltage between primary and secondary windings U kyd Transformer short-circuit voltage between secondary star and delta windings U ll,rms, Effective value of line-to-line output voltage U nm pecific common-mode voltage U o,x Threshold voltage in device x U RRM Rated repetitive peak reverse voltage of diodes U sx Utility grid phase voltage (x = A, B, C) Û tri Peak value of triangular wave U tri,cell,j, U tri,kj Amplitude of triangle carrier signal (j =,, ), (k = L, R) U tri,u tri,j,u tri,j,x U tri,i Amplitude of triangle carrier signal (j = up, low), (x = a, b), (i =, ) U x x-phase line-to-ground voltage (x = a, b, c) U xm pecific phase-midpoint output voltage (x = a, b, c) U xn pecific line-to-neutral voltages (x = a, b, c) U xn pecific H-bridge output voltage (x = a, b, c) V g,v Tj g,v T j g,v Tj,x g, Tj,x V,V,V,V Gate signals (j =,, ), (x = a, b, c), (k = L, R), (i =, ) gtk,x gtk,x gtj,xi gtj,xi X j Transformer primary voltage (X = U, V, W), (j =, ) X jk Transformer secondary voltage (X = U, V, W), (j =,, 3, 4), (k = Y, D) X N Transformer primary rated voltage (X = U, V, W) X NY, X ND Transformer primary no-load voltages with star and delta connections (X = U, V, W) X NY, X ND Transformer secondary no-load voltages with star and delta connections (X = U, V, W) X Nj Transformer secondary rated voltages (X = U, V, W), (j =,, 3, 4) X T Transformer reactance Z jx Transformer secondary winding impedance (j =, ), (x = Y, D) Z Primary equal impedance of 4-pulse transformer Z, Z Primary equal impedance of each -pulse transformer Z Yo Transformer primary winding no-load impedance Z jd Transformer primary winding impedance with delta connection (j =, ) Z j Transformer secondary equal impedance (j =, ) Z jx Transformer secondary winding impedance (j =, ), (x = Y, D) Z kj Transformer equivalent short-circuit impedance (j =,... 4)

14 - viii - Z NY Z T α α p U C U C,max φ ω η Transformer primary winding rated impedance Transformer impedance Transformer phase displacement between primary and secondary Transformer phase displacement DC link capacitor voltage ripples Maximum dc link capacitor voltage ripples Load current angle Fundamental angular frequency Efficiency

15 - ix - Acronyms and Abbreviations Acronym/Name Meaning ANI American National tandard BJT Bipolar Junction Transistor CD Carrier Disposition Modulation CC Current ource Converter CI Current ource Inverter D Diode DC VC Diode Clamped Voltage ource Converter Dd Delta-delta Configuration Dy Delta-star Configuration Dzz Delta-zigzag-zigzag Configuration EMF Electromotive force EMI Electromagnetic Interference FIT One failure in 9 operation hours FLC Flying Capacitor GCT Gate-commutated Thyristor GTO Gate Turn-Off Thyristor H Hybrid Modulation HV-IGBT High Voltage Insulated Gate Bipolar Transistor IEEE Institute of Electrical and Electronics Engineers IGBT Insulated Gate Bipolar Transistor IGCT Integrated Gate Commutated Thyristor LV-IGBT Low Voltage Insulated Gate Bipolar Transistor MCT MO-controlled Thyristor ML Multi-Level MLC Multi-Level Converter MOFET Metal Oxide emiconductor Field Effect Transistor MPC Multiple Point Clamped MTO MO Turn-Off Thyristor MV Medium Voltage MVD Medium Voltage Drive N Number of Voltage Level NEMA National Electrical Manufacturers Association NPC Neutral Point Clamped OP Operating Point PD Phase Disposition POD Phase Opposition Disposition P Phase hifted Modulation PWM Pulse-Width-Modulated CLHB eries Connected Two-Level H-Bridge C3LHB eries Connected Three-Level H-Bridge CHB eries Connected H-Bridge VM pace Vector Modulation T Transistor THD Total Harmonic Distortion VC Voltage ource Converter VI Voltage ource Inverter WTHD Weighted Total Harmonic Distortion Zdy Zigzag-delta-star Configuration

16 - x - List of Figures Figure -: Application ranges of commercially available power semiconductors Figure -: IGBT-based inverter fed medium voltage drives: (a) 3L-NPC, (b) CHB Figure -3: Classification of state-of-the-art power semiconductors Figure -4: Power range of commercially available power semiconductors Figure -5: Application ranges of IGBTs and IGCTs Figure 3-: Two-Level Voltage ource Configuration Figure 3-: witch states: (a) conduction paths, (b) commutations and switching losses for each phase of the L-VC Figure 3-3: Voltage waveforms of the L-VC: (a) control signals U con, x and triangular signal U tri, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-toline output voltage, (e) common mode voltage Figure 3-4: Harmonic spectrum of the L-VC: (a) phase-midpoint output voltage, (b) line-toline output voltage Figure 3-5: One-phase N-Level Neutral Point Clamped Converter Figure 3-6: Three-phase Three-Level Neutral Point Clamped Converter Figure 3-7: Conduction path of the Three-Level Neutral Point Clamped Converter Figure 3-8: Commutations and switching losses in the 3L-NPC VC: (a) and (b) for positive load current, (c) and (d) for negative load current Figure 3-9: Voltage waveforms of the 3L-NPC VC: (a) control signals U con, x and triangular signals U tri,up and U tri,low, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-to-line output voltage, (e) common mode voltage Figure 3-: Harmonic spectrum of the 3L-NPC VC: (a) phase-neutral point output voltage, (b) line-to-line output voltage Figure 3-: The generalized N-Level Flying Capacitor Converter Figure 3-: Three-phase Three-Level Flying Capacitor Converter Figure 3-3: Conduction path of the Three-Level Flying Capacitor Converter Figure 3-4: Commutations and switching losses in the 3L-FLC Converter (a-d) for positive load current, (e-h) for negative load current Figure 3-5: Voltage waveforms of the 3L-FLC VC: (a) control signals and triangular signals, (b) gating signals in phase a, (c) phase-midpoint output voltage, (d) line-to-line output voltage, (e) common mode voltage Figure 3-6: Harmonic spectrum of the 3L-FLC VC: (a) phase-neutral point output voltage, (b) line-to-line output voltage Figure 3-7: Three-phase Four-Level Flying Capacitor Converter Figure 3-8: Voltage waveforms of the 4L-FLC VC: (a) control signals and triangular signals, (b) phase-midpoint output voltage, (c) line-to-line output voltage, (d) common mode voltage Figure 3-9: Harmonic spectrum of the 4L-FLC VC: (a) phase-neutral point output voltage, (b) line-to-line output voltage

17 - xi - Figure 3-: Transitions between voltage levels for the Four-Level Flying Capacitor Figure 3-: Three-phase configuration for the N-Level H-Bridges VC Figure 3-: Typical power cell (H-bridge) converter Figure 3-3: Conduction path of the single-phase H-bridge cell: (a) positive, (b, c) zero, and (d) negative states Figure 3-4: Commutations and switching losses in the H-bridge cell: (a) and (b) for positive load current, (c) and (d) for negative load current Figure 3-5: Voltage waveforms of the H-bridge cell: (a) control signals U con and triangular signals U tri, and U tri,, (b) output voltage of leg a, (c) output voltage of leg n, (d) load voltage Figure 3-6: Harmonic spectrum of the H-bridge output voltage Figure 3-7: Three-phase configuration for the L-H-Bridges Voltage ource Converter Figure 3-8: Voltage waveforms of the three-phase L-H-Bridge cell: (a) control signals U con,x and triangular signals U tri, and U tri,, (b) gate signals, (c) output phase voltage, (d) output line-to-line voltage Figure 3-9: Harmonic spectrum of the three-phase L-H-Bridge cell: (a) phase output voltage, (b) line-to-line output voltage Figure 3-3: eries Connected Two-Level H-Bridge Voltage ource Converter with p series H- bridge cells per phase Figure 3-3: 5L-CLHB Voltage ource Converter Figure 3-3: Transitions between voltage levels for the 5L-CLHB V Figure 3-33: Conduction path of the 5L-CLHB VC Figure 3-34: Voltage waveforms of the 5L-CLHB VC: (a) control signals U con,x and triangular signals U tri,l, U tri,l, U tri,r and U tri,r, (b) gate signals, (c) output phaseto-ground voltage U an, (d) output line-to-line voltage U ab, (e) output load-phase voltage U an Figure 3-35: Harmonic spectrum of the 5L-CLHB VC Figure 3-36: Pulse width modulation for the 7L-CLHB VC: (a) control signals U con,a and triangular signals U tri,li and U tri,ri, (b) gate signals (m f = 3) Figure 3-37: Voltage waveforms of the 7L-CLHB VC: (a) reference and triangular signals, (b) output phase voltage U an, (c) output line-to-line voltage U ab, (d) output loadphase voltage U an (m f = 5) Figure 3-38: Harmonic spectrum of the phase voltage (a) and line-to-line voltage (b) of the 7L- CLHB VC Figure 3-39: The 9L-CLHB Voltage ource Converter Figure 3-4: Pulse width modulation for the 9L-CLHB VC: (a) control signals U con,a and triangular signals U tri,li and U tri,ri, (b) gate signals (m f = 3) Figure 3-4: Voltage waveforms of the 9L-CLHB VC: (a) reference and triangular signals, (b) output phase voltage U an, (c) output line-to-line voltage U ab, (d) output loadphase voltage U an (m f = 5) Figure 3-4: Harmonic spectrum of the phase voltage U an (a) and the line-to-line voltage U ab

18 - xii - (b) of the 9L-CLHB VC Figure 3-43: NL-C3LHB VC with p series 3L-H-Bridge cells per phase Figure 3-44: Five-level C3LHB diode clamped topology (5L-C3LHB) Figure 3-45: Voltage waveforms of the 5L-C3LHB VC: (a) control signal U con and triangular signals, (b) a -leg gate signals, (c) a -leg phase voltage, (d) a -leg gate signals, (e) a -leg phase voltage, (f) converter output voltage Figure 3-46: Harmonic spectrum of the 5L-C3LHB VC Figure 3-47: Number of total components required in the multi-level converter as a function of the number of phase voltage levels Figure 4-: Block diagram of Medium Voltage Drives: (a) NPC and FLC VCs, (b) CHB VC Figure 4-: tandard load model for one-phase and three-phase Figure 4-3: tandard three-phase utility grid model Figure 4-4: The ideal circuit symbol of the IGBT Figure 4-5: The steady state equivalent thermal circuit diagram: (a) general model, (b) Infineon model Figure 4-6: Characteristics of current sharing for two connected modules in parallel Figure 4-7: Approximation characteristics based on the curve-fitting method: (a) IGBT/Diode on-state characteristics, (b) IGBT turn-on and IGBT/Diode turn-off switching energy (FZ8R33KFC IGBT-module from Eupec, U CE = 8V, T j,max = 5 C) Figure 4-8: Equivalent circuit of a capacitor Figure 4-9: Circuit diagram of the standard six-pulse diode rectifier Figure 4-: Multi-pulse phase-shift transformer Figure 4-: 4-pulse phase-shift transformer models: (a) Zdy, (b) Dzz Figure 4-: Investigated zigzag coupling configurations: (a) Delta-zigzag-zigzag configuration (Dzz), (b) Zigzag-delta-star configuration (Zdy) used by the industry Figure 4-3: Windings position for positive (a), and negative (b) phase shift of Dzz configuration Figure 4-4: Windings position for positive (a), and negative (b) phase shift of Zdy configuration Figure 4-5: Equivalent electrical circuit of a linear 3-winding transformer Figure 4-6: The model of a -pulse transformer Figure 4-7: 4-Pulse-Diode-Rectifier with serial connections and Dzz configuration Figure 4-8: 4-Pulse-Diode-Rectifier with serial connections and Zdy configuration Figure 4-9: Utility grid current and its harmonic spectrum for the 4-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the -pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the -pulse transformer (e, f)

19 - xiii - Figure 4-: Primary and secondary winding currents of the 4-pulse transformer Figure 4-: DC link voltage and its harmonic spectrum (a, b), and dc link current and its harmonic spectrum, I dc = 7A, f C = 75Hz Figure 4-: 4-Pulse-Diode-Rectifier with independent connections: (a) Dzz configuration, and (b) Zdy configuration Figure 4-3: Utility grid current and its harmonic spectrum for the 4-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the -pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the -pulse transformer (e, f) Figure 4-4: Primary and secondary winding currents of the 4-pulse transformer Figure 4-5: DC link voltage and its harmonic spectrum, f C = 75Hz Figure 4-6: DC link current and its harmonic spectrum, I dc = 47A, f C = 75Hz Figure 5-: Iterative design approach to the power semiconductor design Figure 5-: Iterative design approach to calculate the maximum converter output power C,max and the semiconductor utilization (T j = T j,max, = const., f C = const.) Figure 5-3: Iterative design approach to calculate the maximum carrier frequency (T j = T j,max, = const., C = const.) Figure 5-4: Iterative design approach to calculate the converter output power and losses (T j = T j,max, = const., f Cb = const.) Figure 5-5: Iterative design approach to calculate the maximum carrier frequency (T j = T j,max, C = const., η = η ref const.) Figure 5-6: The dc link voltage ripple U C and the dc link stored energy E C as functions of the dc link capacitance for the 3L-NPC VC (U ll,rms, = 4.6kV, I ph,rms, = 6A, cos ϕ =.9, Udc = 68V) Figure 5-7: 4-pulse diode rectifier configurations (a) series configuration uses for the 3L-NPC VC, (b) separate configuration uses for the9l-chb VC Figure 5-8: Voltage and power ranges of the selective medium voltage drives (I ph,rms, = 6A), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-: Converter semiconductor losses and efficiencies as functions of the phase current for the investigated output voltage classes (f C = 45Hz, m a =.5, cosϕ =.9): (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, and (c) U ll,rms, = 4.6kV (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-: Converter semiconductor loss distribution at constant carrier frequency (f C = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A) (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, (c) U ll,rms, = 4.6kV (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-3: Harmonic spectrum of line-to-line output voltage at constant carrier frequency (f C = 45Hz, f o = 5Hz, m a =.5, f Cb,3L-NPC = 45Hz, f Cb,3L-FLC = 9Hz, f Cb,4L-FLC = 35Hz, f Cb,5L-CLHB = 8Hz, f Cb,7L-CLHB = 7Hz, f Cb,9L-CLHB = 36Hz) (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A:

20 - xiv - FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-4: Converter semiconductor losses and efficiencies as functions of the carrier frequency for the investigated output voltage classes: (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, and (c) U ll,rms, = 4.6kV (f C = 45Hz, I ph,rms, = 6A, m a =.5, cosϕ =.9) (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-5: Converter semiconductor loss distribution at maximum carrier frequency (f o = 5Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A, f C = 45Hz), (f C,3L-NPC = 45Hz, f C,3L- FLC,.3kV = 88Hz, f C,3L-FLC,3.3kV = 635Hz, f C,3L-FLC,4.6kV = 595Hz, f C,4L-FLC,.3kV = 5Hz, f C,4L-FLC,3.3kV = 79Hz, f C,4L-FLC,4.6kV = 85Hz, f C,5L-CLHB = 585Hz, f C,7L- CLHB = 3Hz, f C,9L-CLHB =345Hz) (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-6: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f Cb,3L-NPC = 45Hz, f Cb,3L-FLC,.3kV = 76Hz f Cb,4L-FLC,.3kV = 75Hz f Cb,5L-CLHB = 634Hz, f o = 5Hz, f C = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A) (3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-7: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f Cb,3L-NPC = 45Hz, f Cb,3L-FLC,3.3kV = 7Hz, f Cb,4L-FLC,3.3kV = 37Hz, f Cb,7L-CLHB = 78Hz, f o = 5Hz, f C = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A) (4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.7kV/6A: FZ6R7KE3) Figure 6-8: Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f Cb,3L-NPC = 45Hz, f Cb,3L-FLC,4.6kV = 9Hz, f Cb,4L-FLC,4.6kV = 55Hz, f Cb,9L-CLHB = 76Hz, f o = 5Hz, f C = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A) (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H,.7kV/6A: FZ6R7KE3) Figure 6-9: Converter semiconductor losses as functions of the phase current for the investigated output voltage classes: (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, and (c) U ll,rms, = 4.6kV (f C,3L-NPC = 45Hz, f C,3L-FLC = 5Hz, f C,4L-FLC = 5Hz, f C,5L- CLHB =.5Hz, f C,7L-CLHB = 75Hz, f C,9L-CLHB = 56.5Hz, f o = 5Hz, f Cb = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-: Converter semiconductor loss distribution at constant frequency of the first carrier band (f C = f Cb = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A): (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, (c) U ll,rms, = 4.6kV (f C,3L-NPC = 45Hz, f C,3L-FLC = 5Hz, f C,4L-FLC = 5Hz, f C,5L-CLHB =.5Hz, f C,7L-CLHB = 75Hz, f C,9L-CLHB = 56.5Hz, f o = 5Hz, f Cb = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-: Harmonic spectrum of line-to-line voltage at constant frequency of the first carrier band (f C,3L-NPC = 45Hz, f C,3L-FLC = 5Hz, f C,4L-FLC = 5Hz, f C,5L-CLHB =.5Hz, f C,7L-CLHB = 75Hz, f C,9L-CLHB = 56.5Hz, f o = 5Hz, f Cb = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A), (6.5kV/6A: FZ6R65KF, 4.5kV/6A:

21 - xv - CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-: Average junction temperature of IGBTs and diodes (,n = 68V, m a =.5, cosϕ =, T h = 8 C) (a) 3L-NPC VC (Eupec 6.5kV/74.4A IGBT, I ph,max = 6A, C = 4.3MVA, f C = 45Hz) (b) 3L-FLC VC (Eupec 6.5kV/863.4A IGBT, I ph,max = 99A, C = 6.6MVA, f C = 5Hz) (c) 4L-FLC VC (Mitsubishi 4.5kV/83A IGBT, I ph,max = 6A, C = 7.64MVA, f C = 5Hz) (d) 9L-CHB VC (Eupec.7kV/85.8A IGBT, I ph,max = 89A, C = 6.4MVA, f C = 56.5Hz) Figure 6-3: Loss distribution (a), efficiency (b), and relative installed switch power (c), ( c = 4.3MVA, I ph,rms, = 6A, f o = 5Hz, m a =.5, cos ϕ =.9, T jmax = 5 C, f C,3L- NPC-6.5kV = 45Hz, f C,3L-NPC-3.3kV = 5Hz, f C,3L-FLC-6.5kV = 475Hz, f C,3L-FLC-3.3kV = 65Hz, f C,4L-FLC-4.5kV = 6Hz, f C,9LCLHB-.7kV = 5Hz), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-4: Flying capacitor current (a) and voltage ripple (b) of a 3L-FLC VC as functions of the modulation index and phase shift (I ph,rms, = 6A, f C,3L-FLC = Hz, C = 77µF) Figure 6-5: Flying capacitor current (a) and voltage ripple (b) of a 4L-FLC VC as functions of the modulation index and phase shift (I ph,rms, = 6A, f C,4L-FLC = Hz, C, = 58µF) Figure 6-6: Harmonic spectrum of line-to-line voltage at constant efficiency (I ph,rms, = 6A, f o = 5Hz, m a =.5, cos ϕ =.9, T jmax = 5 C, f C,3L-NPC-6.5kV = 45Hz, f C,3L-NPC- 3.3kV = 5Hz, f C,3L-FLC-6.5kV = 475Hz, f C,3L-FLC-3.3kV = 65Hz, f C,4L-FLC-4.5kV = 6Hz, f C,9LCLHB-.7kV = 5Hz) Figure 6-7: emiconductor loss distribution and relative installed switch power occurring at line-to-line output voltages of.3kv, 3.3kV, 4.6kV, and 6kV at different switching frequencies of 45Hz, 75Hz, and 5Hz (I ph,rms, = 6A, f o = 5Hz, m a =.5, cos ϕ =.9, T jmax = 5 C), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6-8: The effective, average, and ripple capacitor current as a function of the modulation index and load angle in the 3L-NPC VC according to Figure 3-6: (a-c) (i dc,eff,max /i ph,peak = 85.6% at φ = ±8, and m a =.5), (i dc,avg,max /i ph,peak = 8.3% at φ = and m a =.5), (i dc,rip,max /i ph,peak = 45.8% at φ = ±8, and m a =.6), and in the 9L-CLHB VC according to Figure 3-39 (df).(i dc,eff,max /i ph,peak = 68.7% at φ = ±8, and m a =.5), (i dc,avg,max /i ph,peak = 57.5% at φ = and m a =.5), (i dc,rip,max /i ph,peak = 54.3% at φ = ±9, and m a =.5), (i ph,rms, = 6A, f C = 75Hz, f o = 5Hz) Figure 6-9: (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VC, (c, d): transformer primary phase currents of the -pulse transformer and their harmonic spectra in the 3L-NPC VC, (e, f): transformer secondary phase currents of the -pulse transformer and their harmonic spectra in the 3L-NPC VC (E = 6J/kVA, C = C =.77mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-: (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VC, (c, d): transformer primary phase currents of the -pulse transformer and their

22 - xvi - harmonic spectra in the 3L-NPC VC, (e, f): transformer secondary phase currents of the -pulse transformer and their harmonic spectra in the 3L-NPC VC (E = J/kVA, C = C = 5.54mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-: (a, b): Utility grid phase current and its harmonic spectra in the 9L-CLHB VC, (c, d): transformer primary phase currents of the -pulse transformer and their harmonic spectra in the 9L-CLHB VC, (e, f): transformer secondary phase currents of the -pulse transformer and their harmonic spectra in the 9L-CLHB VC (E = J/kVA, C = C = 4.8mF, f C = 75Hz, f o = 5Hz, m a =.5, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-: (a, b): Utility grid phase current and its harmonic spectra in the 9L-CLHB VC, (c, d): transformer primary phase currents of the -pulse transformer and their harmonic spectra in the 9L-CLHB VC, (e, f): transformer secondary phase currents of the -pulse transformer and their harmonic spectra in the 9L-CLHB VC (E = 34J/kVA, C = C = 44mF, f C = 75Hz, f o = 5Hz, m a =.5, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-3: (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VC, (c, d): dc link current and its harmonic spectra, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VC (E = 6J/kVA, C = C =.77mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-4: (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VC, (c, d): dc link current and its harmonic spectra in the 3L-NPC VC, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VC (E = J/kVA, C = C = 5.54mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-5: (a, b): DC link voltage ripple and its harmonic spectra in the 9L-CLHB VC, (c, d): dc link current and its harmonic spectra in the 9L-CLHB VC, (e, f): phase output voltage and its harmonic spectra in the 9L-CLHB VC (E = J/kVA, C = C = 4.8mF, f C = 75Hz, f o = 5Hz, m a =.5, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-6: (a, b): DC link voltage ripple and its harmonic spectra in the 9L-CLHB VC, (c, d): dc link current and its harmonic spectra in the 9L-CLHB VC, (e, f): phase output voltage and its harmonic spectra in the 9L-CLHB VC (E = 34J/kVA, C = C = 44mF, f C = 75Hz, f o = 5Hz, m a =.5, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-7: (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VC (E = 6J/kVA, C = C =.77mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9) Figure 6-8: (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VC (E = J/kVA, C = C = 5.54mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

23 - xvii - List of Tables Table -: Overview of available industrial medium voltage drives on the market Table -: Device rating and package types of typical MV power semiconductors Table 3-: witch positions for each phase of the two-level VC Table 3-: Conduction losses in the two-level VC Table 3-3: witching losses in the two-level VC Table 3-4: witch positions for one phase of the three-level NPC VC Table 3-5: Conduction losses in the 3L-NPC VC Table 3-6: witching losses in the 3L-NPC VC Table 3-7: witch positions for one phase of the three-level FLC VC Table 3-8: Conduction losses in the three -level FLC VC Table 3-9: witching losses in the three-level FLC VC Table 3-: witch positions for the one phase of the four-level FLC VC Table 3-: witch positions for single-phase H-bridge cell Table 3-: Conduction losses in the single-phase full-bridge converter Table 3-3: witching losses in the single-phase full-bridge converter Table 3-4: Quantities comparison of the CLHB VC Table 3-5: witch positions for the 5L-CLHB VC Table 3-6: The output voltage levels of the 5L-CLHB VC Table 3-7: Number of redundancies in each phase voltage level of the 7L-CLHB VC Table 3-8: The output voltages and their corresponding levels of the 7L-CLHB VC Table 3-9: The output voltages and their corresponding levels of the 9L-CLHB VC Table 3-: witch positions for the 3L-H-Bridge converter Table 3-: Conduction losses in the 3L-H-Bridge converter Table 3-: witching losses in the 3L-H-Bridge converter Table 3-3: Comparison of power component requirements for multi-level topologies Table 4-: Fitting parameters and thermal resistances of medium voltage IGBTs/Diodes Table 4-: Thermal resistance of the IGBT module: FZ6R65KF Table 4-3: Harmonic current and their phase angles in 4-pulse transformers Table 4-4: The necessary input data of the -pulse phase-shift transformer Table 4-5: The secondary quantity parameters for the 4-pulse transformer with Zdy connection Table 4-6: The designing parameters for the 4-pulse transformer with Zdy connection Table 5-: Critical operating points for the determination of the power semiconductor current ratings (stationary thermal design) for all considered topologies Table 5-: Converter data (Output phase current I ph,rms, = 6A)

24 - xviii - Table 5-3: Power semiconductor devices Table 5-4: The converter specifications for medium voltage converters Table 6-: Power semiconductor design for I ph,rms, = 6A, f C = 45Hz / Hz Table 6-: Maximum phase current and apparent converter output power for constant carrier frequency (I ph,rms, = 6A, m a =.5, cosϕ =.9) Table 6-3: Maximum carrier frequency for constant apparent converter output power and constant installed switch power (I ph,rms, = 6A, m a =.5, cosϕ =.9) Table 6-4: Maximum phase current and apparent converter output power for constant carrier frequency of the first carrier band and installed switch power (I ph,rms, = 6A, f Cb = 45Hz / Hz, m a =.5, cosϕ =.9) Table 6-5: Converter voltage and semiconductor specifications for a constant converter power and carrier frequency (U ll,rms, = 4.6kV, I ph,rms, = 6A, C = 4.3MVA, f C = 45Hz, T j,max = 5 C) Table 6-6: Carrier and harmonic carrier band frequencies, capacity of flying capacitors and installed switch power for a converter efficiency of about 99% (U ll,rms, = 4.6kV, I ph,rms, = 6A, C = 4.3MVA) Table 6-7: Power semiconductor design (I ph,rms, = 6A, m a =.5, cos ϕ =.9)

25 . INTRODUCTION The development of new high power semiconductors such as 3.3kV, 4.5kV, and 6.5kV Insulated Gate Bipolar Transistors (IGBTs), and 4.5kV to 5.5kV Integrated Gate Commutated Thyristors (IGCTs), and improved converter designs have led to a drastic increase of the market share of Pulse-Width-Modulated (PWM) controlled Voltage ource Converters (VC) []. Despite a price reduction of Gate Turn-Off Thyristors (GTOs) by a factor of two to three over the last five years, also conventional GTO Voltage ource Converters and Current ource Converters (CC) are increasingly replaced by PWM Voltage ource Converters with IGCTs or IGBTs in traction and industry applications []. Today the two-level Voltage ource Converter (L-VC) applying IGBTs is clearly the dominating converter topology in traction applications (low, medium, and high power propulsion) and the three-level Neutral Point Clamped Voltage ource Converter (3L-NPC VC) is mostly applied in industrial medium voltage converters. The L-VC and the 3L-NPC VC offer technical advantages like a simple power part, a low component count, and straightforward protection and modulation schemes. On the other hand, the hard-switching transients of the power semiconductors at high commutation voltage cause high switching losses and a poor harmonic spectrum which produces additional losses in the machine. Further problems are created by over-voltages in cables and machines as well as bearing currents due to the steep-switching transients [5], [], []. Multi-level converters (MLCs) have been receiving attention in the recent years and have been proposed as the best choice in a wide variety of medium voltage (MV) applications [47]. They enable a commutation at substantially reduced voltages and an improved harmonic spectrum without a series connection of devices, which is the main advantage of a multi-level structure. Other advantages of these topologies are better output voltage quality, reduced electromagnetic interference (EMI) problems, and lower overall losses in some cases. However, today they have a limited commercial impact due to their disadvantages such as high control complexity and increased power semiconductor count compared to the L-VC and the 3L-NPC VC. There is a large variety of power semiconductors (e.g. IGBTs, GTOs, IGCTs) and converter topologies (e.g. L-VC, 3L-NPC VC, 3L-FLC VC, 4L-FLC VC, and CHB VCs). However, today there is no comparative analysis of the different converter topologies. Therefore, the objective of this thesis is a detailed comparison of state-of-the-art L-VC, 3L- NPC VC, and different multi-level VCs (e.g. 3L-FLC VC, 4L-FLC VC, 5L-, 7L-, and 9L- CLHB VCs) for medium voltage converters. On the basis of the application requirements, different ML converter structures are designed, simulated, and evaluated. The development of design tools based on state-of-the-art converters and semiconductors, which enable the dimensioning of power semiconductors, dc link capacitors, and transformers; are one major part of this thesis. Finally, the amount of active and passive components, the modulation, losses, and efficiency of aforementioned converters are calculated and compared. The thesis is arranged in seven main chapters: This introduction is followed by an overview of medium voltage converter topologies, including medium voltage power semiconductors and modulations in chapter.

26 INTRODUCTION Chapter 3 presents the basic structure and function of voltage source converter topologies. Based on the requirements for MV applications, advantages and disadvantages of the topologies are discussed. One of the main parts of this thesis is the modelling and simulation of the different multi-level converters. The dimensioning and design of power semiconductors, dc link capacitors, and isolation transformers are developed in chapter 4. The basic converter data for a converter comparison, including the IGBTs, modulation, switching frequency, and state of the art are described in chapter 5. The comparison of the different converter topologies is performed in chapter 6 for 3L-NPC VC, 3L-FLC VC, 4L-FLC VC, and 5L-, 7L-, 9L-, and L-CHB VCs on the basis of the state-of-the-art.7kv,.5kv, 3.3kV, 4.5kV, and 6.5kV IGBTs for.3kv, 3.3kV, 4.6kV, and 6kV medium voltage converters. As a result, the converter losses, the semiconductor loss distribution, the converter efficiency, harmonic spectrum analysis, and the installed switch power of the different converter topologies are compared in this chapter. Finally, the conclusion and discussion are presented in chapter 7.

27 . OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIE.. tate of the Art in Medium Voltage Converters Multi-level voltage source converters have been studied intensively for high-power applications [44], [53], [87], [88]. tandard drives for medium voltage industrial applications have become available since the mid-98s [7], [8], [83], [9]. These converters synthesize higher output voltage levels with a better harmonic spectrum and less motor winding insulation stress. However, the reliability and efficiency of the converter are reduced due to an increasing number of devices. Today there is a large variety of converter topologies for Medium Voltage Drives (MVD). For low and medium power industrial applications (e.g. = 3kVA - 3MVA) the majority of the drive manufacturers offer different topologies of Voltage ource Converters: Two-Level Voltage ource Converters (L-VC) (e.g. Alstom), Three-Level Neutral Point Clamped Voltage ource Converters (3L-NPC VC) (e.g. ABB, Alstom, iemens), Four-Level Flying Capacitor Voltage ource Converters (4L-FLC VC) (e.g. Alstom: YMPHONY [8]) and eries Connected H-Bridge Voltage ource Converters (CHB VC) (Robicon [8], [39]). One manufacturer (Allen Bradley) still offers self-commutated current source inverters (CI). While 4.5kV, 6kV and 6.5kV IGCTs are mainly used in 3L-NPC VCs and CIs respectively;.5kv, 3.3kV, 4.5kV and 6.5kV High Voltage IGBTs (HV-IGBTs) are applied in L-VCs, 3L- NPC VCs and 4L-FLC VCs. In contrast,.kv and.7kv Low Voltage IGBTs (LV-IGBTs) are usually applied in CHB VCs [94]. Among the high-power multi-level converters, three topologies have been successfully implemented as standard products for medium voltage industrial drives: the Three-Level Neutral Point Clamped Voltage ource Converter (3L-NPC VC) [8], [83], the Four-Level Flying Capacitor Voltage ource Converters (4L-FLC VC) [8], and the eries Connected H- Bridge Voltage ource Converters (CHB VC) [7], [9]. In medium voltage applications, the 3L-NPC topology has been accepted by several large manufacturers. ABB is using this topology in both their AC [83] and AC 6 series, in a voltage and power range of.3kv-4.6kv and 35kVA-7MVA [54]. iemens IMOVERT MV [55] is also utilising this topology with output voltages from.3kv to 6.6kV and a power range from 66kVA to 9MVA. Not only European but also Asian vendors, such as Mitsubishi, employ the 3L-NPC converter [48]. The NPC topology uses high-voltage blocking devices with a relatively low switching frequency capability. This topology has a simple circuit but it needs a large inductivecapacitive (LC) output filter to operate standard motors. The 4L-FLC VC is attractive if a very high switching frequency, a low harmonic distortion, and a small output filter or a high output voltage is required [5]. The CHB topology uses low-voltage blocking devices (e.g. 7V IGBTs) with a high switching frequency capability. It typically consists of three to six equal H-bridge cells per phase, which results in a seven- to thirteen-level output voltage waveform. An input isolation transformer feeds each of the H-bridges via its own three-phase winding and full-bridge diode-

28 4 OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIE rectifier. To obtain a high pulse number at the primary side, secondary transformer windings in star, delta, zigzag, and combinations are used. This topology has excellent utility grid current and output voltage waveforms. However, the cost of the complex input transformer and the high number of semiconductor devices with their control equipment are its drawbacks. The disadvantages of both topologies can be limited by using a hybrid asymmetric multi-level converter which is constructed by combining the CHB with the NPC topologies [33], [34]. This combination produces more output voltage levels with the same number of components than a symmetric multi-level converter. The first H-bridge cells of each phase in the CHB topology are replaced by a leg of the NPC converter. Although an H-bridge cell and a leg of the NPC converter provide the same output voltage level, the hybrid asymmetric multi-level topology requires a smaller number of separate dc sources and H-bridge cells for the same output voltage levels [85], [86]. This leads to a further simplification of the feeding transformer and rectifiers [84]. This topology can be operated with a low or high switching frequency for high- or low-voltage applications. However, the need for a complex input transformer remains and its control would be complicated due to its structure, so that it is not commercially offered on the market. Table - summarizes the available industrial medium voltage drive applications offered by drive manufactures [8]. The voltage source converter topology applying IGBTs and IGCTs are offered by the majority of manufactures. The medium voltage drives cover power ratings from.mw to 4MW at the medium voltage level of.3kv to 3.8kV [9], [8]. These drives are used in various applications such as traction [], electric power, and other industries [35]. The medium voltage traction converters are mostly fed by a single-phase ac line using a lowfrequency transformer (e.g. 5kV 6 Hz or 5kV 5Hz) [], [38], [39]. The feeding of 3 some traction converters by dc mains is also possible, but due to the large variations of the dc voltages of -3% to +4%, such applications are complicated []. Figure - represents the most important power converters on the market and their rated voltages and powers today [4], [8]. Table - Overview of available industrial medium voltage drives on the market [8], [75] Manufacturer (MVA) (kv) Power Voltage Type Topology emiconductor Robicon Perfect Harmony ML-CHB-VC LV IGBT Allen.3, 3.3, Power Flex Bradley 4.6, 6.6 CI IGCT.3, 3.3, iemens Masterdrive MV , 6, 3L-NPC-VC HV IGBT 6.6 Masterdrive ML L-NPC-VC IGCT AC.3-5.3, 3.3, 4 3L-NPC-VC IGCT ABB AC , 6.6, 6.9 ML-CHB-VC IGCT AC , 3.3 3L-NPC-VC IGCT VDM , 3.3, 4. L-VC IGBT Alstom.3, 3.3, VDM L-FLC-VC IGBT VDM L-NPC-VC GTO General Dura-Bilt5 MV L-NPC-VC IGBT Electric MV-GP Type H , 4.6 ML-CHB-VC IGBT

29 OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIE 5 Figure - illustrates two examples of medium voltage drives: Figure -a shows a medium voltage drive using an IGBT-based 3L-NPC inverter (IMOVERT [9]). The standardized output power range extends for motors from about.mw up to more than 7MW [5]. Figure -b shows a 4.6kV, 7.5MW CHB inverter with five identical IGBT power cells which generate levels at the line-to-line output voltage (AI Robicon [9]). Figure - Application ranges of commercially available power semiconductors [4], [8] (a) Cabinet of iemens (IMOVERT MV) (b) Cabinet of AI Robicon (Perfect Harmony) Figure - IGBT-based inverter fed medium voltage drives: (a) 3L-NPC, (b) CHB [9], [75]

30 6 OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIE.. tate of the Art in Medium Voltage Power emiconductors Recent technology advances in power electronics have been made by improvements in controllable power semiconductor devices. Figure -3 and Figure -4 summarize the most important power semiconductors on the market and their rated voltages and currents today [4], []. The device characteristics for medium voltage power semiconductors are shown in Table - [8]. Metal Oxide emiconductor Field Effect Transistors (MOFET) and IGBTs have replaced Bipolar Junction Transistors (BJT) almost completely. A remarkable development in MOFETs took place during the last years. Nowadays MOFETs are available up to a maximum switch power of about kva []. Various new concepts of MO-controlled thyristors such as the MO-controlled thyristor (MCT) and the MO turn-off thyristor (MTO) have been presented but they do not have any commercial applications. Conventional GTOs are available with a maximum device voltage of 6kV in traction and industrial converters (Table -) [], [8]. The high on state current density, the high blocking voltages, and the possibilities to integrate an inverse diode are considerable advantages of these devices. However, the requiring of bulky and expensive snubber circuits [9], [93] as well as the complex gate drive are the reasons that GTOs are being replaced by IGCTs and Gifts [], [8]. Like GTOs, IGCTs are offered only as a presspack device. The symmetrcial IGCT is offered by Mitsubishi with a maximum device voltage of 6.5kV (Table -) [], [8]. An increase of the blocking voltage of IGCTs and inverse diodes to kv is technically possible today []. Due to the thyristor latching, a GTO structure offers lower conduction losses than an IGBT of the same voltage class. To improve the switching performance of classical GTOs, gatecommutated thyristors (GCTs) with a very little turn-off delay (about.5µs) have been developed [9], [9]. New asymmetric GCT devices up to kv with peak controllable currents up to ka have been manufactured but only those devices with 6kV and 6kA are commercially available. IGBTs were introduced on the market in 988. IGBTs from.7kv up to 6.5kV with dc current ratings up to 3kA are commercially available today (Table -) [], [8]. They have been optimized to satisfy the specifications of the high-power motor drives for industrial and traction applications. They are mainly applied in a module package due to the complex and expensive structure of an IGBT presspack [8]. In IGBT modules, multiple IGBT chips are connected in parallel and bonded to ceramic substrates to provide isolation. Both IGCTs and IGBTs have the potential to decrease the cost of systems and to increase the number of economically valuable applications as well as the performance of high-power converters, compared to GTOs, due to a snubberless operation at higher switching frequencies (e.g. 5-Hz). Figure -5 represents the typical converter voltage as a function of power ratings for both IGBT and IGCT applications [8], [3], [3]. It can be seen that LV-IGBT modules are commercially available with a maximum device voltage of 7V on the entire low-voltage drive market (i.e. up to 69V). On the other hand, MV-IGBT modules enable converter designs in a voltage range from kv up to 7.kV with a power range from kva up to 7MVA (Figure -4) [8]. MV- IGBT modules have replaced GTOs in recent traction applications. IGBT presspacks are applied mainly in self-commutated High Voltage Direct Current (HVDC) converters (e.g. HVDC light) where a redundant converter design is a main

31 OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIE 7 requirement and each converter switch position consists of a series connection of many IGBTs (e.g. n ) [8]. Table - Device rating and package types of typical MV power semiconductors [8] Power emiconductors Manufacturer Voltage Ratings Current Ratings Case GTO MITUBIHI 6kV 6A* Presspack 4.5kV -4A* Presspack ABB 4.5kV 6-4A* Presspack 6kV 3A* Presspack EUPEC 3.3kV 4-A Module 6kV -6A Module MITUBIHI 3.3kV 4.5kV 6kV 8-A 4-9A 6A Module Module Module IGBT HITACHI 3.3kV 4-A Module TOHIBA 3.3kV 4-A Presspack IGCT ABB ABB MITUBIHI 4.5kV 3.3kV 4.5kV 6kV 4.5kV 4.5kV 5.5kV 6kV 4.5kV 6kV 6.5kV -A A 6-3A 6A 38-4A* 34-A** 8-8A** 3A* 4A* 35-6A* 4-5A*** Module Module Presspack Module Presspack Presspack Presspack Presspack Presspack Presspack Presspack *: Asymetric blocking device **: Reverse conducting device ***: ymetric blocking device Power emiconductors ilicon ilicon Carbide Diodes Transistors Thyristors Diodes Transistors chottky BJT GTO chottky MOFET PIN MOFET IGCT JB Double (PIN) IGBT GCT PIN MCT MTO Low importance on the market today Figure -3 Classification of state-of-the-art power semiconductors []

32 8 OVERVIEW OF MEDIUM VOLTAGE CONVERTER TOPOLOGIE IGCTs enable converter designs in the high power range from 5MVA up to MVA in a voltage range of.3kv to 5kV. The majority of applications are industrial converters and drives as well as interties, dynamic voltage restorers, and energy storage systems [8]. Figure -4 Power range of commercially available power semiconductors [4], [] U ll Figure -5 Application ranges of IGBTs and IGCTs [8], [3], [3]

33 3. BAIC TRUCTURE AND FUNCTION OF MULTI-LEVEL VOLTAGE OURCE CONVERTER TOPOLOGIE This chapter describes the basic structure and function of Multi-level VC topologies. The principle of operation that includes the structure, switching states, and modulation methods are discussed for the L-VC, 3L-NPC VC, 3L-FLC VC, 4L-FLC VC, 9L-CLHB VC, and the hybrid VC. 3.. Two-Level Voltage ource Converter (L-VC) 3... tructure of Two-Level Voltage ource Converter The three-phase L-VC consists of three legs, one for each phase, as shown in Figure 3-. Each converter leg consists of two active switches and two freewheeling diodes in parallel with each switch. The output of each leg of the three-phase converter depends only on the dc link voltage and the switch state. The output voltage is independent of the output load current since one of the two active switches or freewheeling diodes in a leg is always on at any instant. Therefore, the converter output voltage is independent of the direction of the load current. + i dc C U c T a D Ta T b D Tb T c D Tc c M U am a b c C U c T a D Ta T b D Tb T c D Tc - iph,a U ab U bc n Figure 3- Two-Level Voltage ource Configuration 3... witch tates and Commutations As shown in Figure 3-, the three-phase two-level VC contains six unidirectional active switches having inverse diodes. Each ac terminal of the converter (a, b, or c) can be connected to the positive dc rail "+" or the negative dc rail "-". Thus, the number of different converter switch states calculates to nsw ph 3 = N = = 8 (3-) with N being the number of voltage levels in the dc link and ph being the number of phases.

34 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The switch positions for two possible states of each phase leg are given in Table 3-, where and denote the on- and off state of the switch. Figure 3-a depicts the eight active inverter voltage vectors for the three-phase two-level VC, where [ ] means that a, b are switched off and c is switched on. [ ] [ ] [ ] a b c a b c a b c [ ] [ ] [ ] a b c a b c a b c [ ] [ ] a b c a b c + (a) + C T a D Ta C T a D Ta M a M a C T a D Ta C T a D Ta - + (b) - + C T a D Ta C T a D Ta M M C T a D Ta C T a D Ta - (c) - Figure 3- witch states: (a) conduction paths, (b) commutations and switching losses of the L-VC

35 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE Table 3- witch positions for each phase of the two-level VC tate x x Positive + (U xm = + /) Negative - (U xm = - /) The current paths for positive and negative phase currents i ph are depicted in Figure 3-b. In any switch state, one semiconductor lies within the current path. It should be noted that all switches and diodes of the two-level VC are stressed by. Assuming a sinusoidal phase current, the maximum switch/diode current is the maximum phase current î ph. These parameters determine the rating of the main semiconductors. witching losses are created by the commutation processes between the different switch states. Only turn-on and turn-off losses of active switches and recovery losses of diodes are considered. Turn-on losses of diodes are usually small so that they can be neglected []. The distribution of the switching losses and the conduction losses are summarized in Table 3- and Table 3-3 respectively. For a positive phase current i ph >, the commutation (+ ) is initiated by the turn-off of T x and the current forced from T x to D Tx (x = a, b, c). The situation is visualized in Figure 3-8c, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled. In contrast, the commutation ( +) is initiated by the turn-off of D x and the current forced from D Tx to T x. For a negative phase current i ph <, the commutation (+ ) is initiated by the turn-off of D Tx and the current forced from D Tx to T x. In contrast, the commutation ( +) is initiated by the turn-off of T x and the current forced from T x to D Tx, as shown in Figure 3-8c. Table 3- Conduction losses in the two-level VC tate T x T x D Tx D Tx Positive phase current + - Negative phase current + - Table 3-3 witching losses in the two-level VC tate T x T x D Tx D Tx Positive phase current + Negative phase current ine-triangle Modulation The purpose of PWM three-phase converters is to shape and to control the three-phase output voltages in magnitude and frequency with an essentially constant input voltage. To obtain balanced three-phase output voltages in a three-phase PWM, the same triangular voltage

36 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE waveform U tri is compared with three control voltage waveforms ( con,a con,b con,c ) are out of phase. U, U, U that In order to generate the switching signals, three control signals are compared with a repetitive switching frequency triangular waveform, as shown in Figure 3-3a. The frequency modulation ratio m and the amplitude modulation ratio m of a PWM are defined as f a m m f a f f tri = (3-) Û n con, = (3-3) Û tri where Û con, denotes the peak value of the fundamental component of the reference voltage. For a sine-triangle modulation the linear modulation range is limited to values of m a. By adding a third harmonic with one-sixth of the fundamental amplitude, it can be expanded to its theoretical maximum of m a =.55 [73]. Thus, the reference control voltage per phase is U con,x(t) Uˆ = con, sin( wt ) + sin( 3wt ) 6 In order to trigger the switches, the following algorithm can be used: (3-4) U dc Ucon,x > Utri x = on ( x = off ) U xm = ( x= a,b,c) (3-5) U dc Ucon,x < Utri x = off ( x = on ) U xm = ( x= a,b,c) (3-6) ince the two switches are never off simultaneously, the output voltage U xm fluctuates between two values ( / and /). The gating signals (V g,x and V g,x ) and switching sequence according to Figure 3- are depicted in Figure 3-3b (for m f = 5 ) Output Waveforms and pectrum The following equations will be very helpful to obtain the line-to-line voltages (U ab, U bc and U ca ) and line-to-neutral voltages (U an, U bn and U cn ) respectively. For all investigations in this thesis, a load with a floating star point is assumed. Uab = UaM - U bm (3-7) U = U - U (3-8) an am nm where the common mode voltage U nm is calculated as UnM = ( UaM + UbM + U cm ) (3-9) 3 It should be noted that the same value of the average dc component exists in the output voltages of any one of the legs, which are measured with respect to the negative dc rail "-". These dc components are suppressed in the line-to-line voltages, as shown in Figure 3-3d. The phasemidpoint output voltage waveform (U am, U bm, and U cm ) and the common mode voltage are depicted in Figure 3-3c and Figure 3-3e respectively. The common mode voltage can assume the voltage levels of ± / and ± /6.

37 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 3 U tri U con, a U con, b U con, c (a) - V g, a (b) V g, a / U am (c) - / U ab (d) - / / 6 - / 6 - / U nm (e) Figure 3-3 Voltage waveforms of the L-VC: (a) control signals U con, x and triangular signal U tri, (b) gating signals in phase a, (c) phase-midpoint output voltage U am, (d) line-toline output voltage U ab, (e) common mode voltage U nm

38 4 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE In order to eliminate even harmonics, the frequency modulation ratio m f should be odd. The odd harmonics in the phase-midpoint voltages are the same as the output of any one of the legs, centred around the switching frequency and its multiples (m f, m f,...), as shown in Figure 3-4a. Various harmonics in the line-to-line voltage (U ab, U bc and U ca ) are suppressed due to the phase difference between the m f harmonic in the output voltage of any one of the legs, as shown in Figure 3-4b. Harmonic Magnitude (p.u.).6.4. ( U ) U am dc h m f = 5, m a =.5 (a) Harmonic Magnitude (p.u.) m f m f 3m f ( U ) U ab dc h m f = 5, m a =.5 (b) m f m f 3m f Harmonic Order Figure 3-4 Harmonic spectrum of the L-VC: (a) phase-midpoint output voltage, (b) line-toline output voltage 3.. Diode Clamped Voltage ource Converter (DC VC) 3... tructure A type of a voltage source converter configuration, which is important for high-power applications, is the so-called diode clamped (DC) converter. The diode-clamped converter provides multiple voltage levels through the connection of the phases to a series bank of capacitors. According to the original invention [7], the concept can be extended to any number of levels by increasing the number of capacitors. Early descriptions of this topology were limited to three levels [37], where two capacitors were connected across the dc bus resulting in one additional level. The additional level was the neutral point of the dc bus; hence, the terminology NPC converter was introduced [37]. However, with an even number of voltage levels, the neutral point is not accessible, and the term multiple point clamped (MPC) is sometimes applied [4]. Due to capacitor voltage balancing and also high voltage stress on the clamping diodes with a number of levels larger than three, the diode-clamped converter implementation has been mostly limited to three levels [7], [], [3]. In this case the converter is usually called Three-Level Neutal Point Clamped Voltage ource Converter (3L-

39 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 5 NPC VC). One phase leg consists of (N-) active switches and (N-) (N-) clamping diodes, where N is the number of voltage levels shown in Figure 3-5 []. The total dc bus voltage is distributed across the dc capacitors C, C,..., C (N-). Hence, an output voltage of / (N-),..., / (N-) is possible at the output [47]. M (N-) i dc(n-) i c(n-) C (N-) i dc(n-) D (N-)a D (N-)a (N-)a (N-)a M (N-) i c(n-) D (N-3)a (N-3)a C (N-) M (N-3) i dc(n-3) D a a i c(n-3) C (N-3) a i ph,a a (N- )a i dc(n-4) M (N-4) i c(n-4) (N- )a (N- 3 )a i dc M i c a C a M o Figure 3-5 One-phase N-Level Neutral Point Clamped Converter [] 3... Three-Level Neutral Point Clamped Voltage ource Converter (3L-NPC VC) The topology of the three-level neutral point clamped (diode-clamped) converter is presented in Figure 3-6. It contains unidirectional active switches having inverse diodes and 6 neutral point clamp diodes. The switches x, x are named outer switches ( out ) and the remaining switches x, x are designated inner switches ( in ). The group of NPC-diodes is referred to as D x,d x. This converter has a zero dc voltage centre point "M ", which is switchable to the phase outputs, thereby creating the possibility of switching each converter phase leg to one of three voltage levels. The major benefit of this configuration is that, while there are twice as many switches as in the two-level converter, each of the switches must block only one-half of the dc link voltage " /" [7]. However, one problem that does not occur in a two-level converter is the need to ensure voltage balance across the two series-connected capacitors making up the dc link. One solution is to simply connect each of the capacitors to its own

40 6 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE isolated dc source (for example, the output of a diode bridge fed from a secondary transformer) [7], [4]. The other method is to balance the two capacitor voltages by feedback control [7], [4], [5]. M i dc T a D Ta T b D Tb T c D Tc c D a D b D C U c T a D Ta T b D Tb T c D Tc i dc M a b c T a T b T c C U c D a D b D c T a T b T c M i dco U ab U bc i ph,a n Figure 3-6 Three-phase Three-Level Neutral Point Clamped Converter 3... witch tates and Commutations In order to produce three levels, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time [37]. In summary, each phase node (a, b, or c) can be connected to any node in the capacitor bank (M, M, and M ). Thus, the number of different converter switch states calculates to nsw ph 3 = N = 3 = 7 (3-) with N being the number of voltage levels in the dc link and ph being the number of phases. Connection of the a-phase to junctions M and M can be accomplished by switching both transistors T a and T a either off or on. These states are the same as the two-level inverter, yielding a phase voltage of U xm = / or U xm = - / assuming U C = U C = /. The connection to the junction M is accomplished by gating T a on and T a off. In this representation, the labels T a and T a are used to identify the transistors as well as the transistor logic ( = on and = off). ince the transistors are always switched in pairs, the complement transistors are labelled T a and T a accordingly. In a practical implementation, some dead time is inserted between the transistor signals and their complements meaning that both transistors in a complementary pair may be switched off for a small amount of time during a transition. However, for this discussion here the dead time will be ignored. From Figure 3-6 it can be seen that, with this switching state, the a-phase current i ph,a will flow into the junction through diode D a if it is negative, or out of the junction through diode D a if the current is positive. According to this description, the switch positions for three possible states of each phase leg are given in Table 3-4. The current paths for positive and negative phase currents i ph are depicted in Figure 3-7. In zero state, the direction of i ph determines whether the upper or lower path of the neutral tap is

41 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 7 utilized. Therefore, both x and x have to be turned on in zero state "" to provide an open path in case the phase current reverses. In any switch state, two semiconductors in series lie within the current path, either two active switches or two diodes for the states positive "+" and negative "-". It should be noted that each of the switches must block only one-half of the dc link voltage / assuming sinusoidal currents. The maximum switch/diode current is the maximum phase current î ph. These parameters condition the rating of the main semiconductors. The distribution of the conduction losses is summarized in Table 3-5. Table 3-4 witch positions for one phase of the three-level NPC VC tate x x x x Positive + (U xm = + /) Zero (U xm = ) Negative - (U xm = - /) x x x D x x D x x D x x D x x D x x D x x x x x Figure 3-7 Conduction path of the Three-Level Neutral Point Clamped Converter Table 3-5 Conduction losses in the 3L-NPC VC tate T x D Tx Tx DT x Tx DT x Tx DT x Positive phase current + - Negative phase current + - witching losses are created by the commutation processes between the different switch states. For a positive phase current i ph >, the commutation from "+" towards "-" (+ ) is named forced commutation. The contrary natural commutation ( +) realizes a positive output power gradient. They are initiated by an active turn-on transient. For the following discussion of commutations, a positive phase current i ph > is assumed. Only turn-on and turn-off losses of active switches and recovery losses of diodes are D x D x

42 8 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE considered. For a positive phase current i ph >, the commutation (+ ) is initiated by the turn-off of T x and the current is forced from T x to D x. After a dead time (to ensure that T x has completely turned off), T x is turned on. The switches T x and T x stay on and off respectively. Only two switches and diodes are involved in this commutation: T x and D x. Essential turn-off losses occur in T x. Though the switch T x is turned on, it does not experience losses since it does not take over any current after the commutation. For the reverse commutation ( +), all switching transitions take place in the reverse order. T x is turned off first, followed by turning on T x after the dead time. Turning off T x does not affect the phase current. It only returns to the positive rail after the turn-on of T x. Recovery losses occur in D x, and T x experiences turn-on losses. The situation for this pair of commutations is visualized in Figure 3-8a, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled. Four devices are involved in the commutation ( ) (Figure 3-8b). It is started by the active turn-off of the switch T x, forcing the current from its path through D x and T x to D Tx and D Tx. T x has already been in the on state before; T x is turned on after a dead time. T x faces turn-off losses. D x E rec x x E E on off D x x x E E on off D x x D x x x x E rec (a) (b) x E rec x D x x D x x D x x x E E on off D x E rec x x E E on off (c) (d) Figure 3-8 Commutations and switching losses in the 3L-NPC VC: (a) and (b) for positive load current, (c) and (d) for negative load current

43 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 9 Although the diode D x in series with T x is turned off too, it does not experience notable recovery losses since it does not take over voltage after the commutation. Again, for the reverse commutation ( ), all switching transitions take place in the reverse order. T x is turned off, and T x is turned on after a dead time. After triggering T x, the phase current commutates from D Tx and D Tx back to D x and T x. Both diodes in series D Tx and D Tx are turned off, but only D Tx takes over blocking voltage. Thus, only D Tx experiences recovery losses. T x faces turn-on losses. This situation is depicted in Figure 3-8b. The commutations at negative phase current are illustrated in Figure 3-8c and Figure 3-8d. The distribution of the switching losses is summarized in Table 3-6. It is important to note that all commutations in the NPC VC can be explained by the basic commutation cell, comprising one active switch and one diode. Table 3-6 witching losses in the 3L-NPC VC tate T x D Tx Tx DT x Tx DT x Tx DT x Positive phase current + Negative phase current + D x D x 3... ine-triangle Modulation To obtain balanced three-phase output voltages, the converter is controlled by a PWM technique. The reference control voltage per phase is U con,x(t) Uˆ = con, sin( wt ) + sin( 3wt ) 6 (3-) where Û con, denotes the peak value of the desired fundamental component of the reference voltage. In order to generate the switching signals, two triangular voltage waveforms U tri,up and U tri,low are compared with three control voltage waveforms that are out of phase (which is drawn for m f = 5 ), as shown in Figure 3-9a. In order to trigger the switches, the following algorithm can be used U dc Ucon,x > Utri,up ( x = on, x = on) UxM = U dc Ucon,x < Utri,low ( x = on, x = on) UxM = else U xm = x = a,b,c ( ) (3-) The positive half wave of the desired sinusoid is generated by switching the respective phase leg

44 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE between the positive "+" and zero "" states, and the negative half wave is generated by switching between the zero "" and negative "-" states. The average switching frequency per device equals half the carrier frequency visible at the output. U tri,up U con, a U con, b U con, c U tri,low (a) - V g, a (b) V g, a / (c) U am - / / - / U ab (d) - / U nm (e) - / Figure 3-9 Voltage waveforms of the 3L-NPC VC: (a) control signals U con, x and triangular signals U tri,up and U tri,low, (b) gating signals in phase a, (c) phase-midpoint output voltage U am, (d) line-to-line output voltage U ab, (e) common mode voltage U nm

45 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The output voltage fluctuates between three values ( /,, and /). The gating signals and switching sequence according to Figure 3-6 are depicted in Figure 3-9b. The output voltage waveforms of the three-phase 3L-NPC VC according to Figure 3-6 are depicted in Figure 3-9. The line-to-line voltages of the three-level converter, e.g. U = U - U (3-3) ab am bm comprise five voltage levels, viz. +, + /,, - /, - (see Figure 3-9d). The connection of two considered phases to the opposite dc rails gives rise to the maximum lineto-line voltage of ±. The intermediate voltage levels are generated by connecting one phase to neutral point M, whereas both phases switched to the same dc terminal create a zero voltage. The comparison of the line-to-line voltage waveform of Figure 3-9d with that of a two-level converter clearly reveals the superior output voltage quality of the 3L-NPC VC. The steps in the line-to-line voltage are reduced to /, compared to for the two-level converter. Moreover, the reduction of the commutation voltage to / yields lower switching losses for every single commutation [3]. The common mode part of the phase voltages drops between load star point "n" and converter neutral point "M ". The common mode voltage depicted in Figure 3-9e is calculated as UnM = ( U ) am + U bm + U cm (3-4) 3 and the line-to-neutral voltage shown in Figure 3-9c is as follows U = U - U (3-5) an am nm The line to neutral voltage consists of nine voltage levels, viz. ± /3, ± /, ± /3, ± /6, and. Harmonic Magnitude (p.u.) ( UaM ) U dc h m f = 5, m a =.5 (a) -3 Harmonic Magnitude (p.u.) -3 3 m f m f 3m f ( U ) U ab dc h m f = 5, m a =.5 m f m f 3m f Harmonic Order (b) Figure 3- Harmonic spectrum of the 3L-NPC VC: (a) phase-neutral point output voltage, (b) line-to-line output voltage

46 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The common mode voltage can assume the voltage levels of ± /, ± /3, ± /6, and. However, the maximum common mode voltage arises from the connection of all three phases to either the positive or the negative dc link. The odd harmonics in the line-to-neutral voltages are centred around a switching frequency and its multiples ( m,m,3m,...), f f f as shown in Figure 3-a. ome dominant harmonics are suppressed in the line-to-line voltage (U ab, U bc and U ca ), as shown in Figure 3-b Flying Capacitor Voltage ource Converter (FLC VC) Flying Capacitor Converter tructure Another fundamental multi-level topology, the flying capacitor converter, involves a series connection of capacitor switching cells [44]. This topology has several unique and attractive features when compared to the diode-clamped converter. One feature is that added clamping diodes are not needed. Furthermore, the flying capacitor converter has a switching redundancy within the phase, which can be used to balance the flying capacitors so that only one dc source is needed. Traction converters (e.g. T3 locomotive [45]) and industrial medium voltage converters (e.g. YMPHONY [45], [8]) are typical applications of this topology. One phase leg consists of (N-) active switches and (N-) flying capacitors, with N being the number of level voltage waveforms U xm shown in Figure 3- [47]. i c(n-),a (N-)a (N-)a i c,a 3a i c,a a a Cell M C (N-)a C a C a i ph,a a a a 3a (N )a (N )a Figure 3- The generalized N-Level Flying Capacitor Converter []

47 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE Three-Level Flying Capacitor Voltage ource Converter (3L-FLC VC) The topology of the three-level flying capacitor converter is presented in Figure 3-. It contains unidirectional active switches having inverse diodes and 3 flying capacitors. The general concept of operation is that each flying capacitor is charged to one-half of the dc voltage. It can be connected in series with the phase to add or subtract this voltage. i c,a T a T a D Ta D Ta i c,b b b i c,c c c M U Ca C a a C b b C c c T a b c T a b c U ab U bc i ph,a n Figure 3- Three-phase Three-Level Flying Capacitor Converter witch tates and Commutations In order to produce three levels, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time. In this representation, the labels T a and T a are used to identify the transistors as well as the transistor logic ( = on and = off). ince the transistors are always switched in pairs, the complement transistors are labelled T a and T a accordingly. Table 3-7 shows the switch positions for each phase leg. In comparison to the three-level diode clamped converter, an extra switching state is possible. In particular, there are two transistor states which make up the zero state. Considering the direction of the a-phase flying capacitor current i c,a for the redundant states, a decision can be made to charge or discharge the capacitor, and the capacitor voltage can therefore be regulated to its desired value by operating the switches within the phase. Due to two switch states that produce the same output voltage but different current directions through the flying capacitor, the capacitors can be balanced regardless of the load current. Table 3-7 witch positions for one phase of the three-level FLC VC tate x x x U x xm i c,x + / - i ph i ph - - /

48 4 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The current paths for positive and negative phase currents i ph are depicted in Figure 3-3. For positive and negative phase currents, either both x, x or both x, x, have to be turned on in state "". In any switch state, two semiconductors in series lie within the current path, either two active switches or two diodes for the states "+" and "-". Like the 3L-NPC, each switch must block only one-half of the dc link voltage /. The distribution of the conduction losses is summarized in Table 3-8. witching losses are created by the commutation processes between the different switch states. T x T x D Tx D Tx T x T x D Tx D Tx M C x M C x T x T x T x T x (a) (b) T x T x D Tx D Tx T x T x D Tx D Tx M C x M C x T x T x T x T x (c) (d) Figure 3-3 Conduction path of the Three-Level Flying Capacitor Converter Table 3-8 Conduction losses in the three-level FLC VC tate T x D Tx Tx DT x Tx DT x Tx D Tx Positive phase current + - Negative phase current + -

49 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 5 For a positive phase current i ph >, the commutation (+ ) is initiated by the turn-off of T x. After a dead time (to ensure that T x has completely turned off), T x is turned on and the current is forced from T x to D x. The switches T x and T x stay on and off respectively. Essential turnoff losses occur in T x. For the reverse commutation ( +), all switching transitions take place in the reverse order. T x is turned off first, followed by the turn-on of T x after the dead time. The situation for this pair of commutations is visualized in Figure 3-4a, where the commutation (+ ) is marked bold and the reverse commutation ( +) is marked with a dashed line. The loss devices are encircled. The commutation ( ) is started by the active turn-off of the switch T x, forcing the current to D Tx. T x has already been in the on state and T x faces turn-off losses. Again, for the reverse commutation ( ), all switching transitions take place in the reverse order. T x is turned off and T x turned on after a dead time. After triggering T x, the phase current commutates from D Tx back to T x. The diode D Tx is turned off and thus experiences recovery losses while T x faces turn-on losses. This situation is depicted in Figure 3-4c. The commutations at negative phase current are illustrated in Figure 3-4e and Figure 3-4f. The distribution of the switching losses is summarized in Table 3-9. Table 3-9 witching losses in the three-level FLC VC tate T x DT x Tx DT x Tx DT x Tx D Tx Positive phase current + Negative phase current ine-triangle Modulation The 3L-FLC VC is modulated by a sine-triangle modulation with an addition of /6 of the third harmonics according to equation (3-7). The modulation of this converter can be seen in Figure 3-5a. In the FLC VCs, there is one carrier signal per commutation cell and the commutations of one commutation cell are determined by the comparison of the carrier and the reference signals. Two carrier signals are shifted by T C /, resulting in four commutations per phase during one period T C. In order to generate the switching signals, two triangular voltage waveforms U tri,cell, and U tri,cell, are compared with three control voltage waveforms that are out of phase (which is drawn for m f = 5 ). In order to trigger the switches, the following algorithm can be used. The gating signals and switching sequence according to Figure 3- are depicted in Figure 3-5b. ( ) ( ) ( ) ( ) Ucon,x > Utri,cell, x = on x = off U dc U xm = ( x= a,b,c) U con,x Utri,cell, x on x off > = = Ucon,x < Utri,cell, x = off x = on U dc U xm = x= a,b,c U con,x < Utri,cell, x = off x = on else U = x = a,b,c xm ( ) ( ) (3-5)

50 6 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE M C x x x E E on off (a) M C x x x E E on off (b) x E rec x x x E rec i ph >, commutation (+ ) i ph >, commutation (+ ) (c) Eon x x Eoff x E x E M M C x C x on off (d) x x E rec x E rec x i ph >, commutation ( ) i >, commutation ( ) ph M i ph C x x x x x E rec E E on off (e) <, commutation (+ ) i <, commutation (+ ) M ph C x x x x x E rec E E on off (f) (g) (h) x x E rec x x E rec M i ph C x x x E E on off <, commutation ( ) i <, commutation ( ) Figure 3-4 Commutations and switching losses in the 3L-FLC Converter (a-d) for positive load current, (e-h) for negative load current M ph C x x x E E on off

51 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 7 U tri,cell, U tri,cell, U con, a U con, b U con, c (a) - V g, a (b) V g, a / U am (c) - / / - / U ab (d) - / - / U nm (e) Figure 3-5 Voltage waveforms of the 3L-FLC VC: (a) control signals and triangular signals, (b) gating signals in phase a, (c) phase-midpoint output voltage U am, (d) line-to-line output voltage U ab, (e) common mode voltage U nm

52 8 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The output voltage waveform of the three-phase 3L-FLC VC according to Figure 3- is depicted in Figure 3-5c to Figure 3-5e. The phase-to-midpoint voltages of the 3L-FLC VC, e.g. U am, comprise three voltage levels, viz. + /,, - / (see Figure 3-5c) and the line-toline voltages, e.g. U ab, comprise five voltage levels, viz. +, + /,, - /, - (see Figure 3-5d). The connection of two considered phases to the opposite dc rails gives rise to the maximum line-to-line voltage of ±. The common mode part of the phase voltages drops between load star point "n" and converter midpoint "M". The common mode voltage depicted in Figure 3-5e is calculated according to equation (3-9). The common mode voltage can consist of the voltage levels of ± /3, ± /, ± /3, ± /6, and. For a constant carrier frequency, the 3L-NPC VC generates half of the switching losses than the 3L-FLC VC, where two commutation cells switch during one period of the carrier frequency (T C = /f C ). However, whereas the first carrier band of the line-to-line voltage of the 3L-NPC VC occurs around the carrier frequency, the first carrier band is centred around two times the carrier frequency in the 3L-FLC VC (f Cb = f C ), as shown in Figure 3-6. Harmonic Magnitude (p.u.) -3 Harmonic Magnitude (p.u.) -3 ( U ) U am dc ( U ) U ab dc h h m f = 5, m a =.5 3 m f m f 3m f m f = 5, m a =.5 m f m f 3m f Harmonic Order (a) (b) Figure 3-6 Harmonic spectrum of the 3L-FLC VC: (a) phase-neutral point output voltage, (b) line-to-line output voltage Four-Level Flying Capacitor Voltage ource Converter (4L-FLC VC) Figure 3-7 shows the structure of the three-phase 4L-FLC VC. For this converter, the capacitors C x and C x are ideally charged to one-third and two-thirds of the dc voltage respectively. The four voltage levels are obtained by the relationships shown in Table 3-. As with the three-level flying capacitor converter, the highest and lowest switching states do not change the charge of the capacitors. The two intermediate voltage levels contain redundant states so that both capacitors can be regulated to their ideal voltages. In order to generate the switching signals, three triangular voltage waveforms U ( i = 3,, ) tri,cell,i are compared with three control voltage waveforms that are out of phase. The three carrier

53 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 9 signals are shifted by T C /3, resulting in six commutations per phase during one period T C. The modulation of the 4L-FLC converter topology can be seen in Figure 3-8a for m f = 5. i c,a T 3a D T3a 3b 3c i c,b i c,c i c,a T a D Ta i c,b b i c,c c M U Ca C a U Ca C a T a D Ta a C b C b b b C c C c c c T a b c T a b c T3a 3b 3c i ph,a U ab U bc n Figure 3-7 Three-phase Four-Level Flying Capacitor Converter In order to trigger the switches, the following algorithm can be used Ucon,x > Utri,cell, 3x = on ( 3x = off ) ( ) con,x tri,cell, x x xm Ucon,x > Utri,cell, 3 x = on ( x = off ) Ucon,x < Utri,cell, 3x = off ( 3x = on) Ucon,x < Utri,cell, x = off ( x = on) xm Ucon,x < Utri,cell, 3 x = off ( x = on) ( con,x > tri,cell, con,x > tri,cell, con,x < tri,cell, 3) ( con,x > tri,cell, con,x < tri,cell, con,x > tri,cell, 3) ( Ucon,x < Utri,cell,, Ucon,x > U tri,cell,, Ucon,x > Utri,cell, 3) ( con,x > tri,cell, con,x < tri,cell, con,x < tri,cell, 3) ( con,x < tri,cell, con,x > tri,cell, con,x < tri,cell, 3) ( Ucon,x < Utri,cell,, Ucon,x < U tri,cell,, Ucon,x > Utri,cell, 3) Udc U > U = on = off U = x= a,b,c ( ) Udc U = ( x= a,b,c) U U, U U, U U or Udc U U, U U, U U or U xm = 6 U U, U U, U U or U dc U U, U U, U U or U xm = 6 (3-6) The output voltage waveforms of the three-phase 4L-FLC VC according to Figure 3-7 are depicted in Figure 3-8b to Figure 3-8d.

54 3 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE Table 3- witch positions for one phase of the four-level FLC VC tate x x 3x x x U 3x xm c,x i - / - /6 -i ph i c,x - /6 i ph -i ph - /6 i ph /6 -i ph /6 i ph /6 - i ph i ph 3 / U tri,cell,3 U tri,cell, U tri,cell, U con, a U con, b U con, c (a) - / U am (b) - / / - / U ab (c) - / - / U nm (d) Figure 3-8 Voltage waveforms of the 4L-FLC VC: (a) control signals and triangular signals, (b) phase-midpoint output voltage U am, (c) line-to-line output voltage U ab, (d) common mode voltage U nm

55 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 3 The phase-to-midpoint voltages of the 4L-FLC VC, e.g. u am, comprise four voltage levels, viz. ± / and ± /6 (see Figure 3-8b) and the line-to-line voltages, e.g. U ab, comprise seven voltage levels, viz. ±, ± /3, ± /3, (see Figure 3-8c). The common mode voltage U nm can assume the voltage levels of ± /3, ±5 /9, ±4 /9, ± /3, ± /9, and ± /9 (see Figure 3-8d). The harmonic spectrum of phase voltage and line-to-line voltage are depicted in Figure 3-9. The first carrier band harmonics of the 4L-FLC VC occurs at three times the corresponding carrier frequency (f Cb = 3f C ). Figure 3- shows the transitions between two voltage levels in the 4L-FLC VC. ome of these transitions (dashed lines) force all switches of the leg to switch. Nevertheless, these critical transitions can be used to achieve the full control of the voltages of the floating capacitors. Harmonic Magnitude (p.u.) Harmonic Magnitude (p.u.) -3-3 ( U ) U am dc ( U ) U ab dc h h m f = 5, m a =.5 3 m f m f 3m f m f = 5, m a =.5 m f m f 3m f Harmonic Order (a) (b) Figure 3-9 Harmonic spectrum of the 4L-FLC VC: (a) phase-neutral point output voltage, (b) line-to-line output voltage U U xm = dc U U xm = 6 dc U U xm = 6 dc U U xm = dc 3x x x 3x x x 3x x x 3x x x off off on off on on off off off off on off on off on on on on on off off on on off Figure 3- Transitions between voltage levels for the Four-Level Flying Capacitor

56 3 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 3.4. eries Connected H-Bridge Voltage ource Converter (CHB VC) This class of multi-level converters is based on a series connection of single-phase converters (Figure 3-), and the earliest reference to them appeared in 975 [8] but several recent patents have been obtained for this topology as well [9], [3], [3]. This converter topology has several advantages that have made it attractive to medium and high power drive applications [86]. ince this topology consists of series power conversion cells, the voltage and power level may be easily scaled. The dc link supply for each H-bridge converter element must be provided separately. The ability to synthesize higher number of output voltage levels with an excellent harmonic spectrum utilizing low-cost low-voltage power semiconductors and capacitors are important advantages of this topology [86]. However, drawbacks of this topology are the large number of power devices and of voltages required to supply each cell with a complex and expensive isolated transformer, as well as control the complexity [6], [9]. i ph,a n a b c i dcpa i dcpb i dcpc T pra T pla U pan T prb T plb U pbn T prc T plc U pcn pa pb pc T pra T pla T prb T plb T prc T plc i dca i dcb i dcc T Ra T La U an T Rb T Lb U bn T Rc T Lc U cn a b c T Ra T La T Rb T Lb T Rc T Lc i dca i dcb i dcc T Ra T La U an T Rb T Lb U bn T Rc T Lc U cn a b c T Ra T La T Rb T Lb T Rc T Lc n Figure 3- Three-phase configuration for the N-Level H-Bridges VC ingle-phase Full-Bridge (H-Bridge) Topology Circuit Configuration The circuit of Figure 3- shows the basic topology of an H-bridge converter used for the implementation of CHB VCs. It is based on the simple, four switches converter, which is usually used for single-phase applications. A three-phase diode rectifier, fed by an isolated transformer, charges the dc capacitor. The dc voltage feeds a single-phase IGBT bridge, which generates the PWM output of the power cell.

57 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 33 i dc R T T L L a D D L L i ph T T R R n D D R U = U U an ag n g R g Figure 3- Typical power cell (H-bridge) converter witch tates and Commutations Each cell consists of two half-bridge configurations. The labels T L and T R are used to identify the transistors as well as the transistor logic ( = on and = off). ince the transistors are always switched in pairs, the complement transistors are labelled T L and T R accordingly. In order to prevent a short circuit, the complementary leg switches are not switched simultaneously. In other words, whatever state the top switch is in (either on or off) the bottom switch must be in the opposite. The switch positions for the three possible states of each phase leg are given in Table 3-. The current paths for positive and negative phase currents i ph are depicted in Figure 3-3. The zero state "" can be generated in two ways, depending on the direction of i ph. Therefore, if either top switches (T L, T R ) or bottom switches ( T,T) L R are turned on, the output voltage will lead to zero. In positive "+" and negative "-" states, two diagonally opposite semiconductors, (T L, T R ) or (T R, T L ), lie within the current path, either two active switches or two diodes. Therefore, each typical H-bridge cell can only produce three distinct voltage levels. It should be noted that each of the switches must block the dc link voltage /. The maximum switch/diode current is the maximum phase current î ph. These parameters determine the basic requirements for rating the main semiconductors. The distribution of the conduction losses is summarized in Table 3-. witching losses are created by the commutation processes between the different switch states. Two complement switches in each leg, (T R, T R ) or (T L, T L ), are involved in (+ ) and ( ) commutations. For a positive phase current i ph >, the commutation (+ ) is initiated by the turn-off of T L in the first leg and the current is forced from T L to D L The switch T R stays turned on. Only two complement switches in the first leg are involved in this commutation. Essential turn-off losses occur in T L. In the second leg, the commutation (+ ) is initiated by the turn-off of T R and the current is forced from T R to D R. The switch T L stays turned on. Only two complement switches in the second leg are involved in this commutation (T R, T R ). Essential turn-off losses occur in T R. For the reverse commutation ( +), all switching transitions take place in the reverse order.

58 34 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE For example, in the second leg, T R is turned off first, followed by the turn-on of T R after the dead time. Recovery losses occur in D R while T R experiences turn-on losses. Table 3- witch positions for the single-phase H-bridge cell tate L R L U R ag U n g U an Positive + / / / / Zero Negative - / - / T L D L T R D R T L D L T R D R a n a n T L D L T R D R T L D L T R D R (a) (b) T L D L T R D R T L D L T R D R a n a n T L D L T R D R T L D L T R D R (c) (d) Figure 3-3 Conduction path of the single-phase H-bridge cell: (a) positive, (b, c) zero, and (d) negative states Table 3- Conduction losses in the single-phase full-bridge converter tate T L D L T R Positive phase current + (U ag = /) (U ag = ) - (U ag = - /) Negative phase current + (U ag = /) (U ag = ) - (U ag = - /) D R T L D L T R D R

59 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 35 The situation for these commutations is visualized in Figure 3-4a, where the current path of the switching active device is marked bold and the current path of the switching passive device is marked with a dashed line. The loss devices are encircled. The commutation ( ) in the first leg is started by the active turn-off of the switch T L, forcing the current from its path through D L. D R has already been in the on state. T L faces turnoff losses. Again, for the reverse commutation ( ), all switching transitions take place in the reverse order. T is turned off and T L turned on after a dead time. L T L D L T R D R T L D L T R D R a n a n T L D L T R D R T L D L T R D R T L D L T R D R T L D L T R D R a n a n T L D L T R D R T L D L T R D R (a) i >, commutation (+ ) (b) i >, commutation ( ) ph ph T L D L T R D R T L D L T R D R a n a n T L D L T R D R T L D L T R D R T L D L T R D R T L D L T R D R a n a n T L D L T R D R T L D L T R D R (c) i <, commutation (+ ) ph (d) i, commutation ph < ( ) Figure 3-4 Commutations and switching losses in the H-bridge cell: (a) and (b) for positive load current, (c) and (d) for negative load current

60 36 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE After triggering T L, the phase current commutates from D L back to T L. Diode D L is turned off and thus takes over blocking voltage and experiences recovery losses. T L faces turn-on losses. In the second leg, the commutation ( ) is started by the active turn-off of the switch T R, forcing the current from its path through D R. D L has already been in the on state. T R faces turnoff losses. Again, for the reverse commutation ( ), all switching transitions take place in the reverse order. T R is turned off and T R turned on after a dead time. After triggering T R, the phase current commutates from D R back to T R. Diode D R is turned off and thus takes over blocking voltage and experiences recovery losses. T R faces turn-on losses. These situations are depicted in Figure 3-4b. The commutations at the negative phase current are illustrated in Figure 3-4c and Figure 3-4d. The distribution of the switching losses is summarized in Table 3-3. Table 3-3 witching losses in the single-phase full-bridge converter tate + + T Lx DLx TRx DRx T Lx DLx TRx Positive phase current Negative phase current D Rx ine-triangle Modulation Each cell is modulated by a sine-triangle modulation with an addition of /6 of the third harmonic, as shown in Figure 3-5a. There are two carrier signals Utri, U tri and the commutations of one commutation cell (half bridge) are determined by the comparison of the corresponding carrier signal and the reference signal U con. The two carrier signals are shifted by T C / (8 phase difference with respect to each other). Thus, there are four commutations during one period of the carrier signal. As shown in Figure 3-5a, the comparison of U con with U results in the following logic signals to control the switches in the first leg tri U ag U dc if : U con> U tri TL : on,tl : off = if : U < U T : off,t : on ( ) ( ) con tri L L (3-7) For controlling the second leg switches, U tri is compared with the same control signal, which yields the following U ng ( ) ( ) if : U con> U tri TR : off,tr : on = U dc if : U con< U tri TR : on,tr : off (3-8)

61 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 37 U tri, U tri, U con (a) - (b) U ag (c) U n g (d) U an, U an Figure 3-5 Voltage waveforms of the H-bridge cell: (a) control signals U con and triangular signals U tri, and U tri,, (b) a-leg output voltage U ag, (c) n -leg output voltage U n g, (d) load voltage U an Because of the diodes in anti-parallel with the switches, the foregoing voltage given by equations (3-3) and (3-3) are independent of the direction of the output current i ph. The output voltages of leg a and leg n with respect to the negative dc rail g are shown in Figure 3-5b and Figure 3-5c respectively. The H-bridge output voltage waveform U an according to Figure 3- is depicted in Figure 3-5d. This voltage comprises three voltage levels, viz. ± / and. Because two legs of the H-bridge are controlled separately, as mentioned in the previous section, the first carrier band harmonics of the output voltage occur at twice the corresponding carrier

62 38 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE frequency (f Cb = f C ). This advantage appears in the harmonic spectrum of the output voltage waveform, as shown in Figure 3-6. If we choose the frequency modulation ratio m f to be even, the output voltage waveforms of any one of the legs U ag and U n g are displaced by 8 of the fundamental frequency, with respect to each other. Therefore, the harmonic components at the switching frequency in any one of the legs have the same phase, since the output voltage waveforms are 8 displaced and m f is assumed to be even [4]. This results in the cancellation of the harmonic component at the sidebands of the switching frequency in the output voltage. Moreover, the use of this PWM voltage switching causes a smaller ripple on the dc current side. We notice that when both the upper switches are on, the output voltage is zero. The output current circulates in a loop through (T L, D R ) or (D L, T R ), depending on the direction of i ph. During this interval, the current i dc is zero. A similar condition occurs when both bottom switches T L and T R are turned on. Harmonic Magnitude (p.u.) ( U ) ab h U dc m f = 5, m a = m f m f 3m f Harmonic Order Figure 3-6 Harmonic spectrum of the H-bridge output voltage Three-Phase Two-Level H-Bridge (L-H-Bridge) Topology Circuit Configuration Converters having additional phases can be realized by simply adding multiple numbers of H- bridge converter legs (Figure 3-). A simplified diagram of a three-phase two-level H-bridge converter is shown in Figure 3-7. It contains unidirectional active switches with inverse diodes. i ph,a n U ab U bc i dc,a a U an i dc,b b U bn i dc,c c U cn La Ra,c Lc Rc,a,b Lb Rb La Ra Lb Rb Lc Rc n Figure 3-7 Three-phase configuration for the L-H-Bridges Voltage ource Converter

63 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE witch tates and Commutations In order to produce three levels in each phase leg, the switches are controlled so that only two of the four switches in each phase leg are turned on at any time. The labels Lx and Rx are used to identify the transistors in each phase (x = a, b, c). ince the transistors are always switched in pairs, the complement transistors are labelled Lx and Rx accordingly. The switch positions for three possible states of each phase leg remain the same as for a single-phase H- bridge (see Table 3-). The distribution of the conduction and switching losses are the same as for a single-phase H-bridge (see Table 3- and Table 3-3) ine-triangle Modulation The fundamental modulation concept remains the same as for a single-phase H-bridge. The modulation method for a three-phase L-H-Bridge is shown in Figure 3-8a. It demonstrates that the difference between the three-phase L-H-Bridge and a single-phase H-bridge are the two-phase legs which were added to the first. Furthermore, the reference signals for each phase leg are now displaced by. Therefore, each phase leg is controlled separately by comparing a reference signal U con, x (x=a, b, c) with the triangular waveforms Utri, U tri. The commutations are determined by the comparison of the corresponding carrier signal and the reference signal. The two carrier signals are shifted by T C /. Thus, there are four commutations per phase during one period of the carrier signal. In order to generate the gate signals, the same algorithm as for a single-phase H-bridge can be used Udc U con,x> Utri ( TLx : on,tlx : off ),U con,x> Utri( TRx : off,trx : on) U xn = U U con,x< Utri ( TLx : off,tlx : on ),U con,x< Utri( TRx : on,trx : off ) U xn = else U xn = dc (3-9) Because of the inverse diodes in anti-parallel to the switches, the voltage given by equation (3-9) is independent of the direction of the output current i ph. The output voltage waveforms of the three-phase L-H-Bridge according to Figure 3-7 are depicted in Figure 3-8. The phase voltages (e.g. U an ) comprise three voltage levels, viz. ± / and [see Figure 3-8c], and the line-to-line voltages (e.g. U ab ) comprise five voltage levels, viz. ±, ± /, and (see Figure 3-8d). The harmonic spectrum of the phase voltage and the line-to-line voltage are illustrated in Figure 3-9a and Figure 3-9b respectively (which is drawn for m f = 5 ). Like in a single-phase H- bridge, the first carrier band harmonics of the L-H-Bridge occurs at twice the corresponding switching frequency (f Cb = f C ).

64 4 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE U tri, U tri, U con, a U con, b U con, c (a) - (b) V gl, a V gr, a U an, (c) U an U ab (d) Figure 3-8 Voltage waveforms of the three-phase L-H-Bridge cell: (a) control signals U con,x and triangular signals U tri, and U tri,, (b) gate signals, (c) output phase voltage, (d) output line-to-line voltage

65 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 4 Harmonic Magnitude (p.u.) ( U ) an U dc h m f = 5, m a =.5 (a) -3 Harmonic Magnitude (p.u.) 3 m f m f 3m f ( U ) ab h U dc m f = 5, m a =.5 (b) -3 m f m f 3m f Harmonic Order Figure 3-9 Harmonic spectrum of the three-phase L-H-Bridge cell: (a) phase output voltage, (b) line-to-line output voltage Introduction to the eries Connected Two-Level H-Bridge Voltage ource Converter (CLHB VC) In traditional converter topologies such as the L-VC or 3L-NPC VC, the device with the maximum available voltages (e.g. 6.5kV IGBT) is connected in series to reach the required lineto-line output voltage (U ll > 3.3kV and U ll > 4.6kV). The concept of the generalized eries Connected Two-Level H-Bridge Voltage ource Converter (CLHB VC) is shown in Figure 3-3. It is based on series connected isolated H-bridge cells rather than series connected devices. The patent for the series connected isolated H-bridge cell was originally obtained by Robicon [9]. The CLHB VC is a popular power converter for motor drives [4], [46], [9], [3], power supplies [49], [3], and ac power systems [5], [54], [57], [58]. The CLHB VCs will be designated according to the voltage levels of the individual H- bridge cells. The step of the output voltage is comparatively small and equal to the dc bus voltage of one H-bridge cell (order of 6 volts for a 46-volt input). To attain the rated medium output voltage, all single-phase low-voltage H-bridge cells are connected in series, only using low-cost low-voltage devices (e.g..7kv IGBT). The total virtual dc link voltage,tv differs according to the necessary line-to-line output voltage of the converter. This voltage depends on the number of series connected H-bridges p and is determined by U = p U (3-3) dc,tv dc,hb Using the same dc link voltage,hb for each H-bridge cell, the converter synthesizes an output phase voltage (e.g. U an, U bn, U cn ) U = U + U U (3-3) xn xn xn pxn

66 4 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE U an i ph,a n a U pan U ab α p pla pra 3 pla pra b α p 3 plb plb prb prb U pbn c α p plc prc U pcn 3 plc prc 3 α 3 α La Ra La Ra U an Lb Rb U bn 3 Lb Rb α Lc Rc U cn 3 Lc Rc α La Ra U an 3 La Ra α Lb Rb U bn 3 α Lb Rb Lc Rc U cn 3 Lc Rc n Figure 3-3 eries Connected Two-Level H-Bridge Voltage ource Converter with p series H- bridge cells per phase with a number of output phase voltage levels N=p+ (3-3) and a number of output line-to-line voltage levels Nll = N (3-33) The number of series H-bridge cells is chosen typically from to 5, for the worldwide standard machine voltages of.3 to 7.kV. With two power cells per phase (p = ), the circuit of Figure 3-3 can produce five distinct phase voltage levels (N = 5). With three, four, and five cells per phase; 7, 9, and distinct phase voltage levels are available. There are several families of H- bridge cells with the same input voltage (46, 63, and 69) that are capable to produce (8,

67 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 43, and ) line-to-line output voltages (per cell) for rated currents ranging from 7 to amperes [35]. For the modulation, two triangular carrier signals are needed for each cell, which is the same as in the single-phase H-bridge. It should be noted that the pair of triangular carrier signals applied in each cell have a phase shift of 8 /p, in contrast to the triangular carrier of the previous H- bridge cell, with the first H-bridge cell as reference cell. With this modulation, the frequency of the first harmonics carrier band of the output voltage is equal to f = p f (3-34) Cb C where f C denotes the carrier frequency. Due to many different output voltage levels and the high frequency f Cb, the output voltage and current harmonics are low; and therefore, the filtering processes are easier. Each additional level is another "degree of freedom" in reducing the output harmonics. It is possible to add an extra tier of H-bridge cells that enables the drive to operate with an increased output voltage (p+)/p capability. ince the output voltage is distributed uniformly between the H-bridge cells, there is some redundancy which allows the drive to operate with one shortened H-bridge. If an H-bridge fails, its output is shortened by the controller without any user intervention. The drive remains at work and operates with nominal output voltage. The maximum input and output voltages of each H-bridge cell are equal to the instantaneous dc link voltage, according to Figure 3-. Therefore, the dc link capacitor acts as a large snubber for all the devices. All H-bridge cells carry the same current at the output fundamental voltage. This results in an equal power among all H-bridge cells, a simple control structure, and modularity of the control. Although the H-bridge could be constructed with a variety of low voltage semiconductor devices, the LV-IGBT is an excellent choice due to its extremely low gate power and fast switching behaviour. Robicon utilizes low-cost low-voltage IGBTs, e.g. 7V, for its medium voltage drives [36]. The drive can produce.3kv, 3.3kV, 4.6kV, and 6kV line-to-line voltages with two, three, four, and five H-bridge cells in series per phase. Other important advantages of this drive are a minimal common mode voltage and a potentially low dv/dt in the output voltages. However, the dc link supply for each H-bridge cell must be provided separately. This is accomplished by multiple isolated secondary windings of an integral isolation transformer. The transformer is more complex and expensive than customary, but it performs several very important functions. First, it ensures that any common mode voltage does not have to be supported by the motor insulation. econd, by the phase shift 36 α = p 6 p (3-35) between the secondary windings, it is possible to cancel most of the harmonic currents drawn by the individual power cells so that the primary currents are nearly sinusoidal (the pulse number at the primary is equal to 6p). The transformer impedance is consciously made larger than normal to limit the inrush current and to reduce the harmonics. Due to the excellent harmonic performance of the grid side, the reduced input filter compensates the extra cost of the transformer. The transformer efficiency is typically 98.5%. Table 3-4 summarizes the quantities comparison for this topology with different H-bridge cells per phase.

68 44 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE Table 3-4 Quantities comparison of the CLHB VC Number of series connected H-Bridges p p Number of phase output voltage level N p+ Number of line-to-line output voltage level N ll p+ Number of dc-link capacitors p Transformer phase displacement α p 3 5 6/p Number of the carrier signals p Carrier phase shift displacement /p eries Connected Two-Level H-Bridge Voltage ource Converter with Two Power Cells per Phase Leg (5L-CLHB VC) Circuit Configuration Figure 3-3 shows the 5L-CLHB VC utilizing two three-level H-bridge cells in series per phase. This structure may be related to Figure 3-3 regarding the points labelled a and n. It contains 4 unidirectional active switches with inverse diodes, 6 separated dc link capacitors, and a -pulse transformer with two secondary windings which are shifted 3 with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of,hb, the resulting converter can operate with five output phase voltage levels (e.g. U xn ). a 3 La Ra U an b 3 3 La Ra Lb Rb U bn c 3 Lb Rb 3 3 Lc Rc Lc Rc U cn 3 La Ra U an 3 La Ra Lb Rb U bn 3 Lb Rb Lc Rc U cn 3 Lc Rc n witch tates and Commutations Figure 3-3 5L-CLHB Voltage ource Converter In order to produce five levels, the switches are controlled so that only two of the four switches in each H-bridge cell are turned on at any time. The labels plx and prx are used to identify the switches as well as the switches logic ( = on and = off, p =, ). ince the

69 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 45 switches are always switched in pairs, the complement switches are labelled plx and prx accordingly. In order to prevent a short circuit, the complementary leg switches are not switched simultaneously. In other words, in whatever state that the top switch is, the bottom switch must be in the opposite. The switch positions for five possible states of each phase leg as well as the individual H-bridge voltage are given in Table 3-5. It shows that there are six and four redundant possibilities for switching U xn = and U xn = ±,HB. Figure 3-3 illustrates the transitions between the output voltage steps. The number of commutations between each two adjacent voltage levels are marked in grey. These critical transitions can be used to achieve the full control of the voltages. As can be seen from this Figure, some of these transitions force three switches to switch. For the following discussion of commutations, only one of the transition states is assumed, as indicated in bold line in Figure 3-3. The current paths for positive and negative phase currents i ph are depicted in Figure If either the diagonally opposite semiconductors ( Lx, Rx, Lx, Rx ) or ( Lx, Rx, Lx, Rx ) are turned on, i.e. either two active switches or two diodes, then the phase-to-ground output voltage will lead to,hb or -,HB (Table 3-5). The positive and the negative states,hb and,hb can be generated, if either for example,,,, are turned on (Table 3-5). the switches ( Lx, Rx, Lx, Rx ) or ( Lx Rx Lx Rx ) The zero state can be generated if the upper switches ( ),,, in both H-bridges Lx Rx Lx Rx lie within the current path. Therefore, each phase-to-ground can produce five distinct voltage levels. It should be noted that each of the switches must block the dc link voltage,hb (e.g. /4), compared to / in the 3L-NPC and 3L-FLC converters, to achieve the same output voltage. The distribution of the conduction and switching losses are the same as for a single-phase H- bridge converter (refer to section 3.4..). Table 3-5 witch positions for the 5L-CLHB VC Lx Rx Lx Rx U xn U xn U xn tate,hb,hb,hb = /,HB 3,HB 4,HB 5,HB ,HB,HB,HB -,HB -,HB 3 -,HB 4 -,HB 5 -,HB,HB = /4 -,HB = - /4 6 -,HB -,HB -,HB = - /

70 46 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE U xn = U tate dc,hb U xn = U tate dc,hb U = xn tate Number of the commutations between states U xn = U tate dc,hb U xn = U tate 6 dc,hb Figure 3-3 Transitions between voltage levels for the 5L-CLHB VC ine-triangle Modulation There are different PWM methods which have been extended for the use in an H-bridge converter by applying multiple carriers. These methods are described in many publications in the technical literature [8], [43], [5], [55], [59], [6], [6]. They can be categorized into three groups: Phase hifted (P), Carrier Disposition (CD), and Hybrid (H) method. These methods are described in Appendix in detail. The following subsection only discusses the P method due to its balanced switch utilization and simple implementation. This PWM method uses four carrier signals of the same amplitude and frequency, which are phase shifted by T C /4 with respect to each other, where T C is the period of the carrier signal. The modulation method for the 5L-CLHB VC is shown in Figure 3-34a. The triangular carriers U tri,l, U tri,r for the first H-bridge cell and the triangular carriers U tri,l, U tri,r for the second H-bridge cell are considered (one carrier signal for each column). The commutations are determined by the comparison of the corresponding carrier signal and the reference signal U con,x (x = a, b, c). There are eight commutations per phase during one period of carrier signal T C. The gate signals can be produced by the following algorithm ( ) ( ) ( ) ( ) U con, x > Utri, Lp plx : on, plx : off or Ucon, x < Utri, Lp plx : off, plx : on U con, x > Utri, Rp prx : on, prx : off or U con, x < Utri, Rp prx : off, prx : on p =, (3-36)

71 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 47 Lx Rx Lx Rx U = U / 4 dc,hb dc,hb Lx Rx Lx Rx Lx Rx Lx Rx U = U / 4 dc,hb dc,hb Lx Rx Lx Rx tate tate 4 Lx Rx Lx Rx,HB,HB Lx Rx Lx Rx Lx Rx Lx Rx,HB,HB Lx Rx Lx Rx tate 7 tate 4 Lx Rx,HB Lx Rx Lx Rx,HB Lx Rx tate 6 Figure 3-33 Conduction path of the 5L-CLHB VC (according to Figure 3-3)

72 48 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The resulting gate signals for the 5L-CLHB VC are shown in Figure 3-34b, which directly yields the switch states of Lx, Rx, Lx and Rx. The output voltage waveforms of the 5L-CLHB VC according to Figure 3-3 are depicted in Figure 3-34c to Figure 3-34e. The converter ground n is isolated from the load neutral point n and each phase voltage U an, U bn, and U cn is directly controlled by the ac output of the individual multi-level H-bridge cells. Due to the same dc voltage value of each cell (i.e.,hb = /4), the phase output voltage of the 5L-CLHB converter, e.g. U U dc ( conx, > tril,, conx, > trir,, conx, > tril,, conx, > trir, ) dc if ( Ucon, x > Utri, L, Ucon, x < Utri, R, Ucon, x > Utri, L, Ucon, x > Utri, R ) 4 U = if ( Ucon, x > Utri, L, Ucon, x < Utri, R, Ucon, x > Utri, L, Ucon, x < Utri, R) xn U 4 U dc if U U U U U U U U ( con, x > tri, L, con, x < tri, R, con, x < tri, L, con, x < tri, R) if U U U U U U U U dc if ( Ucon, x < Utri, L, Ucon, x < Utri, R, Ucon, x < Utri, L, Ucon, x < U tri, R ) (3-37) comprises five voltage levels, viz. ± /, ± /4, and (see Figure 3-34c). The line-to-line output voltages of the 5L-CLHB converter, e.g Uab = Uan U bn (3-38) comprise nine voltage levels, viz. ±, ±3 /4, ± /, ± /4, and (see Figure 3-34d). The load phase voltages U an, U bn, and U cn, as depicted in Figure 3-34e, may be expressed in terms of the phase voltages by [] Uan Uan U bn U = bn 3 (3-39) U cn U cn The load phase voltages comprise thirteen voltage levels, viz. ±7 /, ± /, ±5 /, ± /3, ± /4, ± /6, and. Table 3-6 summarizes the output voltages and their corresponding voltage levels. The spectrum of the phase voltage and line-to-line output voltage waveforms are depicted in Figure 3-35a and Figure 3-35b respectively (at m a =. 5 and m f = 5 ). As can be seen in these Figures, the first carrier band of the output voltages is centred around four times the carrier frequency (f Cb = 4f C ) (equation 3-33). Hence, an output filter of the 5L-CLHB VC would be smaller than the corresponding filters of conventional converters such as the 3L-NPC VC [5]. Table 3-6 The output voltage levels of the 5L-CLHB VC Output Voltage 3 /4 /3 7 / / 5 / /3 /4 /6 U xn ± ± U ab ± ± ± ± U xn ± ± ± ± ± ±

73 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 49 U con, a U tri,l U tri,r U tri,l U tri,r / (a) - / - / / 4 V g, R V gl, V g, R V g, L U an (b) (c) - / 4 - / U an, / - / U ab (d) - 3 /5 /5 /5 - /5 - /5-3 / Figure 3-34 Voltage waveforms of the 5L-CLHB VC: (a) control signals U con,x and triangular signals U tri,l, U tri,l, U tri,r and U tri,r, (b) gate signals, (c) output phase-toground voltage U an, (d) output line-to-line voltage U ab, (e) output load-phase voltage U an U an (e)

74 5 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE Harmonic Magnitude (p.u.) - - ( U ) U an dc h m f = 5, m a =.5 (a) -3 3 m f m f 3m f 4m f Harmonic Magnitude (p.u.) - - ( U ) U ab dc h m f = 5, m a =.5 (b) -3 m f m f 3m f 4m f Harmonic Order Figure 3-35 Harmonic spectrum of the 5L-CLHB VC eries Connected Two-Level H-Bridge Voltage ource Converter with Three Power Cells per Phase Leg (7L-CLHB VC) Circuit Configuration The structure of the 7L-CLHB VC utilizing three H-bridge cells in series per phase leg is similar to Figure 3-3, but with p = 3. It contains 36 unidirectional active switches with inverse diodes and 9 separated dc link capacitors as well as an 8-pulse transformer with three secondary windings which are shifted with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of,hb, the resulting converter can operate with seven output voltage levels (e.g. U xn ) by using the combinations of the three H-bridge converter voltages witch tates and Commutations The fundamental concepts for the 7L-CLHB VC remain the same as for the 5L-CLHB VC. The total number of switch states, which includes all redundancies, calculates to 6 n p sw = = = 64 (3-4) with p being the number of H-bridge cells per phase. The phase output voltages (e.g. U xn ) ±,HB (± /3 according to equation (3-3)), ±,HB (± /6), and can be generated with more than one combination, as given in Table 3-7. It shows that there are different redundant possibilities to achieve the same output voltages. For a positive phase current, if either all diagonally opposite switches ( plx, prx : p 3,, ) ( plx, prx : p 3,, ) = or = are turned on, then the phase output voltage will lead to +3,HB =

75 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 5 + / or -3,HB = + /. The positive and negative states +,HB and,hb can be, :p = or or 3 or generated, if either only one pair of switches ( plx prx ) ( plx, prx :p or or 3) = is turned off. In order to produce the positive state +,HB and the negative state,hb, only one out of three diagonally arranged switches must be turned on. The zero state can be created if all upper or lower switches in the three H-bridges lie within the current path. Therefore, each phase can produce seven distinct voltage levels, viz. ± /, ± /3, ± /6, and (Table 3-7). There are some redundancies to produce the output voltage levels + /3, + /6, and. Although the same output voltages are generated, the output current i ph flows in different paths. This means that a different current flows in different dc link capacitors. Consequently, the dc link capacitors have different voltage profiles. The redundancies can be used to adjust the individual capacitor voltages and to balance these voltages. To achieve minimal operating losses and power balancing, the most suitable redundancy should be selected. Regarding the optimization concern, the selected operation modes used to generate the positive and zero output voltages for a 7L-CLHB VC. U con,a U tri,l U tri,l U tri,l3 (a) - U tri,r U tri,r U tri,r Figure 3-36 Pulse width modulation for the 7L-CLHB VC: (a) control signals U con,a and triangular signals U tri,lp and U tri,rp, (b) gate signals (m f = 3) Table 3-7 Number of redundancies in each phase voltage level of the 7L-CLHB VC Phase output voltage level / /3 /6 - /6 - /3 - / Number of redundancies at level V g, L V g, R V gl, V g, R V gl, 3 V g, R 3 (b)

76 5 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The redundancy combination used to produce the output voltages of +3,HB, +,HB, +,HB, and are one, three, three, and one respectively (Table 3-7). This also applies to negative output voltages. Therefore, the total number of switch states for the 7L-CLHB VC is 5, which breaks down to seven for the positive voltage, seven for the negative voltage, and one for the zero voltage. It should be noted that each switch of the H-bridge cells must block the dc link voltage /6, compared to the /4 in the 5L-CLHB VC, to achieve the same output voltage. witching losses are caused by the commutation processes between the different switch states. Only the two complement switches in each H-bridge cell are involved in the commutations ine-triangle Modulation The fundamental concept is the same as the 5L-CLHB converter. The P modulation method uses six carrier signals of the same amplitude and frequency, which are phase shifted by T C /6 with respect to each other, where T C is the period of the carrier signal. The modulation method for the 7L-CLHB VC is shown in Figure 3-36a. Triangular carriers ( UtriL,, U trir, ), ( Utri, L, U tri, R), and ( Utri, L3, U tri, R3) are considered for the first, second, and third H-bridge cell respectively (one carrier signal for each leg). The commutations are determined by the comparison of the corresponding carrier signal and the reference signal Ucon, x ( x= abc,, ). There are twelve commutations per phase during one period of the carrier signal T C. Gate signals can be produced by ( ) ( ) ( ) ( ) U con,x> Utri,Lp plx : on, plx : off or U con,x< Utri,Lp plx : off, plx : on U con,x> Utri,Ri prx : on, prx : off or U con,x< Utri,Rp prx : off, prx : on p = 3,, (3-4) The resulting gate signals for the 7L-CLHB VC are shown in Figure 3-36b, which directly yield the switch states of Lx, Rx, Lx, Rx, 3Lx and 3Rx respectively. U xn (,,,, 3,,, 3 ) (,,,, 3,,,, 3 ) (,,, UtriL, 3, UtriR,, Uconx, < UtriR,, UtriR, 3 ) ( con, x tri, L tri, L tri, L3 con, x tri, R tri, R tri, R3 ) (,,,, 3, nx, > UtriR,, UtriR, 3 ) (,,,, 3,,,, 3) (,,,, 3,,, 3 ) Udc if Ucon x > Utri L, Utri L, Utri L, Utri R, Utri R, Utri R Udc 3 if Uconx> UtriL, UtriL, UtriL, UtriR, UtriR, Uconx< UtriR Udc 6 if Uconx> UtriL, UtriL, = if U > U, U, U, U < U, U, U Udc 6 if Ucon x < Utri L, Utri L, Utri L, Utri R, Uco Udc 3 if Ucon x < Utri L, Utri L, Utri L, Utri R, Utri R, Ucon x > Utri R Udc if Ucon x < Utri L, Utri L, Utri L, Utri R, Utri R, Utri R (3-4) The output voltage waveform of the 7L-CLHB VC is depicted in Figure imilar to the 5L-CLHB VC, the converter ground n is isolated from the load neutral point n and each phase-to-ground voltage U an, U bn, and U cn is directly controlled by the ac output of the individual multi-level H-bridge cells. Considering the same dc voltage value,hb = /6 for each cell (according to equation 3-3), the phase output voltage of the 7L-CLHB VC

77 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 53 comprises seven voltage levels, viz. ± /, ± /3, ± /6, and (see Figure 3-37b and Table 3-8). The line-to-line output voltages of the 7L-CLHB VC comprise thirteen voltage levels, viz. ±, ±5 /6, ± /3, ± / ± /3, ± /6, and (see Figure 3-37c and Table 3-8). The load phase voltage U an is depicted in Figure 3-37d. It comprises 5 voltage levels, viz. ± /3, ± /8, ±5 /9, ± /, ±4 /9, ±7 /8, ± /3, ±5 /8, ± /9, ± /6, ± /9, ± /8, and (Table 3-8). (a) / - / - / /4 U an (b) - /4 U an, - / / U ab (c) - / - 3 /5 /5 /5 - /5 - /5-3 / Figure 3-37 Voltage waveforms of the 7L-CLHB VC: (a) reference and triangular signals, (b) output phase voltage U an, (c) output line-to-line voltage U ab, (d) output loadphase voltage U an (m f = 5) U an (d)

78 54 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE Table 3-8 The output voltages and their corresponding levels of the 7L-CLHB VC output voltage levels U xn U ab U xn ± 5 /6 ± /3 ± ± /8 ± 5 /9 ± / ± ± ± 4 /9 ± 7 /8 ± /3 ± ± ± 5 /8 ± /9 ± /6 ± ± ± /9 ± /8 ± The spectrum of the phase-to-ground and the line-to-line output voltage waveforms are depicted in Figure 3-38a and Figure 3-38b respectively (at m a =.5 and m f = 5). It becomes apparent that the first carrier band of the output voltages is centred around six times the carrier frequency (f Cb = 6f C ), according to equation Harmonic Magnitude (p.u.) - - ( U ) U an dc h m f = 5, m a =.5 (a) Harmonic Magnitude (p.u.) -3 3 m f m f 3m f 4m f 5m f 6m f - - ( U ) U ab dc h m f = 5, m a =.5 (b) -3 m f m f 3m f 4m f 5m f 6m f Harmonic order Figure 3-38 Harmonic spectrum of the phase voltage (a) and line-to-line voltage (b) of the 7L- CLHB VC eries Connected Two-Level H-Bridge Voltage ource Converter with four Power Cells per Phase Leg (9L-CLHB VC) Figure 3-39 represents the structure of the 9L-CLHB VC utilizing four H-bridge cells in

79 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 55 series per phase leg p = 4. It contains 48 unidirectional active switches with inverse diodes, separated dc link capacitors as well as a 4-pulse transformer with three secondary windings which are shifted 5 with respect to each other. If the dc voltage of each H-bridge cell is set to the same value of,hb, the resulting converter can operate with nine voltage levels by using the combinations of the four H-bridge converter voltages. α 4 a i ph,a 4La 4Ra U 4an U an U ab n 3 4La 4Ra b α 4 3 4Lb 4Rb 4Lb 4Rb U 4bn c α 4 4Lc 4Rc U 4cn 3 4Lc 4Rc α 3 3La 3Ra U 3an 3 3La 3Ra α 3 3Lb 3Rb U 3bn 3 3Lb 3Rb α 3 3Lc 3Rc U 3cn 3 Lc Rc 3 α La Ra U an 3 La Ra α Lb Rb U bn 3 Lb Rb α Lc Rc U cn 3 Lc Rc i da α 3 La Ra La Ra U an α Lb Rb U bn 3 α Lb Rb Lc Rc U cn 3 Lc Rc n Figure 3-39 The 9L-CLHB Voltage ource Converter

80 56 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The fundamental concepts of commutations are the same as for the 7L-CLHB VC. There are different redundant possibilities to generate the phase output voltage, (e.g. U xn ), ±3,HB, ±,HB, ±,HB, and. The redundancies can be used to adjust the individual capacitor voltages and to balance cell power. Considering the optimal redundancies, the total number of switch states can be calculated by 5 p+ = = 3 (3-43) In order to generate the gate signals, the P modulation method is used. The commutations are determined by the comparison of the eight carrier signals, one carrier signal for each leg, and the reference signal Ucon, x ( x= abc,, ). The carrier signals are phase shifted by T C /8 with respect to each other. The modulation method for the 9L-CLHB VC is shown in Figure 3-4a. There are sixteen commutations per phase (four commutations per cell) during one period of carrier signal T C. The gate signals can be produced by ( ) ( ) ( ) ( ) U con,x> Utri,Lp plx : on, plx : off or U con,x< Utri,Lp plx : off, plx : on U con,x> Utri,Ri prx : on, prx : off or U con,x< Utri,Rp prx : off, prx : on p = 34,,, (3-44) The resulting gate signals for the 9L-CLHB VC are depicted in Figure 3-4b, which directly yield the switch states of Lx, Rx, Lx, Rx, 3Lx, 3Rx, 4Lx and 4Rx respectively. The output voltage waveform of the 9L-CLHB VC is illustrated in Figure 3-4. Each phase voltage U an, U bn, and U cn is directly controlled by the ac output of the individual multi-level H-bridge cells. Considering the same dc voltage value,hb = /8 for each cell, according to equation 3-3, the phase output voltage U xn of the 9L-CLHB VC, e.g. U xn (,,,, 3, 4,,, 3, 4 ) (,,,, 3, 4,,, 3,, 4 ) ( conx, tril, tril, tril, 3 tril, 4 trir, trir, conx, trir, 3 trir, 4 ) (,,,, 3, 4,,,, 3, 4 ) ( con, x tri, L tri, L tri, L3 tri, L4 con, x tri, R tri, R tri, R3 tri, R4 ) (,,,, 3, 4,,,, R3, Utri, R4 ) (,,,, 3, 4,,,, 3, 4 ) (,,,, 3, 4,,, 3 nx, > UtriR, 4 ) (,,,, 3, 4,,, 3, 4 ) Udc if Ucon x > Utri L, Utri L, Utri L, Utri L, Utri R, Utri R, Utri R, Utri R 3Udc 8 if Ucon x > Utri L, Utri L, Utri L, Utri L, Utri R, Utri R, Utri R, Ucon x < Utri R U dc 4 if U > U, U, U, U, U, U, U < U, U Udc 8 if Uconx> UtriL, UtriL, UtriL, UtriL, UtriR, Uconx< UtriR, UtriR, UtriR = if U > U, U, U, U, U < U, U, U, U Udc 8 if Ucon x < Utri L, Utri L, Utri L, Utri L, Utri R, Ucon x > Utri R, Utri Udc 4 if Ucon x < Utri L, Utri L, Utri L, Utri L, Utri R, Utri R, Ucon x > Utri R, Utri R 3Udc 8 if Ucon x < Utri L, Utri L, Utri L, Utri L, Utri R, Utri R, Utri R, Uco Udc if Ucon x < Utri L, Utri L, Utri L, Utri L, Utri R, Utri R, Utri R, U tri R (3-45) comprises nine voltage levels, viz. ± /, ±3 /8, ± /4, ± /8, and (see Figure 3-4b and Table 3-9). The line-to-line output voltages of the 9L-CLHB VC comprise seventeen voltage levels, viz. ±, ±7 /8, ±3 /4, ±5 /8, ± /, ±3 /8, ± /4, ± /8, and (see Figure 3-4c and Table 3-9). The load phase voltage U an of the 9L-CLHB VC comprises 9 voltage levels (see Figure 3-4d and Table 3-9).

81 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 57 U con,a U tri,l U tri,l U tri,l3 U tri,l4 U tri,r U tri,r U tri,r3 U tri,r4 (a) - V g, L (b) V g, R V gl, V g, R V gl, 3 V gl, 4 V g, R Figure 3-4 Pulse width modulation for the 9L-CLHB VC: (a) control signals U con,a and triangular signals U tri,lp and U tri,rp, (b) gate signals (m f = 3) Table 3-9 The output voltages and their corresponding levels of the 9L-CLHB VC output voltage levels U xn U ab U xn ± 7 /8 ± 3 /4 ± 5 /8 ± ± 7 / ± 3 /4 ± / ± ± ± /4 ± 5 / ± 3 /8 ± ± ± /3 ± 7 /4 ± /4 ± ± ± 5 /4 ± /6 ± /8 ± ± ± / ± V g, R 4

82 58 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE (a) - / /4 U an (b) - /4 U an, - / / U ab (c) - / - 3 /5 /5 /5 - /5 U an (d) - /5-3 / Figure 3-4 Voltage waveforms of the 9L-CLHB VC: (a) reference and triangular signals, (b) output phase voltage U an, (c) output line-to-line voltage U ab, (d) output loadphase voltage U an (m f = 5) The spectrum of the phase and line-to-line output voltage waveforms are depicted in Figure 3-4a and Figure 3-4b respectively (at m a =. 5 and m f = 5 ). As can be seen in these Figures, the first carrier band of the output voltages is centred around eight times the carrier frequency (f Cb = 8f C ), according to equation 3-33.

83 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 59 Harmonic Magnitude (p.u.) ( U ) - - an h U dc m f = 5, m a = m f m f 3m f 4m f 5m f 6m f 7m f 8m f Harmonic Magnitude (p.u.) - - ( U ) U ab dc h m f = 5, m a =.5-3 m f m f 3m f 4m f 5m f 6m f 7m f 8m f Harmonic order Figure 3-4 Harmonic spectrum of the phase voltage U an (a) and the line-to-line voltage U ab (b) of the 9L-CLHB VC N-Level eries Connected 3-Level H-Bridge Voltage ource Converter (NL- C3LHB VC) [47], [] The topologies summarized above constitute the basic structures of the multi-level converters. To reduce the number of separate dc sources for high-voltage high-power applications, the CLHB VC can be modified by replacing its conventional two-level converters (L-H- Bridge) with combinations of multi-level converters (3L-H-Bridge). These combinations can be considered as having NL-C3LHB VC because this includes multi-level cells as the building block of the cascaded converter. Figure 3-43 represents the structure of the NL- C3LHB VC, utilizing p 3L-H-Bridge cells in series per phase leg. The dc link voltage depends on the number of the series connected 3L-H-Bridges and is determined by Udc p Udc, 3L HB = (3-46) Using the same dc link voltage for each H-bridge cells,3l-hb, the converter synthesizes an output phase voltage (e.g. U an, U bn, U cn ) U = U U (3-47) xn xn pxn with a number of output phase voltage levels N = 4p+ (3-48) Due to a higher number of voltage levels, compared to the CLHB VC, this converter generates an output voltage with improved harmonic performance. The advantage of the topology is that it needs less separate dc sources. However, the modulation is more complicated due to the 3L-H-Bridge structure.

84 6 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE a i ph,a U an n α p 3 pa p a pa p a pa p a U pan U ab b pa p a U pbn c α p pb p b pb p b 3 pb p b U pcn pb p b α p 3 pc p c pc p c pc p c pc p c 3 α a a a a U an 3 a a a a U bn α b b b b U cn 3 b b b b α c c c c 3 c c c c Figure 3-43 NL-C3LHB VC with p series 3L-H-Bridge cells per phase Circuit Configuration of Five-Level eries Connected 3-Level H-Bridge Voltage ource Converter (5L-C3LHB VC) The circuit of Figure 3-44 shows the basic topology of a single-phase 5L-C3LHB VC [46], [47], []. This converter was constructed from two halves of a three-level diode-clamped converter connected to the same bank of series capacitors to form a five-level converter. This topology is presently being produced by ABB and General Electric in their medium voltage (46V) drive product [], [46]. It contains 8 unidirectional active switches with inverse n

85 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 6 diodes and 4 neutral point clamp diodes per phase. If a NPC single-phase (3L-H-Bridge) replaces the conventional full-bridge cell (L-H-Bridge), the voltage level is effectively doubled for each cell. Thus, to achieve the same voltage levels N for each phase, only (N-)/4 separate dc sources are needed for one phase leg converter, whereas (N-)/ separate dc sources are needed for the NL-CLHB converter. Although the converter in Figure 3-44 is a five-level structure, the concept may be expanded to any odd number of voltage levels [33]. Using the same philosophy, a full-bridge five-level phase leg can be built, based on the three-level flying capacitor topology, but in this section only the 5L-C3LHB diode-clamped converter will be discussed. M i dc a a a D a D a U an C U c a a,3l-hb M i dc n a a C U c D a D a a a M i dco Figure 3-44 Five-level C3LHB diode clamped topology (5L-C3LHB) witch tates and Commutations By suitably switching the converter transistors, the points a and n in Figure 3-44 may be connected to any of the points M, M, and M [33]. In order to produce five levels in each cell, the switches are controlled like in the conventional 3L-NPC VC, which was explained in section 3... Four of the eight switches in each cell are turned on at any time. The switch positions for five possible states of each cell are given in Table 3-, where and designate the on- and off state of the respective switch. Assuming that the dc voltage is set to and each capacitor remains charged to half of the dc voltage, the converter output voltage U an, according to equation (3-46), may be set to the five distance levels ±, ± /, and (Table 3-). Capacitor voltage balancing in this topology may be accomplished in a straightforward way through redundant state selection [4]. As can be seen in Figure 3-44, switching to output voltages of ± and will not result in a current draw from the neutral point M and therefore will not affect the capacitor voltage balance. However, when a voltage of ± / is required, the neutral junction will be utilized. As an example of how the redundant state switching is accomplished, consider the case where an output voltage of / is desired and the phase current is positive. One possibility is to switch point a to junction M and point n to M. This choice will tend to charge the lower capacitor since the current is flowing into the neutral junction. The other possibility is to switch point a to junction M and point n to junction M. This will result in a current out of the neutral junction which will discharge the lower capacitor. The choice can then be readily made, depending on whether the lower capacitor is under- or over-charged relative to the upper one.

86 6 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE The commutation processes between the different switch states are the same as in the conventional 3L-NPC VC, which was explained in section 3... The distribution of the conduction and switching losses are summarized in Table 3- and Table 3- respectively. It is remarkable that four semiconductors lie within the current path in any switch state, either four active switches or four diodes. Table 3- witch positions for the 3L-H-Bridge converter tate a a a a U am / / / - / - / - / U nm - / - / / - / / / U U ab dc / - / - Table 3- Conduction losses in the 3L-H-Bridge converter witches witches Half-Bridge a Half-Bridge a Half-Bridge a Half-Bridge a tate Positive phase current Negative phase current + (U an = ) T a,t a T a,t D a Ta,D Ta D Ta,D Ta (U an = ) D a,t a T a,d a T a,d D a a,t a - (U an = - ) D Ta,D D Ta Ta,D Ta T a,t T a a,t a Table 3- witching losses in the 3L-H-Bridge converter witches witches Half-Bridge a Half-Bridge b Half-Bridge a Half-Bridge b tate Positive phase current Negative phase current + T,D T,D D,T D,T a a T,D a Ta a a T,D a Ta Ta a D,T a a Ta a D,T a a ine-triangle Modulation Gate signals for one half-bridge are produced by comparing one control voltage waveform with two triangular voltage waveforms U tri,up and U tri,low (which is drawn for m f = 5 ), as shown in Figure 3-45a. The upper and lower carrier band are in phase but displaced vertically. However, the triangular signals in each carrier band are shifted by T C / with respect to each other. In order to trigger the switches, the following algorithm can be used. The comparison of U con with U tri,up,a and U tri,low,a results in the following logic signals to control the switches in the first leg

87 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 63 U dc if ( U con > and U con > Utri,up,a ) ( a, ) a :on, a, a :off U am = if ( U con > and U con < Utri,up,a ) ( a, ) a :on, a, a :off U am = if ( U con < and U con > Utri,low,a ) ( a, ) a :on, a, a :off U am = U if ( U con and U con Utri,low,a ) ( a, ) a : on, a, a : off U am < < = dc (3-49) For controlling the second leg switches, U tri,up,b and U tri,low,b are compared with the same control signal, which yields the following U if ( U con > and U con > Utri,up,b ) ( a, ) a : on, a, a : off U n M = if ( U con > and U con < Utri,up,b ) ( a, ) a :on, a, a :off U n M = if ( U con < and U con > Utri,low,b ) ( a, a :on, a, a :off ) U nm = U dc if ( U con < and U con < Utri,low,b ) ( a, ) a :on, a, a :off U n M = dc (3-5) Therefore, the leg voltages (e.g. U am and U n M ) comprise three voltage levels, viz. ± / and (see Figure 3-45c and Figure 3-45e). The output voltage of the 5L-C3LHB VC, e.g. U = U U (3-5) ab am n M ( ) ( con > con > tri,up,a con < tri,up,b ) ( U con and U con U tri,up,a and U con Utri,up,b ) > < > ( U con > and U con < U tri,up,a and U con < Utri,up,b ) ( U con < and U con > U tri,low,a and U con > Utri,low,b ) ( con < con > tri,up,a con < tri,up,b ) ( U con < and U con < U tri,low,a and U con > Utri,low,b ) ( con < ) if U con > and U con > U tri,up,a and U con > Utri,up,b U ab = U dc U and U U and U U U dc if U ab = if U ab = U and U U and U U U dc if Uab = if U and U con < U tri,low,a and U con > Utri,low,b U ab = U dc (3-5) comprise five voltage levels, viz. ±, ± /, and (see Figure 3-45f). The output voltage waveforms of the 5L-C3LHB VC according to Figure 3-44 are depicted in Figure The harmonic spectrum of the output voltage U ab is illustrated in Figure 3-46 (which is drawn for m f = 5 ). It can be seen in this Figure that the first carrier band of the output voltage is centred around two times the carrier frequency (f Cb = f C ), according to equation 3-33.

88 64 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE U tri,up,a U con U tri,up,b U tri,low,a U tri,low,b (a) - V g,t a (b) V g,t a / U am (c) - / V g,t a (d) V g,t a / - / U nm (e) / - / U an (f) Figure 3-45 Voltage waveforms of the 5L-C3LHB VC: (a) control signal U con and triangular signals, (b) a-leg gate signals, (c) a-leg phase voltage, (d) n -leg gate signals, (e) n -leg phase voltage, (f) converter output voltage u an

89 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE 65 Harmonic Magnitude (p.u.) ( U ) U ab dc h m f = 5, m a =.5 3 m f m f 3m f Harmonic Order Figure 3-46 Harmonic spectrum of the 5L-C3LHB VC Conclusion Multi-level converters are becoming more attractive in high voltage and high efficiency applications. Because of their multi-step output voltage waveforms, the total harmonic distortion (THD) of the multi-level converter voltages is relatively low compared to the L- VC. Moreover, the effective switching frequency of the multi-level converters is a function of its number of voltage levels. In other words, to achieve the same voltage THD, a higherlevel converter can operate at a lower switching frequency. Obviously, the theoretical superiority of a multi-level converter is proportional to its number of voltage levels assuming ideal switches. However, the number of voltage levels is limited by its control complexity, complication of the system structure, cost and conduction losses. Four multi-level VCs have been considered: Neutral Point Clamp (NPC), Flying Capacitor (FLC), eries Connected Two-Level H-Bridge (CLHB), and eries Connected Three-Level H-Bridge (ML-C3LHB). These converter topologies are compared in terms of the structure, function and basic characteristics in medium voltage applications. The number of components needed in each system is compared in Table 3-3, where N is the number of voltage levels. Clamping diodes are not required in the FLC and CLHB, while balancing capacitors are not needed in the NPC and FLC. In the FLC topology, a high amount of capacitances are required for high voltage levels. In the 7L-FLC VC, for example, 5 clamping capacitors plus 6 dc link capacitors are necessary to achieve the same voltage rating yielded by utilizing 9 capacitors in the CLHB topology. Not only do these many capacitors make the system less cost-effective, but they also induce the necessity to balance the capacitor voltages. Figure 3-47 shows the total required components of Table 3-3 in four investigated multi-level converters as a function of the number of voltage levels. Although the same number of modules (IGBTs/diodes) is needed in the four considered topologies, the total number of components necessary in these four topologies is different at higher voltage levels. In the same voltage range, the NPC requires substantially more components than the others do; therefore, it does not qualify for the use with a high number of voltage levels. Moreover, for more than three-level configuration, the NPC voltage imbalance problem cannot be overcome by utilizing modulation techniques. Complex balance circuits would be necessary. This makes the NPC unattractive for levels larger than three. As shown in Figure 3-47, to synthesize the same number of voltage levels, the CLHB

90 66 BAIC TRUCTURE AND FUNCTION OF VOLTAGE OURCE CONVERTER TOPOLOGIE requires the least number of total main components. However, the CLHB needs more capacitors as compared to those needed in the NPC. Another major advantage of the CLHB is its circuit layout flexibility, because each level has the same structure and there are no extra clamping diodes or voltage balancing capacitors, which are required in the NPC and the FLC topologies. The number of output voltage levels can then be easily adjusted by changing the number of H-bridge cells. Moreover, redundancy can be easily applied to enhance the reliability of the entire system. However, the control complexity is directly proportional to the number of H-bridge cells. As the number of voltage levels increases, the voltage imbalance problem becomes more of a concern. To achieve stable system, a well-defined model and an effective dc link balancing method are necessary. Each cell of the C3LHB VC generates a number of output voltage levels higher than the CLHB VC with fewer harmonic. To achieve the same number of voltage levels N for each phase, the C3LHB requires a 3(N-)/ pulse-transformer, whereas a 3(N-) pulse-transformer is needed for the CLHB VC. In conclusion, among the considered multi-level converter topologies, the eries Connected H- Bridge Converter is an attractive topology for multi-level converters. Number of total componenets NPC FLC CLHB C3LHB Number of phase voltage levels Figure 3-47 Number of total components required in the multi-level converter as a function of the number of phase voltage levels Table 3-3 Comparison of power component requirements for multi-level topologies Topology NPC FLC CLHB C3LHB Number of module (IGBT/Diode) 6(N-) 6(N-) 6(N-) 6(N-) Number of clamping diodes 3(N-)(N-) 3(N-) Number of dc link capacitors (N-) (N-) 3(N-)/ 3(N-)/ Number of balancing capacitors 3(N-) Total 3N -N- N = 3, 4, N-3 N = 3, 4, 5(N-)/ N = 5, 7, 9,.. (N-)/ N = 5, 9,

91 4. MODELLING AND IMULATION This chapter introduces the modelling of the medium voltage drive components, including utility grid, load, multi-pulse transformer, rectifier, dc link capacitor, power semiconductor devices, and inverter, as shown in Figure 4-. Grid Multi-Pulse Transformer Rectifier Converter DC-link Capacitor Inverter Load i s 3 i L (a) i s 3 3 i L (b) Figure 4- Block diagram of Medium Voltage Drives: (a) NPC and FLC VCs, (b) CHB VC 4.. Load and Grid Models 4... Load Model The electric load component has different characteristics according to the variation of voltage and frequency. Thus, for proper operation, it is essential to model it. Figure 4- depicts a standard load model for a one-phase and a three-phase form [5]. The simplified circuit diagram is based on the following conditions and simplifications: The three-phase equivalent circuit is assumed to be symmetric. It is accepted that the electromotive force (EMF) delivers sinusoidal voltages with variable amplitude and frequency.

92 68 MODELLING AND IMULATION i La R L L L e a i La R L L L e a U a i Lb R L L L e b U a U b i Lc R L L L e c U c Figure 4- tandard load model for one-phase and three-phase Resistance R L is assumed to be zero. According to this assumption, the inductive portion L L of the load impedance is dominant. Generally, this simplification is permissible for middle and large power drives, since the amount of the relationship between the inductive and resistive portion of impedance can be and more for the nominal frequency of the converter. However, the simplification is invalid if the control of the converter is concerned. In particular, within very low fundamental frequency, for example, in the starting range of a drive, resistance R L is dominant in relation to inductor L L. If the standard load is used with a star connection, the load voltages are equal to the phase voltages and the load currents are equal to the phase currents. However, it is not relevant to the converter which kind of load connection is used. These general load models are often used to simulate an induction motor or a synchronous motor, which are the most important class of the three-phase loads. Although for simulation purposes, other simple load models are also considered such as an ideal current source or a series resistive-inductive load Grid Models The three-phase utility grid is modelled by an electrical generator that implements a symmetrical voltage of three different phases (e.g. U sa, U sb, U sc ) with internal resistive-inductive impedance. In contrast to the load model, the currents are defined to be positive in the inverse direction according to Figure 4-3. The three voltage sources are connected in star with a neutral connection that can be internally grounded or made accessible. The source-internal resistance R s is assumed to be zero. U sa L s R s i sa U sb L s R s i sb U sc L s R s i sc Figure 4-3 tandard three-phase utility grid model 4.. Converter Model 4... Inverter The inverter consists of the power semiconductor devices which are triggered by sine-triangle modulation scheme.

93 MODELLING AND IMULATION Modulation method The modulation is one of the important factors in optimizing the performance of the converter. The modulation process determines the spectral content of the output waveforms as well as the distribution of losses within the converter. Many different modulation approaches have been proposed in the literature [43], [53], [56], [68], [69], [7], [7]. The converter model in this thesis is based on the sine-wave modulation strategy with a third harmonic added, as explained in detail in chapter 3 and Appendix Compact Power emiconductor Model In this thesis, IGBT modules are considered due to the modularity. For analysis purposes, the IGBTs and diodes are usually considered ideal, i.e. lossless, featuring infinite current and voltage handling capability according to Figure 4-4. The ideal IGBT is simulated as being controlled by a logical gate signal (g s ). It conducts an arbitrary current with zero on-state voltage when the switch is on (g s > ) and blocks any forward or reversely applied voltage with zero current when the switch is off (g s = ) [4]. The device can be switched instantaneously between on and off states or vice versa by triggering it. I C UCE Figure 4-4 The ideal circuit symbol of the IGBT 4... Power emiconductor Losses For the calculations, the load current is assumed to be an ideal sinusoid. Then, a symple calculation of the power semiconductor losses for medium voltage converters is presented. The losses of an IGBT can be classified as switching losses and on state (conduction) losses. The power loss dissipation in an IGBT (P loss,t ) and diode (P loss,d ) can be calculated as t P = U I + f ( E + E ) loss,t CE,n C,n C on off TC turn-on and turn off losses on-state loss t Ploss,D = UF IF,n + [ fc Erec ] TC on-state loss Reverse recovery loss with U CE,n is the on state saturation voltage and I C,n is the collector current of the IGBT U F,n is the on state voltage and I F,n is the forward current in the diode f C is the carrier frequency and T C is the one period of the carrier frequency E on is the turn-on and energy and E off is the and turn-off energy of the IGBT and E rec is the recovery energy in the diode. These parameters may be deviated from the data sheets. (4-) (4-)

94 7 MODELLING AND IMULATION 4... Loss Approximation based on Datasheets A loss model of the device is developed based on an experimental determination of the power losses. The total power losses in the converter are estimated to determine the junction temperature. A. Conduction Losses The conduction losses P con,x of an IGBT or a diode can be expressed by the well-known approximation as [9], [66], [43] B ( () ) () T con,x P = U + A i t i t dt (4-3) con,x o,x con,x T with P con,x are the conduction losses in device x T is the fundamental period U o,x and A on,x are on state voltage parameters for device x B con,x is the curve-fitted constant for device x and i is the instantaneous value of the device current. B. witching Losses witching losses are created by the commutation processes between different switch states. These commutation processes can be classified into () natural or inductive commutations, which are characterized by turn-on losses of active switches and recovery losses of diodes, and () forced or capacitive commutations, which are contrarily characterized by turn-off losses of active switches. Turn-on losses of diodes are usually small and can be neglected [], [3]. It is possible to calculate the switching losses on the basis of the collector-emitter voltage and the collector current. However, this is not a very accurate method due to the need of rough approximations. Therefore, it is more effective and more accurate to measure the switching energy directly as a function of the load current and then describe the relationship by a simple equation. The equation B ( () () ) sw,on,x B U sw,off,x com Esw,x = Asw,on,x i t + Asw,off,x i t (4-4) U CE can be found in [3], [66], [43]. E sw,x is the switching energy loss for device x, A sw,on,x, B sw,on,x and A sw,off,x, B sw,off,x are turn-on and turn-off curve-fitting constants for device x, U com is the commutation voltage, and U CE denotes the voltage at which the losses where measured. This equation is useful for turn-on and turn-off losses of the IGBT as well as for the diode. The constant parameters are determined by applying a first-order curve-fitting of the measured on state voltage characteristics and the switching energy losses which are dependent on the load current. The fitting parameters and thermal resistances of the semiconductors examined in this thesis are given in Table 4- [9], where the abbreviations T (IGBT) and D (Diode) are used for a device x. Therefore, the average switching losses P sw,x are written as P = E dt sw,x T sw,x T (4-5)

95 MODELLING AND IMULATION 7 The total converter losses are dependent on the conduction ratio of the diode and the IGBT (modulation index m a and power factor cosϕ) on the modulation method, the junction temperature T j, dc link voltage, gate drive conditions, load current, and switching frequency f C [66]. Table 4- Fitting parameters and thermal resistances of medium voltage IGBTs/Diodes FZ6R7KE3 EUPEC.7kV/6A FZR5KF EUPEC.5kV/A FZ8R33KFC EUPEC 3.3kV/8A CM6HB9H POWEREX 4.5kV/6A FZ6R65KF EUPEC 6.5kV/6A U CE 9V V 8V 5V 36V U o,t.7 U o,d A on,t B on,t A off,t B off,t A off,d B off,d A cond,t B cond,t A cond,d B cond,d R th-jc,t R th-jc,d R th-ch C. election of Heat inks For safe operation, the power losses generated by each module must be dissipated. The heat transfer of a semiconductor can be simulated in an electric circuit. Figure 4-5a shows the general equivalent circuit for an IGBT module. At steady state the junction temperature T j can be calculated using the following thermal equation T = P R + R + P R + T (4-6) ( ) { } j x loss th,ch th,ha loss,x th, jcx a with R th,jc denotes the thermal resistance of the IGBT/diode from junction to case R th,ch is the thermal resistance of the IGBT/diode from case to heat sink R th,ha is the thermal resistance from heat sink to ambient, and T a is the ambient temperature. Infineon/Eupec published a new datasheet software for IGBT modules in 3 [47] which states that R th,ch can be supplemented by the therein included values for R th,cht and R th,chd, as shown in Figure 4-5b. However, homogeneous heat distribution to the base plate is not guaranteed under all operation conditions [47] due to the distribution of separate chips for the IGBT and diode across the module s surface. Hence, a separate thermal calculation for the IGBT as well as the diode part is necessary. The values of R th,cht and R th,chd can already be derived from the previous specification but have now been added for more simplicity, as shown in Table 4- taken from [47].

96 7 MODELLING AND IMULATION Junction Case Heat sink Ambient P loss,t R th,jcd R th,ch R th,ha T j(t) R th,jct T a P loss,d T j(d) (a) Junction Case Heat sink Ambient P loss,t R th,jct R th,cht T j(t) R th,ha T a P loss,d R th,jcd R th,chd T j(d) (b) Figure 4-5 The steady state equivalent thermal circuit diagram: (a) general model, (b) Infineon model Table 4- Thermal resistance of the IGBT module: FZ6R65KF [47] Previous specifications Thermal resistance, case to heat sink per module R th,ch 6K/kW New specifications Thermal resistance, case to heat sink per module R th,ch 6K/kW Thermal resistance, case to heat sink per IGBT R th,cht 9K/kW Thermal resistance, case to heat sink per Diode R th,chd 8K/kW Description of the Loss imulation Model [66], [43] An accurate loss simulation model, which is described in detail in [3], [], [66], enables the determination of the semiconductor losses and junction temperatures. The accuracy of the loss and junction temperature calculation and the thermal model being applied is evaluated in [3], [9], [66]. To calculate the ideal current rating I C,n (I F,n ), an ideal parallel connection of commercially available IGBT or diode modules is assumed. It is obvious that on state and switching losses are adapted to the ideally rated current and the corresponding silicon area, as shown in Figure 4-6. Furthermore, the thermal resistances R th,jc and R th,ch are adjusted to the rational number of ideally parallel connected modules according to the silicon area and the module size Agreement Calculation Measurement An agreement calculation of the power semiconductor on-state voltage and switching losses is represented at this stage. It is necessary to use computer simulations in order to realize detailed

97 MODELLING AND IMULATION 73 power loss calculations of different converter topologies. The output characteristics of the IGBT/diode modules have been approximated based on data contained in the module specification sheets. Figure 4-7 depicts the simulation results for the FZ8R33KFC IGBT-module from Eupec. I C I C I C cf I C cf U CE Parallel current factor cf U CE P loss (U CE, I C ) I cf P loss (U CE, C ) cf P loss P loss R th Τ Parallel current factor cf R th cf Τ R th = R th,jc + R th,ch R th = R th,jc + R th,ch cf Figure 4-6 Characteristics of current sharing for two connected modules in parallel I C / I F [A] A con,t = r ot =.3363 B con,t =.6876 U o,t = A con,d = r od =.534 B con,d =.7534 U o,d =.8 U CEfitting U CEdata sheet E [J] E onfitting E ondata sheet E offfitting E offdata sheet E recfitting E recdata sheet A on,t = B on,t =.54 A off,t =.3776 B off,t =.8486 A off,d =.596 B off,d =.47 4 U Ffitting U Fdata sheet U CE / U F [V] (a) I C [A] (b) Figure 4-7 Approximation characteristics based on the curve-fitting method: (a) IGBT/Diode on-state characteristics, (b) IGBT turn-on and IGBT/Diode turn-off switching energy (FZ8R33KFC IGBT-module from Eupec, U CE = 8V, T j,max = 5 C) 4... DC Link Capacitor Models The instantaneous dc link current values of the grid side and the machine side converter are generally different. The dc link capacitor serves for the decoupling of both sides from each other. This section discusses the modelling process of a dc link capacitor.

98 74 MODELLING AND IMULATION 4... Capacitor [63-65], [35-4] 4... Aluminium Electrolytic Capacitors [35], [38] Aluminium electrolytic or foil capacitors are generally used in converters to smooth the dc link voltage. Among the various types of capacitors, aluminium electrolytic capacitors offer a large volume at low cost. It can also provide a large capacitance, compared with other types. Hence, it is mostly used in low voltage converters. The principle structure of an aluminium electrolytic capacitor is represented in [3], [35] in detail. The equivalent circuit of an aluminium electrolytic capacitor is shown in Figure 4-8 [35]. It forms a capacitance, a series resistance, a series inductance, and a parallel resistance. Equivalent eries Resistance (R ER ) is the series resistance consisting of the aluminium oxide layer, electrolyte/separator combination, and other resistance-related factors, foil length, foil surface area, among others. It depends upon the temperature and represents the di-electric losses and the resistance of the electrolytes and the connections. The series capacitance C x represents the actual capacity of the capacitor and depends upon frequency and temperature. The capacitance of an aluminium electrolytic capacitor becomes smaller with increasing frequency. As the temperature decreases, the capacitance also becomes smaller. The Equivalent eries Inductance (L EL ) consists of the inductive resistance of the connecting cables. The bypass resistor R EPR is due to a leakage current and can be neglected. The capacitor is designed for an operating voltage U C. This may be exceeded only briefly by a peak voltage of percent. All aluminium electrolytic capacitors are polarized for dc applications. Therefore, the alternating voltage may be located only within the range U C [35]. Each capacitor has a rating current which is effective at the maximal permissible alternating current. Typical values for an acceptable rating current range from 3mA to ma per µf [3], [36]. The capacity is indicated for a certain operating point. Typical tolerance values for the capacity are ±% and ±% for operating voltages of U C > 5V. Aluminium electrolytic capacitors have a higher dissipation factor tanδ than any other types of capacitors. Therefore, the ripple current causes in aluminium electrolytic capacitors a higher internal heat. This leads to an increase in temperature. R EPR R ER C x L EL Figure 4-8 Equivalent circuit of a capacitor [35] 4... Film Capacitors [39], [4] ince 98, great improvements have been made on dc film capacitors. Their volume and weight have been reduced by a factor of 3 or 4 over the last years. By now, film manufacturers [4] have developed thinner films and improved the segmentation techniques. Today film capacitors are attractive in a voltage ranges between 6V DC and V DC. Depending on the application, over VDC, oil-filled versions are recommended [39]. Consequently, the

99 MODELLING AND IMULATION 75 trend of industrial and traction power conversion is to replace electrolytic capacitors with film technology. This trend is supported by the many advantages that film technology offers [4]. These include: high effective current capabilities up to ARM per µf, over-voltage withstanding up to times the rated voltage, capability of voltage reversal and high peak current, no acid inside, long lifetime, and no storage problems. The principle structure of film capacitors is represented in [39] in detail. Film capacitors have the same simplified equivalent circuit as aluminium electrolytic capacitors, as depicted in Figure 4-8. However, the magnitude of the parameters differs strongly from that of the aluminium electrolytic capacitors. The serial inductance L EL and the serial resistance R ER are clearly smaller. Thus, the dissipation factor tanδ is also clearly smaller. It is typically in the range of , whereas for aluminium electrolytic capacitors it is in the range of The capacitance of the film capacitors remains virtually unaffected by the frequency up to MHz [39]. The frequencies of film capacitors are increased by times, compared to the aluminium electrolytic capacitors, due to their structure. The capacity of film capacitors depends on the temperature and exhibits a small tolerance compared to aluminium electrolytic capacitors [39]. The capacitance fluctuation as a function of temperature is smaller than that in the aluminium electrolytic capacitors. The temperature range is typically from -55 C C with a variable capacity of -4%... +%. The maximum continuous voltage of film capacitors is equal to the rated dc voltage, and their maximum permissible current rating depends on the energy dissipation. The film capacitors are outstandingly suitable for high alternating current applications because of their small dissipation factor and self-heating. Typical values for film capacitors are from 5 to 5mA per µf rated current, up to V rated voltage, and mf nominal capacity. However, film capacitors are relatively expensive compared to aluminium electrolytic capacitors. For simulation purposes, two simplified capacitor models have been used. In the first model, the effect of R EPR, L EL, and R ER is neglected. The second model which was applied is an ideal voltage source Rectifier Models In medium voltage drives, a diode rectifier is often used as a front-end converter due to its simple structure and low manufacturing cost. The simplified circuit diagram of the standard six-pulse rectifier is represented in Figure 4-9. To simplify the simulations, all the diodes are considered to be ideal, i.e. without any on state voltage drops, reverse recovery behaviour or power losses. i dc U u U v U w Figure 4-9 Circuit diagram of the standard six-pulse diode rectifier

100 76 MODELLING AND IMULATION 4.3. Isolation Transformer Modelling and imulation [6], [7], [9], [67] The dc power supplies are made of rectifiers which inject harmonics into the grid. Increasing the pulse number of the rectifiers (e.g. -, 8-, 4-pulse rectifier) is attractive, since the grid current harmonics decrease. Corresponding circuit configurations are shown in Figure 4-. This requires phase-shifting transformers with multi-windings. The 5-degree phase shift can not be obtained by classical transformers with delta, star, or zigzag winding connections. The only means is using an unbalanced zigzag winding with two different numbers of turns. The most complex part of modelling such special transformers is the determination of all the needed parameters: inductance and resistance values for each winding and coupling coefficients between all considered windings. These parameters must be determinated by using the measurements obtained from the typical tests under no-load and short-circuit conditions. Unfortunately, perfect transformers cannot be built in practice. The output voltage of the secondary windings cannot be perfectly balanced because this depends on turn ratios, which are limited to plus or minus one turn. Leakage reactance is another function of the coil position and volume. Therefore, the perfect balance between the groups of secondary windings cannot be achieved. However, to simplify the analysis the simulations are performed under the assumption of balanced three-phase line voltages. - 3 (a) -pulse diode rectifier (b) 8-pulse diode rectifier (c) 4-pulse diode rectifier Figure 4- Multi-pulse phase-shift transformer Transformer Model The 4-pulse isolation transformer is designed to provide one-fourth of the nominal input voltage to each of the four rectifiers at a 5-degree phase displacement from each other. The 5-degree phase shift is obtained by phase shifting the transformers secondary windings. ome transformer connections can be used to achieve the 5-degree phase displacement between the input voltages and the four rectifiers. Figure 4- depicts two typical diagrams of 4-pulse

101 MODELLING AND IMULATION 77 transformers constructed from two -pulse transformers. Each model has six windings overall, two windings in the primary sides and four windings in the secondary sides. Figure 4-b shows the model which is used by the industry with zigzag primary connections and a delta-star connection in the secondary sides; whilefigure 4-a simply uses an isolation transformer with a delta-primary connection and four zigzag secondary winding connections, one shifted +.5 degrees, one shifted -7.5 degrees, one shifted +7.5 degrees, and one shifted -.5 degrees in relation to the primary connection. The transformer has a turn ratio that ensures the total dc voltage produced by the four rectifiers being the same as that of a single unit of the three-phase diode rectifier directly connected to the utility grid. Due to the use of diode rectifiers, the secondary currents are distorted, but they do not contain even or triple harmonics if a constant dc link current is assumed. The secondary currents can be expressed as ( ω 5 ) 5( ω 5 ) 7( ω 5 ) ( ω 5 ) ( ω 5 ) I = I sin t +. + I sin t +. + I sin t +. s 5 7 h ( ) + I sin t I sin h t h h = 573,,,,,... ( ( ω 5 )) Is = I sin h t +. (4-7) POWER TRANFORMER WITH IOLATED ECONDARY WINDING POWER TRANFORMER WITH IOLATED ECONDRAY WINDING.5 I s U I s U I p I p V I s V I s W W I s I s3 U U I p I p V V W I s4 I s4 W (a) (b) Figure 4-4-pulse phase-shift transformer models: (a) (Dzz), (b) (Zdy)

102 78 MODELLING AND IMULATION h h = 573,,,,,... ( ( ω 75 )) Is = I sin h t. (4-8) h h = 573,,,,,... ( ( ω 75 )) Is3 = I sin h t +. (4-9) h h = 573,,,,,... ( ( ω 5 )) Is4 = I sin h t. (4-) where I h is the amplitude of h th harmonic. The utility grid phase current i sa (Figure 4-7) can be calculated by i = I + I = I + I + I + I (4-) ' ' ' ' sa p p s s s3 s4 ' ' ' ' where I s,i s,i s3,i s4 are the secondary currents referring to the primary side. For the referred ' current I s, all the positive-sequence current components (h =, 7, 3, 9 ) are.5 ahead of their corresponding positive-sequence currents whereas all the negative-sequence components (h = 5,, 7, 3 ) are -.5 behind their counterparts in the secondary winding. The magnitude of this current is reduced by the turn ratio of the transformer n tr ; therefore ' Is = Ihsin h t+ h.. + Ihsin h t+ h. +. ntr h =, 7, 3, 9,... h = 5, 7,, 3,... ' ' ' In a similar method, the other referred currents I s,i s3,i s4 can be expressed as ( ω 5 5 ) ( ω 5 5 ) (4-) ' Is = Ih sin h t h Ih sin h t h.. ntr h = 739,,,,... h = 573,,,,... ' Is3 = Ih sin( h t h ) Ih sin( h t h ) n ω + + ω + + tr h =, 7, 3, 9,... h = 5, 7,, 3,... ' Is4 = Ihsin hωt h Ihsin hωt h ntr h =, 7, 3, 9,... h = 5, 7,, 3,... ( ω ) ( ω ) (4-3) (4-4) ( ) ( ) (4-5) in which the first term represents all the positive-sequence harmonic currents while the second term denotes the negative-sequence harmonic currents. ubstituting equations (4-) through (4-5) with (4-) and using an appropriate turn ratio yields [ ω 3ω 5ω ] i = I + I + I + I = I sin t + I sin t + I sin t +... (4-6) ' ' ' ' sa s s s3 s4 3 5 Equation (4-6) shows that the low-order current harmonics, 5 th, 7 th, th, 3 th, 7 th, and 9 th are eliminated due to the transformer connection, and they do not appear in the utility grid current. The other harmonic components (up to the 49 th ) and their corresponding phase angles are also calculated and listed in Table 4-3. As a result, the utility line current is close to sinusoidal with little distortion, which is recommended by the IEEE standard [5] and C [5].

103 MODELLING AND IMULATION 79 Table 4-3 Harmonic current and their phase angles in 4-pulse transformers h ' ' ' I I I 3 I 4 ' s s s s i sa 4 = I ωt ωt ωt ωt I sin ωt 5 5 ωt ωt 45 5 ωt ωt ωt ωt 45 7 ωt ωt 35 ωt + 7 ωt 9 ωt + 9 ωt ωt ωt 9 3 ωt ωt ωt ωt 35 7 ωt ωt ωt ωt 35 9 ωt ωt ωt ωt 8 3 ωt ωt 54 I 3 sin 3ωt 5 5 ωt ωt 8 5 ωt ωt 54 I 5 sin 5ωt 9 9 ωt ωt 5 9 ωt ωt ωt ωt 5 3 ωt ωt ωt ωt 7 35 ωt ωt ωt ωt 7 37 ωt ωt ωt ωt 35 4 ωt ωt ωt ωt ωt ωt ωt ωt ωt ωt 8 I 47 sin 47ωt 49 47ωt ωt ωt ωt 8 I 49 sin 49ωt i= ' si Transformer Winding Model Generally, in high power applications, using two transformers is more favourable and the mechanical construction is simpler, compared to one transformer with four secondary windings. In this section, two different configurations are modelled and investigated, according to Figure 4-a and Figure 4-b, applying the transformer component in MATLAB/PLEC. It should be noted that the kind of winding connections is the basic difference between these configurations. In the first model Dzz, two basic zigzag couplings are used for negative and positive phase shifts, as shown in the left part of Figure 4-a. In the second model Zdy, which is used by the industry, the zigzag primary connections and delta-star secondary connections are used for the desired phase-shift angle, as shown in the left part of Figure 4-b. This means that the Zdy configuration needs thinner conductors due to more windings than the Dzz configuration. Therefore, the fluctuations on the primary windings are realized simpler in the Zdy configuration. In the following sections, both configurations are investigated separately and finally the results are compared. Table 4-4 shows the necessary input data that corresponds to the data plate of the transformer used for both models. Table 4-4 The necessary input data of the -pulse phase-shift transformer Apparent rated power, N Primary side line voltage, U N econdary line voltage (no-load), U N Frequency, f No-load primary side current, o.5[mva] [kv].74,n [V] The no-load current of transformers with a range of to MVA is assumed to about.9% of the rated current [6].

104 8 MODELLING AND IMULATION - U V W U U U L UD L VD L WD W V W V W V U V W U V W U V W V W U L UY L VY L WY L UD L VD L WD U V W V W U V W U L VY L WY L UY L VD L WD L UD Primary, 7.5 econdary, 3 econdary, 4 (a) U V W U U D U Y L UY L VY L WY L UD L VD L WD V D W V W D W Y V Y U D V D W D U V W U D V D W D U Y V Y W Y L UD L VD L WD U V W U Y V Y W Y Primary econdary econdary L UY L VY L WY U V W U U 3Y U 4D L UY L VY L WY L UD L VD L WD W V W 4D V 4D W3Y V 3Y U 4D V 4D W 4D U V W U 4D V 4D W 4D U 3Y V 3Y W 3Y L U4D L V4D L W4D U V W U 3Y V 3Y W 3Y L U3Y L V3Y L W3Y Primary econdary 4 econdary 3 Figure 4- Investigated zigzag coupling configurations: (a) Delta-zigzag-zigzag configuration (Dzz), (b) Zigzag-delta-star configuration (Zdy) used by the industry

105 MODELLING AND IMULATION 8 I. Delta-zigzag-zigzag (Dzz) configuration This configuration is represented in Figure 4-a. For the secondary winding, the desired phase-shift angle is equal to -.5. This means that this secondary winding has to be a combination of Dy (-3 ) and Dd ( ) [67]. The secondary phase voltage is shown in Figure 4-3. For the negative or positive phase shift, the zigzag winding of each phase consists of three parts. - U U L UY L WY U U L UD L VD O L VY W V V W W O L VY V W (a) (b) V Figure 4-3 Windings position for positive (a), and negative (b) phase shift of Dzz configuration Based on Figure 4-3a, the following equation can be written for the negative phase shift ( ) ( ) ( ) U V = U U + U V + V V (4-7) U V = U U + U V + V V (4-8) The turn ratios between the secondary windings n YD can be calculated as n YD n Y UU VV U NY tanα = = = = = n U V U V U tanα D ND (4-9) where U NY, U ND are secondary no-load voltages with star and delta connections in each three-phase transformer. Now equation (4-8) can be rewritten as below by applying equation (4-9) ( 6 ) ( 6 ) UV = U V + n YD + n YD cos j n YD sin (4-). 866 n YD UV = U V ( +. 5 n YD ) + (. 866 n YD ) arctg +. 5 n YD (4-) U V = k U V α (4-) where k is a constant and calculated as

106 8 MODELLING AND IMULATION U V U n k. n. n ( 5 ) ( 866 ) N = = = = + ' ' YD + YD UV UND n D (4-3) The next step is to define the similar open-circuit turn ratio n tr between the primary and each secondary winding of the transformer. n n U V U N tr = = = (4-4) n UV UN According to Figure 4-4, the equivalent short-circuit impedance for secondary winding j can be calculated as follows ' ' ' ' Z jd Z jy Zkj = ZjD + ( Z jd Z jy ) = Z jd + where j =,.., 4 (4-5) ZjD Z jd ' ' where Z jd and Z jy denote the secondary winding impedance with star and delta connections referred to the primary side, and Z jd is the primary winding impedance. Z jωl Z R n jωl R U N U N jωl m R m n Z n jωl R U N Figure 4-4 Equivalent electrical circuit of a linear 3-winding transformer With due attention to the winding impedance, which is proportional to the square number of windings turns, it can be written as ' ' ' jy jy jd jd jy jy ',, jd Z jd jd jd n Z n Z n Z = = = (4-6) n n Z n Z By substituting equations (4-4) and (4-6) in equation (4-5), the equation Z kj = Z + n jyd jd k ( + n jyd ) (4-7) results. Moreover, by suggesting a value for the transformer short-circuit voltage U k = % [46], the equal short-circuit impedance can be calculated according to equation (4-8). Z = U Z =. Z (4-8) kj k N N The absolute value is taken account of since a phase shift will be introduced in the zigzag

107 MODELLING AND IMULATION 83 winding. By replacing equation (4-7) in equation (4-8), the primary winding impedance can be calculated as. ZN j Z jd = (4-9) n jyd + k + n ( jyd ) j Now the equivalent circuit parameters include the winding resistance, the leakage inductance and the magnetizing impedance of the zigzag winding can be determined. These parameters are strongly dependent on the rated output current of the transformer. At large units in a range of MVA to MVA, the leakage inductance can be considered to be to 3 times the resistance [6]. In order to determine the shares of the winding resistance and the leakage inductance in each transformer, a ratio of 5 is considered between the leakage inductance and the winding resistance (X T = 5R T ). Then, the following equation can be used to determine the winding resistance and the leakage inductance in each transformer. R L T T = Z T X T + RT (4-3) = XT RT ω = π f (4-3) II. Zigzag-delta-star (Zdy) configuration This configuration is represented in Figure 4-b. Two primary windings with the desired phase-shift angle of ±7.5 are considered. This means that the primary windings have to be a combination of Delta-star DY and Delta-delta DD connections. The primary phase voltage is shown in Figure 4-5. imilar to the secondary windings in the Dzz configuration, the primary zigzag winding of each phase consists of three parts for the negative or positive phase shift. - U L UY U L UY U U L VD L UD W W O L VY V O L VY W V V (a) V W (b) Figure 4-5 Windings position for positive (a), and negative (b) phase shift of Zdy configuration

108 84 MODELLING AND IMULATION Therefore, equations (4-9) and (4-3) can be rewritten for the positive phase shift, according to Figure 4-5a, n n U U V V U tanα ' ' Y NY YD = = = = = ' ' ' ' nd UV UV U ND tanα k. n. n ( 5 ) ( 866 ) = = + YD + YD n D (4-3) (4-33) where U NY, U ND are primary no-load voltages with star and delta connections in each threephase transformer. The same equations can be applied to the negative phase shift case, according to Figure 4-5b MATLAB/PLEC Implementation The MATLAB simulation software is used to simulate these multi-winding transformers in detail. Both Dzz and Zdy configurations are modelled, examined, and compared. The linear three-winding transformer in the PLEC models three coupled windings on the same core, which is a toolbax for the fast simulation of electrical and power electronics circuits, according to Figure 4-4. The magnetization inductance L m and the core losses R m are modelled as linear elements. The magnetization resistance R m represents the core losses and is negligible in this part. Instead, the values of the core losses are referred to the primary side. For the following discussion, this equivalent electrical circuit is assumed for both Dzz and Zdy configurations. The following computation shows how to model a three-winding transformer with a zigzag connection in detail. I. Dzz configuration By setting U N = kv and U N = V as well as using equation (4-4), the open-circuit turn ratio between the primary and secondary windings can be calculated as n n tr = = = 833. where j =,.., 4 (4-34) n j By setting N =.5MVA, the rated impedance Z NY of the primary winding is calculated according to equation (4-35) ( ) 3 U V N NY 3 N 5 Z = = = Ω [ VA] (4-35) The star-connected equivalent no-load impedance Z Yo is calculated by taking into account the no-load current i o (Table 4-4) [67] Z = Z = 44.44Ω= 8.88kΩ (4-36).5 Yo NY io Using the angular frequency, the equivalent star-connected inductance L my is calculated as Z Y L o my = = 8. 9H π 5Hz (4-37) To obtain the delta-connected inductance L md, the previous value has to be multiplied by 3; thus

109 MODELLING AND IMULATION 85 L = H = H (4-38) md Considering a negative phase-shift angle of.5 and using equation (4-3), the ratio between the turn number of the star and delta connection of this secondary winding is equal to n ( 5) ( ) tan. Y n YD = = =. n D tan. 5 Introducing (4-39) in (4-3), we obtain 693 ( ) ( ) k = = Then, the turn number of the star and delta connections of this secondary is equal to D Y D YD k (4-39) (4-4) n = =. 6, n = n n =. 44 (4-4) Now the equal short-circuit impedance Z k can be calculated as Z =. Z = 444. Ω (4-4) k NY Further, by using equation (4-9), the primary winding impedance is calculated as 444. Ω Z = = 43. Ω D ( +. 5) (4-4) Now by applying equations (4-3) and (4-3), the primary winding resistance, the primary leakage inductance, and the primary impedance are calculated as 43. D R = =. Ω, L =. =. 34H + π D ( ) ( 5) ( ) (4-44) ZD = RD + jx D =. + j 4. Ω (4-45) Afterwards, the secondary winding resistance, the secondary leakage inductance, and the secondary impedance can be determined on the basis of equation (4-6), yielding the following equations n D. 6 RD R D. n 833. = = Ω = 7µ Ω (4-46) n D. 6 LD = L D =. 34H = 3. µ H n 833. ( ) (4-47) ZD = RD + jx D =. 7 + j 4. mω (4-48) n Y. 44 R Y R D. n 833. = = Ω = 594µ Ω n Y. 44 L Y = L D =. 34H = 37. 7µ H n 833. (4-49) (4-5)

110 86 MODELLING AND IMULATION ( ) Z Y = R Y + jx Y = j. 85 mω (4-5) Thus, the secondary equivalent impedance is equal to Y D ( ) Z = 3 Z + Z = j mω (4-5) The same equations can be applied to the positive phase-shift case, according to Figure 4-3b. To achieve this aim, a similar method is employed for the positive phase-shift angle of 7.5. The ratio between the turn number of the star and delta connections of this secondary winding is equal to n ( 75) ( ) tan. Y n YD = = =. n D tan ( ) ( ) (4-53) k = =. 36 (4-54) Then, the turn number of the star and delta connections of this secondary winding is equal to n = =. 765, n = n n =. 5 (4-55) D Y D YD k Thus, by using equation (4-9), the primary winding impedance is calculated as 444. Ω Z = = 434. Ω D ( +. 9) (4-56) Now by using equations (4-3) and (4-3), the primary winding resistance, the primary leakage inductance, and the primary impedance are calculated as R =. 7Ω, L =. 38H (4-57) D D ( ) ZD = R D + jx D =. 7 + j Ω (4-58) Then, the secondary winding resistance, the secondary leakage inductance, and the secondary impedance can be determined as follows, based on equation (4-6), n D. 765 RD R D m n 833. = = Ω = Ω (4-59) n D. 765 LD = L D =. 38H = 6. 4µ H n 833. ( ) (4-6) ZD = RD + jx D = j 365. mω (4-6) n Y. 5 RY R D.. n 833. = = 7Ω = 7 3µ Ω (4-6) n Y. 5 LY = L D =. 38H = 4. 5µ H n 833. ( ) (4-63) ZY = RY + jx Y =. 73+ j. 4 mω (4-64) Thus, the secondary equivalent impedance is equal to

111 MODELLING AND IMULATION 87 Y D ( ) Z = 3 Z + Z = + j 4. 7 mω (4-65) Now the primary equal impedance of parallel transformers (-.5 and 7.5 ) can be calculated by (. j 4. ) (. 7 j 4. 33) (. j 4. ) (. 7 j 4. 33) + Ω + Ω Z = ZD Z D = = (. 8 + j. 4) Ω (4-66) + Ω+ + Ω Thereby, the magnetization inductance L m is equal to L = L = H = 69. 7H (4-67) m md imilar methods can be used to obtain the winding resistances, the leakage inductances, and winding impedances for the parallel operation of the negative phase-shift angle 7.5 and positive phase-shift angle.5. Table 4-5 depicts the quantity results for all secondary windings in detail. These values are used directly in the PLEC model component of MATLAB. As seen in Table 4-5, similar results are obtained for the secondary windings with a phase-shift angle of ±.5 and a phase-shift angle of ±7.5 too. Therefore, the primary equivalent impedance of the parallel transformers -.5 and 7.5 is equal to the primary equivalent impedance of the parallel transformers.5 and -7.5 ( ) ' Z = Z =. 8 + j. 4 Ω (4-68) Then, the primary equivalent impedance of transformer Z is equal to ' Z = Z Z = Z = ( j 7. ) Ω (4-69) Table 4-5 The secondary quantity parameters for the 4-pulse transformer with Zdy connection n YD n D ny k α = ±.5 L D [µh] L Y [µh] R D [µω] R Y [µω] Z [mω] Z D j39.6.+j4. α = ±7.5 n YD n D ny k L D [µh] L Y [µh] R D [µω] R Y [µω] Z [mω] Z D [mω] j36.5.+j4.33 [mω] II. Zdy configuration The Zdy configuration parameters can be determined like the Dzz configuration. For this purpose, the following model is assumed for each -pulse transformer, according to Figure 4-6. The calculations are accomplished on the basis of equations (4-9) to (4-3) and the input data of the Table 4-4. The computation results are summarized in Table Medium Voltage Converter Application The effect of a multi-winding transformer on two medium power converters, i.e. the 3L-NPC VC and 9L-CLHB VC, is investigated. The steady state at % load with symmetrical

112 88 MODELLING AND IMULATION transformers, as calculated above, is assumed. Each 4-pulse transformer consists of two - pulse transformers. The model of one -pulse transformer is illustrated in Figure 4-6. To validate the obtained simulation results, MATLAB and implorer programs are used. Table 4-6 The designing parameters for the 4-pulse transformer with Zdy connection L.4[mH] R.[mΩ] L Y = L D 3[µH] R Y = R D [µω] L m 85[H] U ky = U kd 8[%] U kyd 4[%] i o.5[p.u.] jωl R jωl R Y Y U N U N Y D D ω j L m jωl m jωl R U N D V N jωl R jωl R Y Y V N Y jωl m jωl R D D V N D W N jωl R jωl R Y Y W N Y jωl R D D W N D Figure 4-6 The model of a -pulse transformer Three-Level Neutral Point Clamped Voltage ource Converter The first application example deals with the 4-pulse rectifier with serial diode-bridge-rectifier connections, which is used for the 3L-NPC VC. The corresponding circuit is represented in Figure 4-7 and Figure 4-8 for the two aforementioned configurations. The structure consists of the ac three-phase input source, four diode-bridge circuits, and two -pulse phase-shift transformers. The dc output is made of four 6-pulse rectifiers with a serial connection. The three-phase voltages of the rectifier input terminals are set to have a 5-degree phase difference. This connection allows supplying the four-diode rectifiers with 5-degree phase-shifted their phase voltage systems. This leads to a 4-pulse rectifier system.

113 MODELLING AND IMULATION 89 POWER TRANFORMER WITH IOLATED ECONDARY WINDING RECTIFIER I p I s.5 U sa INPUT POWER THREE-PHAE AC OURCE i sa L s R s U sb Ls R s U i I dc dc s3 U sc Ls R s I p I s I s4 -.5 Figure Pulse-Diode-Rectifier with serial connections and Dzz configuration POWER TRANFORMER WITH IOLATED ECONDARY WINDING RECTIFIER U sa INPUT POWER THREE-PHAE AC OURCE i sa L s R s U sb L s R s I p U sc Ls R s i dc I s I s I s3 -.5 I p 7.5 I s4 7.5 Figure Pulse-Diode-Rectifier with serial connections and Zdy configuration imulation Results Figure 4-9 to Figure 4- represent the simulation results assuming an ideal current source as load. As expected, the first dominant ac supply phase current harmonics are the 3 rd and the 5 th ones, according to Figure 4-9b. The first dominant primary and secondary current

114 9 MODELLING AND IMULATION harmonics are the th, 3 th and 5 th, 7 th ones, according to Figure 4-9c and Figure 4-9e respectively. The harmonics analysis results confirm the proposed 4-pulse modelling. 5 i sa (a) 3 (b) i sb i s,x [A] i sc Amplitude i sa Time [sec.] Harmonics order (c) (d) I p,x [A] - I pu I pv I pw Amplitude I pu Time [sec.] Harmonics order I s,x I su I sv I sw Time [sec.] (e) Amplitude I su Harmonics order (f) Figure 4-9 Utility grid current and its harmonic spectrum for the 4-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the -pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the -pulse transformer (e, f) (see Figure 4-7)

115 MODELLING AND IMULATION 9 I p I s I p 5 I s I s3 I px [A] I sx [A] I s Time [sec.] Time [sec.] Figure 4- Primary and secondary winding currents of the 4-pulse transformer [V] (a) Amplitude 3 (b) Time [sec.] Harmonics order 7 79 (c) (d) i dc [A] Amplitude i dc Time [sec.] Harmonics order Figure 4- DC link voltage and its harmonic spectrum (a, b), and dc link current and its harmonic spectrum (c, d), i dc = 7A, f C = 75Hz (see Figure 4-7)

116 9 MODELLING AND IMULATION Nine-Level eries Connected H-Bridge Voltage ource Converter The second application example deals with the 4-pulse dc supply with independent diodebridge-rectifier connections, which is used for the 9L-CLHB VC. The corresponding circuits are represented in Figure 4- only for one motor phase. The dc supply is made of four separate 6-pulse transformers, each one leading to a 6-pulse rectifier system. The three-phase voltages of the rectifier input terminals are set to have a 5 -phase difference, which generates a 4-pulse rectifier system. POWER TRANFORMER WITH IOLATED ECONDARY WINDING RECTIFIER I s I p.5 i dc, U sa INPUT POWER THREE-PHAE AC OURCE i sa L s R s U sb L s R s I s -7.5 i dc, I s3 U sc L s R s I p 7.5 i dc3,3 I s4 -.5 i dc4,4 (a) POWER TRANFORMER WITH IOLATED ECONDARY WINDING RECTIFIER I s.5 i dc, INPUT POWER THREE-PHAE AC OURCE U sa i sa L s R s U sb Ls R s I p -7.5 I s -7.5 i dc, U sc Ls R s I s3 -.5 i dc3,3 I p 7.5 I s4 7.5 i dc4,4 (b) Figure 4-4-Pulse-Diode-Rectifier with independent connections: (a) Dzz configuration, and (b) Zdy configuration

117 MODELLING AND IMULATION imulation Results Figure 4-3 to Figure 4-6 represent the simulation results in the steady state at % load, which are the equivalent to that of the 3L-NPC VC. As expected, the first dominant ac supply phase current harmonics are the 3 rd and the 5 th ones, according to Figure 4-3b. The harmonics analysis results confirm the proposed 4-pulse modelling. The first dominant primary and secondary current harmonics are the th, 3 th and 5 th, 7 th ones, according to Figure 4-3d and Figure 4-3e respectively. 5 i sa i sb (a) (b) i s,x [A] 5-5 i sc Amplitude i sa Time [sec.] Harmonics order I p,x [A] I pu I pv I pw Time [sec.] (c) Amplitude I pu Harmonics order (d) 6 4 (e) 3 (f) I s,x [A] - I su I sv I sw Amplitude I su Time [sec.] Harmonics order Figure 4-3 Utility grid current and its harmonic spectrum for the 4-pulse transformer (a, b), primary winding currents and their harmonic spectrum for the -pulse transformer (c, d), and secondary winding currents and their harmonic spectrum for the -pulse transformer (e,f) (see Figure 4-8)

118 94 MODELLING AND IMULATION I px [A] Time [sec.] I p I p I sx [A] Time [sec.] I s I s I s3 I s4 Figure 4-4 Primary and secondary winding currents of the 4-pulse transformer ,x [V] Amplitude Time [sec.] Harmonics order Figure 4-5 DC link voltage and its harmonic spectrum, f C = 75Hz (see Figure 4-8) i dc,x [A] i dc i dc Amplitude i dc,x 47.6 i dc3 i dc Time [sec.] Harmonics order Figure 4-6 DC link current and its harmonic spectrum, i dc = 47A, f C = 75Hz (see Figure 4-8)

119 5. DEIGN CRITERIA AND CONVERTER DATA This chapter defines the design criteria and technical data of the typical available industrial medium voltage drives (the 3L-NPC VC, 3L-FLC VC, 4L-FLC VC, and 9L-CLHB VC) which will be compared in detail in chapter Design Criteria The design process of a power converter depends on the topology and the converter specifications including line-to-line voltage U ll,rms,, phase current I ph,rms,, and the apparent converter output power C, which have a critical influence on the overall characteristics, performance, and cost of any design Power emiconductor Devices The selection of power semiconductors fundamentally determines the design and the performance as well as the investment and operating costs of power converters. IGBTs are usually used as power semiconductors in medium and high power applications [8], [78] due to their technical advantages. When designing an IGBT/diode, important technical characteristics are: U CE : Rated collector-emitter voltage. I C,n / I F,n : Rated IGBT/Diode current. U RRM : Repetitive peak reverses voltage of diodes. T j, max : Maximum junction temperature range within the IGBT/Diode may be operated. R th,jc, R th,ch : Thermal resistances of the IGBT/diode from junction to case and case to heat sink. T h : Temperature of the heat sink. E on /E off : Turn-on / turn-off dissipation energy in the IGBT. E rec : Recovery dissipation energy in the Diode. U com@fit : The voltage U com@fit characterizes the device commutation voltage for a device reliability of FIT (where FIT corresponds to one failure in 9 operation hours) due to cosmic radiation. For a steady state operation, this voltage should be higher than the dc link voltage (U com@fit >,n ). The installed switch power is a measureof the semiconductor cost and can be defined as = U I n + 5. U I n (5-) CE C,n T RRM F,n D where n T and n D denote the number of semiconductors and diodes in the converter. Considering that the diode area is typically only about 5% of that of the IGBTs in IGBT modules, the diodes are weighted with 5% compared to the IGBTs (equation 5-), [9], [47].

120 96 DEIGN CRITERIA AND CONVERTER DATA The relative installed switch power is calculated by normalizing the installed switch power of a certain converter topology to the installed switch power of the reference topology (e.g. the 3L- NPC VC) [9]. R = (5-), 3L NPC VC This definition enables a comparison of the installed switch powers as a measure for the expense of semiconductors of the different converter topologies with respect to the 3L-NPC VC. The dimensioning of the semiconductor devices is based on the electrical and thermal data given in module specification datasheets. The switching frequency and output power of the MV converters are limited by the junction temperature T j of the semiconductor devices. For a safe operation, the junction temperature must never exceed the maximum value T j,max, whereby the average power losses in frequency ranges of 5Hz to 5Hz are considered (operating range). Therefore, the cooling of power semiconductors and thus the power dissipation in the semiconductors are criteria for the dimensioning of these devices. However, the operating range of f o < 5Hz, failure conditions, and dynamic procedures (e.g. overload, connection, and disconnection of the converter) are not examined in this thesis. Figure 5- depicts the suggested iterative approach to the power semiconductor design. By using this chart, it is possible to determine the installed switch power, the semiconductor losses, and the necessary silicon area. To select the suitable device, an iterative MATLAB program is used, which allows to select the calculation of the required switch ratings. Essentially, it starts by providing a screen with different critical operation points related to the topology. The number of ideal parallel connections is selected so that the mostly stressed device never exceeds the maximum junction temperature T j,max in all critical operating points (Table 5- ) of a four-quadrant operation [], [5]. A maximum junction temperature greater than 5 C is an indication that the number of ideal parallel connections should be changed and more silicon area is necessary. Furthermore, to evaluate the converter topologies for a variety of applications, four different categories are discussed and simulated in chapter 6. In a first step, a constant carrier frequency and a constant installed switch power are assumed. This approach allows a comparison between the maximum converter output power C,max and the semiconductor utilization of the considered converter topologies. Figure 5- shows the applied calculation method. In the second comparison, a constant installed switch power (which is a measure for the cost of semiconductors) as well as an equal output current and a constant converter output power C are assumed to calculate the maximum carrier frequency of the considered converter topologies, as shown in Figure 5-3. Table 5- Critical operating points for the determination of the power semiconductor current ratings (stationary thermal design) for all considered topologies [], [5] Operating Point,n I ph,rms, cosϕ m a OP +% -%.5 OP -% +%.5 OP3 +% -% -.5 OP4 -% + % -.5 OP5 -% +% OP6 -% +% -

121 DEIGN CRITERIA AND CONVERTER DATA 97 Converter specifications U ll,rms,, I ph,rms,, C Calculation of the nominal dc link voltage,n = f (U ll,rms, ) Calculation of the commutation voltage and the rated device voltage (U com, U CE ) = f (,n ) Calculation of the power semiconductor losses and the junction temperature in 4Q-operation (P loss, T j ) 99. T j,sp T j T j,sp Yes No Adaption of the rated device current I C,n (I F,n ) and thermal resistance R th by cf to provide the condition Calculation of the installed switch power for all considered topologies Adaption of the current factor cf to provide the constant installed switch power for all considered topologies Figure 5- Iterative design approach to the power semiconductor design

122 98 DEIGN CRITERIA AND CONVERTER DATA f C = constant 99. T j,sp T j T j,sp Yes Results I ph,max, C,max,P loss,η No Variation of the output converter current I ph Figure 5- Iterative design approach to calculate the maximum converter output power C,max and the semiconductor utilization (T j = T j,max, = const., f C = const.) I ph = constant Results 99. T j,sp T j T j,sp Yes f,p,η C,max loss No Variation of the carrier frequency f C to provide the condition Figure 5-3 Iterative design approach to calculate the maximum carrier frequency (T j = T j,max, = const., C = const.) The third condition for a converter comparison is the constant installed switch power and a constant frequency of the first harmonic carrier band f Cb, according to Figure 5-4. This approach allows a comparison between the converter output power and losses of the considered converter topologies. If the first harmonic carrier band occurs at around the same frequency, the design of an output filter with about the same size and weight is enabled. The constant converter power C and a constant converter efficiency η are assumed for a fourth condition to calculate the carrier frequency, achieving a maximum junction temperature of T j,max in one worst case operating point of the converter (see Figure 5-5). The chosen efficiency is typical for state-of-the-art medium voltage converters.

123 DEIGN CRITERIA AND CONVERTER DATA 99 f Cb = constant Calculation of the switching frequency f C for all topologies 99. T j,sp T j T j,sp Yes Results I ph,max, C,max,P loss,η No Variation of the output converter current I ph Figure 5-4 Iterative design approach to calculate the converter output power and losses (T j = T j,max, = const., f Cb = const.) η = constant η η ref Variation of the carrier frequency f C to provide the condition 99. T j,sp T j T j,sp Yes Results P loss, η,... No Adaption of the rated device current I C,n (I F,n ) and thermal resistance R th to provide the condition Figure 5-5 Iterative design approach to calculate the maximum carrier frequency (T j = T j,max, C = const., η = η ref const.)

124 DEIGN CRITERIA AND CONVERTER DATA 5... DC Link Capacitor Different criteria are given in the literature for the dimensioning of the dc link capacitor [], [65], [77], [38], and [4]. Design criteria like dc link voltage ripples and dc link capacitor storage energy play important roles in sizing the dc link capacitor and they are therefore examined in this thesis in order to choose the most suitable amount and size of dc link capacitors DC Link Voltage Ripples The primary function of the dc link capacitor is to filter the dc link voltage and to provide a stable dc voltage link for the inverter section. The impermissible dc link voltage ripples may have unfavourable effects on the operation of the drive. They increase the current harmonics and the electromagnetic interference (EMI) of the drive and negatively affect the electric machine. Other possible consequences are an increase of electric losses, higher supply current harmonics, an excessive rise of motor temperature, appearance of torque pulsations on the machine side, noise problems, and a higher risk of semiconductor failure. A solution to these problems is an appropriate design of the dc link capacitor. For this purpose, this section first presents an equation to determine the minimum size of the dc link capacitor for the NPC and CHB topologies as a function of the voltage ripple U C, which is derived in [4], [44]. C C min,npc min,chb PC = U U U f C C dc rec P C π ma = sin arccos U C 4 UC Udc f rec (5-3) (5-4) where P C denotes the converter output active power in watts, m a is the modulation index and f rec is the rectifier output frequency in hertz DC Link Capacitor tored Energy tored energy is a measure to compare the different converter topologies with each other and/or to compare the different applications of a topology with each other. This size is also a measure for ride-through capability. Power disturbance ride-through capability can be defined as the ability of a drive to maintain the motor output power with a power line disturbance or drop voltage at the drive input. If there is an input power disturbance, the dc link voltage will drop and the drive will stop the motor after a short time. During a power ride-through capability, the input power is removed and the stored energy in the dc link capacitor bank is the only source of power available to run the motor. Then, the stored energy per kva is a measure of the ridethrough capability as well as a measure of the cost and volume of the dc link capacitor. The equation for the stored energy in a dc link capacitor is EC = C Udc (5-5) It can be observed that the stored energy in a drive is directly proportional to the dc link capacitance and proportional to the square of the dc link voltage. However, not the entire stored energy is available for the drive to provide output power to the motor. If the ride-through capability time is under one second, it is very likely that the energy requirement is supplied by the internal dc link capacitor. If, however, the required energy is only

125 DEIGN CRITERIA AND CONVERTER DATA slightly more than the stored energy of the dc link capacitor, an increase in the dc link capacitor and a recalculation of the available energy should be considered. Figure 5-6 illustrates the relations between the dc link voltage ripple and the stored energy for the 3L-NPC VC as a function of the dc link capacitance, using equations (5-3) and (5-5). An increase of the dc link capacitance increases the stored energy and decreases the dc link voltage ripple. It is to remark that the application of the dc link capacitance C =.77mF enables a reduction of the dc link voltage ripple by 5% at twice the stored energy, compared to the use of the dc link capacitance C =.39mF at a stored energy of 6J/kVA. 5 UC [%] 5 C =.39 [mf] C =.77 [mf] E C [J/kVA] Figure 5-6 The dc link voltage ripple U C and the dc link stored energy E C as functions of the dc link capacitance for the 3L-NPC VC (U ll,rms, = 4.6kV, I ph,rms, = 6A, cos ϕ =.9, Udc = 68V) Design of the Flying Capacitors Assuming sinusoidal converter output voltages and currents, equation (5-5) can be used as an approximation to determine the capacitance of the flying capacitors of a 3L-FLC VC and a 4L- FLC VC Î C ph,rms, = n C U f C C (5-6) where Î ph,rms, denotes the amplitude of the phase current, n C is the number of series connected flying capacitor cells, f C is the carrier frequency, and U C denotes the maximum voltage ripple across the flying capacitors. For the design being realized the maximum capacitor voltage ripple U C,max was specified to 5% of the rated flying capacitor voltage of the 3L-FLC VC for both flying capacitor converters ( U C,max =.5,n /). [9] To verify the approximation according to (5-5), the voltage ripple U C and current i C,rms of the flying capacitors of a 3L-FLC VC and a 4L-FLC VC are studied in section 6..4.

126 DEIGN CRITERIA AND CONVERTER DATA 5.. Definition of the Converter Data Table 5- depicts the characteristic converter data for the output phase current I ph,rms, = 6A, which is used for the comparison of the investigated converter topologies in chapter 6. Today, the line-to-line voltages of.3kv, 3.3kV, and 4.6kV are usually used for MVDs. However, due to the development of 6kV-7.kV MVDs in the last years, rated voltages of 6.kV and 6.9kV are also selected. Table 5- Converter data (Output phase current I ph,rms, = 6A) Converter line-to-line voltage U ll,rms, Apparent converter output power c Nominal dc link voltage,n Phase current I ph,rms, Converter output frequency f o.3kv, 3.3kV, 4.6kV, 6.kV, and 6.9kV.4MVA, 3.4MVA, 4.3MVA, 6.4MVA, and 7.MVA 3383V, 4853V, 68V, 99V, and 48V 6A 5Hz Converter efficiency 99% Output voltage THD according to IEEE % Modulation Natural sampled sine-triangle modulation with /6 added third harmonics Carrier frequency f C 45Hz 5Hz Maximum junction temperature T j,max (IGBT, diode) 5 C Heat sink temperature T h 8 C 5... Power emiconductor Devices Table 5-3 summarizes the power semiconductor devices in the voltage classes of.7kv,.5kv, 3.3kV, 4.5kV, and 6.5kV from several manufacturers, which are used in this thesis. Table 5-3 Power semiconductor devices [56], [58], [6] Manufacturer Device U CE,n I C,n (I F,n ) U com@fit Eupec (Infineon) Mitsubishi (Powerex) Dynex FZ6R65KF 6.5kV 6A 36V FZ8R33KF 3.3kV 8A 8V FZ8R33KFC 3.3kV 8A 8V FZR5KF.5kV A V FZ6R7KE3.7kV 6A 9V CM9HB-9H 4.5kV 9A 5V CM6HB-9H 4.5kV 6A 5V CM8HA-66H 3.3kV 8A 65V CM8HA-5H.5kV 8A 5V CM6DY-34H.7kV 6A 85V DIM8NM33-A 3.3kV 8A 8V DIM6DDM7-A.7kV 6A 9V

127 DEIGN CRITERIA AND CONVERTER DATA witching Frequency The considered converter topologies are modulated by a sine-triangle modulation with an addition of /6 th of third harmonics. To evaluate the converter topologies for a variety of applications, carrier frequencies of f C = 45Hz... 5Hz are assumed for all investigated converter topologies. This range is typical for available industrial medium voltage drives DC Link Voltage The minimum dc link voltage,min to achieve a certain line-to-line output voltage by using a sine-triangle modulation with /6 added third harmonics for all topologies is calculated by U = U (5-6) dc,min ll,rms, To determine the nominal dc link voltage of the converter,n, a control voltage reserve of 4% is assumed, which is needed for dynamic processes and filter voltage drops. U = 4. U (5-7) dc,n dc,min Due to the circuit structure of the CLHB VCs, the minimum dc link voltage of one H-bridge,HB depends on the number of series connected H-bridges p. It is determined by equation (3-3) and can be rewritten as U dc,n U dc,hb = (5-8) p To evaluate the harmonic spectrum of the line-to-line output voltage, the total harmonic distortion (THD) and the weighted total harmonic distortion (WTHD) are being considered (based on equation 5-9). ( Ull,h ) U h h= h= THD =, WTHD = Ull, Ull, ll,h (5-9) where h denotes the order of harmonics. The weighted total harmonic distortion is a measure of the harmonic content for the output current and the harmonic losses in the load Rectifier Depending on the inverter configuration, two types of diode rectifiers are used: () series-type, where the dc sides of the standard six-pulse diode rectifiers are connected in series which uses for the 3L-NPC VC and () separate-type, where each dc side is connected directly which uses for the 9L-CHB VC. The block diagrams of a 4-pulse-diode-bridge configuration for both applications are depicted in Figure General Data for the elective Medium Voltage Converters Figure 5-8 illustrates the selected medium voltage drives in the.4mva to 7.MVA range with voltage ratings from.3kv to 6.9KV at a phase current rating of 6A. The technical data of the selected medium voltage topologies (e.g. the L-VC, 3L-NPC VC, 3L-FLC VC, 4L- FLC VC, and CLHB VCs), which are analyzed in this thesis, are also summarized in Table 5-4. tate-of-the-art.7kv,.5kv, 3.3kV, 4.5kV, and 6.5kV IGBTs are examined. The converter ratings were chosen so that they are comparable with the ratings of commercially

128 4 DEIGN CRITERIA AND CONVERTER DATA available topologies. It is interesting to note that the same technical data are utilizable for both 3L-VCs due to the same voltage utilization of the semiconductors. However, the required current rating to achieve a certain output current is different because of the different circuit structures and modulation schemes. In CLHB VCs, the number of series connected H-bridges differs according to the required line-to-line output voltage and if.7kv IGBT moduls are applied. Today, the use of the.7kv IGBT moduls is state-of-the-art for all considered output voltage classes of the CLHB VCs (a) eries configuration (b) eperate configuration Figure pulse diode rectifier configurations: (a) series configuration uses for the 3L-NPC VC, (b) separate configuration uses for the9l-chb VC Power range.4mva 3.4MVA 4.3MVA 6.4MVA 7.MVA Voltage range.3kv 3.3kV 4.6kV 6.6kV 6.9kV L-VC 6.5kV IGBT 4.5kV IGBT 3L-VCs 3.3kV IGBT 4.5kV IGBT 6.5kV IGBT 3.3kV IGBT 4L-FLC VC.5kV IGBT 3.3kV IGBT 4.5kV IGBT 6.5kV IGBT 6.5kV IGBT CLHB VC Number of cells per phase/number of levels per phase /5 3/7 4/9 5/ 6/3.7kV IGBT Figure 5-8 Voltage and power ranges of the selective medium voltage drives (I ph,rms, = 6A), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3)

129 DEIGN CRITERIA AND CONVERTER DATA 5 Table 5-4 The converter specifications for medium voltage converters Converter specifications for the L-VC Converter line-to-line voltage U ll,rms,.3kv 3.3kV Apparent converter output power c.4mva 3.4MVA Nominal dc link voltage,n 3383V 4853V Commutation voltage U com =,n 3383V 4853V Rated device voltage U CE,n 6.5kV IGBT 4.5kV IGBT U com@fit 36V 5V U com /U [email protected] Converter specifications for the 3L-VCs Converter line-to-line voltage U ll,rms,.3kv 3.3kV 4.6kV Apparent converter output power c.4mva 3.4MVA 4.3MVA Nominal dc link voltage,n 3383V 4853V 68V Commutation voltage U com =,n / 69.5V 46.5V 359V Rated device voltage U CE,n 3.3kV 4.5kV 6.5kV IGBT or IGBT IGBT 3.3kV IGBT U com@fit 8V 5V 36V U com /U com@fit Converter specifications for the 4L-FLC VC Converter line-to-line voltage U ll,rms,.3kv 3.3kV 4.6kV 6.kV 6.9kV Apparent converter output power c.4mva 3.4MVA 4.3MVA 6.4MVA 7.MVA Nominal dc link voltage,n 3383V 4853V 68V 99V 48V Commutation voltage U com =,n /3 8V 68V 39V 34V 3383V Rated device voltage U CE,n.5kV 3.3kV 4.5kV 6.5kV 6.5kV IGBT IGBT IGBT IGBT IGBT U com@fit V 8V 5V 36V 36V U com /U com@fit Converter specifications for the CLHB VC Converter line-to-line voltage U ll,rms,.3kv 3.3kV 4.6kV 6.kV 6.9kV Apparent converter output power c.4mva 3.4MVA 4.3MVA 6.4MVA 7.MVA Nominal dc link voltage,n 3383V 4853V 68V 99V 48V Number of series connected H-bridges p Dc link voltage of one H-bridge,HB 846V 89V 765V 9V 846V Commutation voltage U com =,HB 846V 89V 765V 9V 846V Number of phase voltage level (p + ) Number of line-to-line voltage level (4p + ) Rated device voltage U CE,n U [email protected] IGBT 9V U com /U com@fit

130

131 6. CONVERTER COMPARION This chapter compares.3kv, 3.3kV, 4.6kV, and 6kV medium voltage converters on the basis of the 3L-NPC VC, 3L-FLC VC, 4L-FLC VC and 5L-, 7L-, 9L-, and L-CLHB VCs topologies applying state-of-the-art.7kv,.5kv, 3.3kV, 4.5kV, and 6.5kV IGBTs. The design of semiconductors and passive components, the semiconductor loss distribution, converter losses, the installed switch power, and the harmonic spectrum will be compared in detail. 6.. Comparison of Power emiconductor Utilization and Loss Distribution Table 6- summarizes the design of the power semiconductors for the two carrier frequencies of f C = 45Hz and f C = Hz at a phase current of I ph,rms, = 6A and a maximum junction temperature of T j, max = 5 C for converter voltages of.3kv, 3.3kV, and 4.6kV in all investigated topologies. The calculated ideal rated IGBT/diode currents I C,n /I F,n (Figure 6-) guarantee that the junction temperature of the mostly stressed IGBT or diode reaches a value of T j,max = 5 C in one worst case operating point of a four-quadrant operation [], [5]. To evaluate the converter topologies for a variety of applications, four different comparison cases are discussed in this section Comparison at Constant Installed witch Power and Constant Carrier Frequency In a first step, a constant carrier frequency (f C = 45Hz / Hz) is assumed for all considered converter topologies. The installed switch power of the 3L-, 4L-FLC VCs, and CLHB VCs are equal to that of the 3L-NPC VC, achieving an output current of 6A in the corresponding output voltage class. This approach allows a comparison of the maximum converter output power C,max and the semiconductor utilization of the considered converter topologies (Table 6-). For line-to-line output voltages of.3kv, 3.3kV, and 4.6kV, the CLHB VCs enable a maximum converter output power C,max, which is increased by.3%, 8.5%, and 36% in comparison to the corresponding 3L-NPC VCs (Table 6- at f C = 45Hz). The total converter losses, efficiencies, the loss distribution, and the harmonic spectrum of the investigated converter topologies are shown in Figure 6- to Figure 6-3, where the installed switch power and the carrier frequency (f C = 45Hz) are constant. Figure 6- depicts the total converter losses (on the left) and efficiencies (on the right) as a function of the phase current in the three investigated output voltage classes. These figures show that the 3L-NPC VCs feature less losses and therefore superior efficiencies, compared to other topologies in the three investigated output voltage classes. The losses of the 5L-CLHB VC are smaller in the entire current range than those of the 3L- and 4L-FLC VCs, assuming a lineto-line voltage of.3kv. The 7L- and 9L-CLHB VCs feature fewer losses up to a phase current 4A for a line-to-line voltage of 3.3kV and 6A for a line-to-line voltage of 4.6kV, compared to the corresponding 3L- and 4L-FLC VCs. Figure 6- shows the loss distribution and the switch utilization of the considered converter topologies if a constant phase current of I ph,rms, = 6A and a constant carrier frequency of f C =

132 8 CONVERTER COMPARION 45Hz are assumed. It is interesting to note that the converter losses (in the left part of Figure 6- ) of the 5L-CLHB VC, 4L-FLC VC, and 3L-FLC VC are increased by.6%, 46.8%, and.8%, compared to the 3L-NPC VC (U ll,rms, =.3kV, C =.39MVA). Furthermore, the 7L-CLHB VC, 4L-FLC VC, and 3L-FLC VC generate 6.5%, 77.7%, and 4.36% more semiconductor losses, compared to the 3L-NPC VC ( C = 3.43MVA), if a line-to-line output voltage of 3.3kV is applied. For a line-to-line output voltage of 4.6kV the converter losses of the 9L-CLHB VC, 4L-, and 3L-FLC VCs produce 8.9%, 9.8%, and 4.4% more semiconductor losses, compared to the 3L-NPC VC ( C = 4.3MVA). Table 6- Power semiconductor design for I ph,rms, = 6A, f C = 45Hz / Hz Converter line-to-line voltage U ll,rms, =.3kV Dc link voltage,n 338.8V Converter topology 3L-NPC 3L-FLC 4L-FLC 5L-CLHB Commutation voltage U com =,n,n /,n /,n / 3,n / 4 / (N-) 69.4V 69.4V 7.6V 845.7V Rated device voltage U CE,n Device commutation voltage U com@fit 3.3kV IGBT FZ8R33KF 3.3kV IGBT FZ8R33KF.5kV IGBT FZR5KF.7kV IGBT FZ6R7KE3 8V 8V V 9V U com /U com@fit Rated IGBT current I C,n (I F,n ) [A] [Hz] [Hz] [Hz] [Hz] [Hz] [Hz] [Hz] T j,max = 5 C, I ph,rms, = 6A Installed switch power [MVA] Converter line-to-line voltage U ll,rms, = 3.3kV Dc link voltage,n V Converter topology 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Commutation voltage U com =,n,n /,n /,n / 3,n / 6 / (N-) 46.8V 46.8V 67.8V 89V Rated device voltage U CE,n 4.5kV IGBT 4.5kV IGBT 3.3kV IGBT CM6HB-9H CM6HB-9H FZ8R33KF U com@fit 5V 5V 8V 9V U com /U com@fit Rated IGBT current I C,n (I F,n ) [A] [Hz] [Hz] [Hz] [Hz] [Hz] [Hz] [Hz].7kV IGBT T j,max = 5 C, I ph,rms, = 6A Installed switch power [MVA] Converter line-to-line voltage U ll,rms, = 4.6kV Dc link voltage,n 68.4V Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Commutation voltage U com =,n,n /,n /,n / 3,n / 8 / (N-) 359.V 359.V 39.4V 765V Rated device voltage U CE,n 6.5kV IGBT 6.5kV IGBT 4.5kV IGBT FZ6R65KF FZ6R65KF CM6HB-9H U com@fit 36V 36V 5V 9V U com /U com@fit Rated IGBT current I C,n (I F,n ) [A] [Hz] [Hz] [Hz] [Hz] [Hz] [Hz] T j,max = 5 C, I ph,rms, = 6A [Hz].7kV IGBT FZ6R7KE3 [Hz] Installed switch power [MVA]

133 CONVERTER COMPARION 9 Table 6- Maximum phase current and apparent converter output power for constant carrier frequency (I ph,rms, = 6A, m a =.5, cosϕ =.9) Converter line-to-line voltage U ll,rms, =.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 5L-CLHB Device part number FZ8R33KF FZ8R33KF FZR5KF FZ6R7KE3 Carrier frequency f C [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Frequency of the first harmonics carrier band f Cb [Hz] Maximum phase current I ph,max T j,max = 5 C Maximum apparent converter output power C,max [MVA] Relative apparent converter output power CR [%] Total harmonic distortion THD [%] Weighted total harmonic distortion WTHD [%] Converter line-to-line voltage U ll,rms, = 3.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Device part number CM6HB-9H CM6HB-9H FZ8R33KF FZ6R7KE3 Carrier frequency f C [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Frequency of the first harmonics carrier band f Cb [Hz] Maximum phase current I ph,max T j,max = 5 C Maximum apparent converter output power C,max [MVA] Relative apparent converter output power CR [%] THD [%] WTHD [%] Converter line-to-line voltage U ll,rms, = 4.6kV Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Device part number FZ6R65KF FZ6R65KF CM6HB-9H FZ6R7KE3 Carrier frequency f C [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Frequency of the first harmonics carrier band f Cb [Hz] Maximum phase current I ph,max T j,max = 5 C Maximum apparent converter output power C,max [MVA] Relative apparent converter output power CR [%] THD [%] WTHD [%]

134 CONVERTER COMPARION Converter semiconductor losses [kw] Converter semiconductor losses [kw] Converter semiconductor losses [kw] L-NPC 3L-FLC 4L-FLC 5L-CLHB Phase current [A] 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Phase current [A] 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Phase current [A] Efficiency [%] (a) U ll,rms, =.3kV Efficiency [%] (b) U ll,rms, = 3.3kV Efficiency [%] (c) U ll,rms, = 4.6kV 3L-NPC 3L-FLC 4L-FLC 5L-CLHB Phase current [A] 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Phase current [A] 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Phase current [A] Figure 6- Converter semiconductor losses and efficiencies as functions of the phase current for the investigated output voltage classes (f C = 45Hz, m a =.5, cosϕ =.9): (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, and (c) U ll,rms, = 4.6kV (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) The switching losses of the 3L-FLC VC are higher than that of the 3L-NPC VC in the three considered output voltage classes (by % for.3kv, 7% for 3.3kV, and 5% for 4.6kV). Furthermore, the switching losses of the 4L-FLC VC are increased by 45.6% (for.3kv), 58.6% (for 3.3kV), and 65.7% (for 4.6kV), compared to the corresponding 3L-NPC VCs. In

135 CONVERTER COMPARION contrast, the switching losses of the 5L-, 7L-, and 9L-CLHB VC topologies are significantly lower than that of the 3L-NPC VCs in all considered output voltage classes (by % for.3kv, 38% for 3.3kV, and 56% for 4.6kV), since the.7kv IGBTs generate distinctly less switching losses than the 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. The conduction losses of the 4L-FLC VC occurring at line-to-line output voltages of.3kv and emiconductor loss distributions [kw] P cont P cond P ont P offt η=98.84% P offd η=99.% η=99.% η=99.9% 3L-NPC 3L-FLC 4L-FLC 5L-CLHB CR [%] %.3% % 93.5% 3L-NPC 3L-FLC 4L-FLC 5L-CLHB (a) U ll,rms, =.3kV emiconductor loss distributions [kw] P cont P cond P ont P offt P offd η=99.6% η=99.4% η=99.5% η=99.47% 3L-NPC 3L-FLC 4L-FLC 7L-CLHB CR [%] % 8.4%.8% 8.5% 3L-NPC 3L-FLC 4L-FLC 7L-CLHB (b) U ll,rms, = 3.3kV emiconductor loss distributions [kw] P cont P cond P ont P offt η=99.% P offd η=99.7% η=99.8% η=99.3% 3L-NPC 3L-FLC 4L-FLC 9L-CLHB CR [%] % 5.%.% % 3L-NPC 3L-FLC 4L-FLC 9L-CLHB (c) U ll,rms, = 4.6kV Figure 6- Converter semiconductor loss distribution at constant carrier frequency (f C = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A): (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, (c) U ll,rms, = 4.6kV (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB- 9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3)

136 CONVERTER COMPARION 3.3kV are increased by 7% and 88% while decreased by.7% for 4.6kV, compared to the corresponding 3L-NPC VCs. The right part of Figure 6- shows that the CLHB VCs and the FLC VCs feature higher converter switch utilization than the 3L-NPC VC, as a reference in the three investigated output voltage classes, while the converter switch utilization of the 4L-FLC VC is decreased by 6.5% if a line-to-line output voltage of.3kv is applied. Figure 6-3 illustrates that the first carrier band of the line-to-line output voltage of the 3L-NPC VC occurs around the carrier frequency of f C = 45Hz. In contrast, the first carrier band of the line-to-line output voltage of the 3L-FLC VC, 4L-FLC VC, 5L-, 7L-, and 9L-CLHB VC is centred around two, three, four, six, and eight times the carrier frequency. Hence, an output filter of the CLHB VCs could be smaller than the corresponding filters of other topologies. The THD decreases when the number of levels increases. The WTHD of the 9L-CLHB VC is clearly lower than that of other topologies due to the nine-level characteristic of the output voltage. Assuming a constant carrier frequency (f C = 45Hz), the WTHD of the 3L-NPC VC (.49%) is almost three, three, five, and fifteen times larger than that of the 4L-FLC VC, 5L- CLHB VC, 7L-CLHB VC, and 9L-CLHB VC respectively (Table 6-). It is important to note that the above-mentioned differences of the output voltage THD and WTHD are primarily caused by the circuit configurations. 3L-NPC 5L-CLHB - - Normalized line-to-line voltage L-FLC L-FLC Normalized line-to-line voltage L-CLHB L-CLHB Frequency [khz] Frequency [khz] Figure 6-3 Harmonic spectrum of line-to-line output voltage at constant carrier frequency (f C = 45Hz, f o = 5Hz, m a =.5, f Cb,3L-NPC = 45Hz, f Cb,3L-FLC = 9Hz, f Cb,4L-FLC = 35Hz, f Cb,5L-CLHB = 8Hz, f Cb,7L-CLHB = 7Hz, f Cb,9L-CLHB = 36Hz) (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) 6... Comparison of Maximum Carrier Frequency at Constant Installed witch Power and Constant Apparent Converter Output Power In the second step, a constant installed switch power (which is a measure for the expense of semiconductors) as well as an equal output current (I ph,rms, = 6A) and constant converter output power C are assumed (Table 6-3) to calculate the maximum carrier frequency of the considered converter topologies.

137 CONVERTER COMPARION 3 Table 6-3 Maximum carrier frequency for constant apparent converter output power and constant installed switch power (I ph,rms, = 6A, m a =.5, cosϕ =.9) Converter line-to-line voltage U ll,rms, =.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 5L-CLHB Device part number FZ8R33KF FZ8R33KF FZR5KF FZ6R7KE3 Carrier frequency f C [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Phase current I ph,rms, [A] Maximum apparent converter output power C,max [MVA] Maximum carrier frequency f C,max T j,max = 5 C, I ph,rms, = A Frequency of the first harmonics carrier band f Cb [Hz] Total harmonic distortion THD [%] Weighted total harmonic distortion WTHD [%] Converter line-to-line voltage U ll,rms, = 3.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Device part number CM6HB-9H CM6HB-9H FZ8R33KF FZ6R7KE3 Carrier frequency f C [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Phase current I ph,rms, [A] Maximum apparent converter output power C,max [MVA] Maximum carrier frequency f C,max T j,max = 5 C, I ph,rms, = A Frequency of the first harmonics carrier band f Cb [Hz] Total harmonic distortion THD [%] Weighted total harmonic distortion WTHD [%] Converter line-to-line voltage U ll,rms, = 4.6kV Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Device part number FZ6R65KF FZ6R65KF CM6HB-9H FZ6R7KE3 Carrier frequency f C [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Phase current I ph,rms, [A] Maximum apparent converter output power C,max [MVA] Maximum carrier frequency f C,max T j,max = 5 C, I ph,rms, = A Frequency of the first harmonics carrier band f Cb [Hz] THD [%] WTHD [%]

138 4 CONVERTER COMPARION The installed switch powers of all topologies are equal to those of the 3L-NPC VC (Table 6-) including NPC diodes. According to section 6.., the maximum switching frequency results from the losses and junction temperatures of the mostly stressed devices (T j,max = 5 C) at critical operating points. Table 6-3 shows that the CLHB VCs enables a higher maximum carrier frequency than the other investigated topologies. Figure 6-4 depicts the total converter losses (on the left) and efficiencies (on the right) as a function of the carrier frequency in the three investigated output voltage classes. These figures demonstrate that the 5L-, 7L-, and 9L-CLHB VC feature less losses and therefore high efficiencies, compared to the 3L-NPC VCs, for a carrier frequency beyond Hz, 9Hz, and 79Hz respectively. Figure 6-5 depicts the power loss distribution and the maximum possible carrier frequencies for a constant apparent converter output power in the three investigated output voltage classes. Assuming a nominal phase current of I ph,rms, = 6A, the converter losses of the 5L-, 7L-, and 9L-CLHB VC are increased by 4%, 5%, and 6% at the maximum carrier frequency in comparison to that of the 3L-NPC VC. It is obvious that the 9L-CLHB VC has the maximum converter losses at the maximum possible carrier frequencies and a line-to-line output voltage 4.6kV, compared to the other topologies. The switching and conduction losses of the 5L-, 7L-, and 9L-CLHB VC are higher than that of the corresponding 3L-NPC VCs (by 7% and 5% for.3kv, 83% and 7% for 3.3kV, and 7% and 7% for 4.6kV). It is interesting to note that the 5L-, 7L-, and 9L-CLHB VC clearly realize the maximum carrier frequencies in the three investigated output voltage classes. The harmonic spectra of the line-to-line output voltage of the considered converters are shown in Figure 6-6 to Figure 6-8. The maximum carrier frequencies of the 3L-FLC VCs are increased by factors of.95 (88Hz for.3kv),.4 (635Hz for 3.3kV), and.3 (595Hz for 4.6kV), compared to those of the 3L-NPC VCs (f C,max = 45Hz). On the other hand, the maximum carrier frequency of the 4L-FLC VC are increased by factors of.75 (79Hz for 3.3kV) and.88 (85Hz for 4.6kV), compared to those of the 3L-NPC VCs (f C,max = 45Hz), whereas it is decreased by factors of.45 (5Hz for.3kv) (Table 6-3). Furthermore, the maximum carrier frequencies of the 5L-CLHB VC (f C,max = 585Hz), 7L-CLHB VC (f C,max = 3Hz), and 9L-CLHB VC (f C,max = 345Hz) are increased by factors of 3.5,.88, and 7.8, compared to those of the 3L-NPC VCs (Table 6-3). The first carrier band of the line-to-line voltage of the 4L-FLC VC occurs around three times (f Cb = 3f C ) the carrier frequencies (75Hz for.3kv, 37Hz for 3.3kV, and 55Hz for 4.6kV). The first carrier band of the line-to-line voltage of the 5L-, 7L-, and 9L-CLHB VCs occur around 6.34kHz, 7.8kHz, and 7.6kHz respectively, whereas the first carrier band generated by the 3L-NPC VC occurs around the carrier frequency f C = 45Hz (Figure 6-8). Thus, for the three considered output voltage classes, the CLHB VCs enable substantially reduced sine output filters, compared to those of the 3L-NPC VCs and both flying capacitor topologies. Comparing the WTHD at the maximum possible carrier frequency, the 9L-CLHB VC features the minimum value of.% since the harmonics of the first carrier band (f Cb = 7.8kHz) are strongly damped. The WTHD of the 5L-CLHB VC (.%) and the 7L- CLHB VC (.78%) are about 95% and 9% smaller than that of the 3L-NPC VC (.49%) since the first harmonics of the 5L-CLHB VC and the 7L-CLHB VC occur at four (f Cb = 4f C ) and six (f Cb = 6f C ) times the carrier frequency, compared to those of the 3L-NPC VC (f Cb = f C ).

139 CONVERTER COMPARION 5 Converter semiconductor losses [kw] Converter semiconductor losses [kw] Converter semiconductor losses [kw] L-NPC 3L-FLC 4L-FLC 5L-CLHB Frequency [Hz] 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Frequency [Hz] 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Frequency [Hz] Efficiency [%] (a) U ll,rms, =.3kV Efficiency [%] (b) U ll,rms, = 3.3kV Efficiency [%] (c) U ll,rms, = 4.6kV 3L-NPC 3L-FLC 4L-FLC 5L-CLHB Frequency [Hz] 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Frequency [Hz] 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Frequency [Hz] Figure 6-4 Converter semiconductor losses and efficiencies as functions of the carrier frequency for the investigated output voltage classes: (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, and (c) U ll,rms, = 4.6kV (f C = 45Hz, I ph,rms, = 6A, m a =.5, cosϕ =.9) (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3)

140 6 CONVERTER COMPARION emiconductor losses distributions [kw] P cont P cond P ont P offt η=98.8% P η=98.98% offd η=98.88% η=99.% 3L-NPC 3L-FLC 4L-FLC 5L-CLHB f C,max / f C [%] % 95.6% % 55.6% 3L-NPC 3L-FLC 4L-FLC 5L-CLHB (a) U ll,rms, =.3kV 5 35 Power loss distributions [kw] 4 3 P cont P cond P ont P η=99.4% offt P offd η=99.47% η=98.8% η=98.9% f C,max / f C [%] 3 % 4.% 75.6% 88.9% 3L-NPC 3L-FLC 4L-FLC 7L-CLHB 3L-NPC 3L-FLC 4L-FLC 7L-CLHB (b) U ll,rms, = 3.3kV emiconductor losses distributions [kw] P cont P cond η=98.45% P ont P offt η=98.8% η=98.78% P offd η=99.3% 3L-NPC 3L-FLC 4L-FLC 9L-CLHB f C,max / f C [%] % 88.9% % 3.% 3L-NPC 3L-FLC 4L-FLC 9L-CLHB (c) U ll,rms, = 4.6kV Figure 6-5 Converter semiconductor loss distribution at maximum carrier frequency (f o = 5Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A, f C = 45Hz), (f C,3L-NPC = 45Hz, f C,3L- FLC,.3kV = 88Hz, f C,3L-FLC,3.3kV = 635Hz, f C,3L-FLC,4.6kV = 595Hz, f C,4L-FLC,.3kV = 5Hz, f C,4L-FLC,3.3kV = 79Hz, f C,4L-FLC,4.6kV = 85Hz, f C,5L-CLHB = 585Hz, f C,7L-CLHB = 3Hz, f C,9L-CLHB =345Hz) (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3)

141 CONVERTER COMPARION 7 Normalized line-to-line voltage - 3L-NPC L-FLC L-FLC L-CLHB Frequency [khz] Figure 6-6 Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f Cb,3L-NPC = 45Hz, f Cb,3L-FLC,.3kV = 76Hz, f Cb,4L-FLC,.3kV = 75Hz, f Cb,5L-CLHB = 634Hz, f o = 5Hz, f C = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A) (3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Normalized line-to-line voltage - 3L-NPC L-FLC L-FLC L-CLHB Frequency [khz] Figure 6-7 Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f Cb,3L-NPC = 45Hz, f Cb,3L-FLC,3.3kV = 7Hz, f Cb,4L-FLC,3.3kV = 37Hz, f Cb,7L-CLHB = 78Hz, f o = 5Hz, f C = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A) (4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.7kV/6A: FZ6R7KE3)

142 8 CONVERTER COMPARION Normalized line-to-line voltage - 3L-NPC - 3 3L-FLC L-FLC L-CLHB Frequency [khz] Figure 6-8 Harmonic spectrum of line-to-line voltage at maximum carrier frequency (f Cb,3L-NPC = 45Hz, f Cb,3L-FLC,4.6kV = 9Hz, f Cb,4L-FLC,4.6kV = 55Hz, f Cb,9L-CLHB = 76Hz, f o = 5Hz, f C = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A) (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H,.7kV/6A: FZ6R7KE3) Comparison of Converter Power and Loss Distribution at Constant Installed witch Power and Constant Frequency of the First Carrier Band The conditions for the third comparison are constant installed switch power and constant frequency of the first harmonic carrier band f Cb. To place the first harmonic carrier band at the frequency occurring in the 3L-NPC VC (f Cb = f C = 45Hz), the carrier frequencies of the different topologies have to be reduced (Table 6-4). This approach allows a comparison of the converter output power and the losses of the considered converter topologies. If the first harmonic carrier band occurs around the same frequency, the design of an output filter of about the same size and cost range is enabled. The maximum apparent converter output powers C,max of the 5L-, 7L-, and 9L-CLHB VCs are increased by 5%,.5%, and 37%, in comparison to the 3L-NPC VC (Table 6-4). Figure 6-9 shows the total converter losses and efficiencies as a function of the phase current and Figure 6- illustrates the power loss distribution and the converter switch utilization of the investigated topologies whereas the installed switch power and the frequency of the first harmonics carrier band are constant (f Cb = f C = 45Hz). The losses of the 5L CLHB VC are smaller in the entire current range (left part of Figure 6-9) and therefore its efficiency is higher (right part of Figure 6-9), compared to that of the corresponding 3L-NPC VC, assuming a lineto-line output voltage of.3kv. In contrast, the 7L- and 9L CLHB VCs feature fewer losses at a phase current of up to 3A and 58A than the corresponding 3L-NPC VC. The semiconductor losses of the 4L-FLC VC are larger in the entire current range for a line-to-line output voltage of.3kv, compared to those of the corresponding 3L-NPC VC. Assuming a nominal phase current of I ph,rms, = 6A, the 5L-, 7L-, and 9L-CLHB VCs feature 8.4% lower, 44.%, and 3.3% higher losses, compared to the corresponding 3L-NPC VCs (Figure 6-).

143 CONVERTER COMPARION 9 Table 6-4 Maximum phase current and apparent converter output power for the constant carrier frequency of the first carrier band and installed switch power (I ph,rms, = 6A, f Cb = 45Hz / Hz, m a =.5, cosϕ =.9) Converter line-to-line voltage U ll,rms, =.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 5L-CLHB Device part number FZ8R33KF FZ8R33KF FZR5KF FZ6R7KE3 Frequency of the first harmonics carrier band f Cb [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Carrier frequency f C [Hz] Maximum phase current I ph,max T j,max = 5 C Maximum apparent converter output power C,max [MVA] Relative apparent converter output power CR [%] Total harmonic distortion THD [%] Weighted total harmonic distortion WTHD [%] Converter line-to-line voltage U ll,rms, = 3.3kV Converter topology 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Device part number CM6HB-9H CM6HB-9H FZ8R33KF FZ6R7KE3 Frequency of the first harmonics carrier band f Cb [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Carrier frequency f C [Hz] Maximum phase current I ph,max T j,max = 5 C Maximum apparent converter output power C,max [MVA] Relative apparent converter output power CR [%] THD [%] WTHD [%] Converter line-to-line voltage U ll,rms, = 4.6kV Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Device part number FZ6R65KF FZ6R65KF CM6HB-9H FZ6R7KE3 Frequency of the first harmonics carrier band f Cb [Hz] Installed switch power [MVA] Rated IGBT current I C,n (I F,n ) [A] Carrier frequency f C [Hz] Maximum phase current I ph,max T j,max = 5 C Maximum apparent converter output power C,max [MVA] Relative apparent converter output power CR [%] THD [%] WTHD [%]

144 CONVERTER COMPARION Converter semiconductor losses [kw] Converter semiconductor losses [kw] Converter semiconductor losses [kw] L-NPC 3L-FLC 4L-FLC 5L-CLHB Phase current [A] 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Phase current [A] 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Phase current [A] Efficiency [%] (a) U ll,rms, =.3kV Efficiency [%] (b) U ll,rms, = 3.3kV Efficiency [%] (c) U ll,rms, = 4.6kV 3L-NPC 3L-FLC 4L-FLC 5L-CLHB Phase current [A] 3L-NPC 3L-FLC 4L-FLC 7L-CLHB Phase current [A] 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Phase current [A] Figure 6-9 Converter semiconductor losses as functions of the phase current for the investigated output voltage classes: (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, and (c) U ll,rms, = 4.6kV (f C,3L-NPC = 45Hz, f C,3L-FLC = 5Hz, f C,4L-FLC = 5Hz, f C,5L-CLHB =.5Hz, f C,7L-CLHB = 75Hz, f C,9L-CLHB = 56.5Hz, f o = 5Hz, f Cb = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB- 9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3)

145 CONVERTER COMPARION emiconductor loss distributions [kw] P cont P cond P ont P offt P offd η=99.4% η=99.% η=99.5% η=99.7% 3L-NPC 3L-FLC 4L-FLC 5L-CLHB CR [%] % 4.8% % 3.5% 3L-NPC 3L-FLC 4L-FLC 5L-CLHB (a) U ll,rms, =.3kV emiconductor loss distributions [kw] P cont P cond P ont P offt P offd η=99.4% η=99.3% η=99.47% η=99.46% 3L-NPC 3L-FLC 4L-FLC 7L-CLHB CR [%] % 9.%.7% % 3L-NPC 3L-FLC 4L-FLC 7L-CLHB (b) U ll,rms, = 3.3kV emiconductor loss distributions [kw] P cont P cond P ont P offt η=99.3% η=99.3% P offd η=99.9% η=99.46% 3L-NPC 3L-FLC 4L-FLC 9L-CLHB CR [%] % 33.5% 36.8% % 3L-NPC 3L-FLC 4L-FLC 9L-CLHB (c) U ll,rms, = 4.6kV Figure 6- Converter semiconductor loss distribution at constant frequency of the first carrier band (f C = f Cb = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A): (a) U ll,rms, =.3kV, (b) U ll,rms, = 3.3kV, (c) U ll,rms, = 4.6kV (f C,3L-NPC = 45Hz, f C,3L-FLC = 5Hz, f C,4L-FLC = 5Hz, f C,5L-CLHB =.5Hz, f C,7L-CLHB = 75Hz, f C,9L-CLHB = 56.5Hz, f o = 5Hz, f Cb = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3)

146 CONVERTER COMPARION The switching losses of the 5L-, 7L-, and 9L-CLHB VCs are significantly lower than those of the 3L-NPC VC (76% for.3kv, 88% for 3.3kV, and 94% for 4.6kV), since the.7kv IGBTs generate distinctly less switching losses than the.5kv, 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. On the other hand, the conduction losses of the 5L-, 7L-, and 9L-CLHB VCs are increased by 5% for.3kv, 8% for 3.3kV, and 7% for 4.6kV, compared to the corresponding 3L-NPC VC topologies. For a line-to-line output voltage of.3kv, the 4L-FLC VC features the highest losses and the lowest converter output power, whereas the 7L- and 9L-CLHB VCs have the maximum value for line-to-line output voltages of 3.3kV and 4.6kV respectively. The 3L-FLC VC enables the maximum converter switch utilization, compared to that of the corresponding 3L-NPC VCs in the three investigated output voltage classes, as shown in the right part of Figure 6-. Furthermore, both three-level topologies provide the poorest THD and WTHD (Table 6-4). Both the THD and the WTHD of the 9L-CLHB VC are clearly the smallest, since the distortion of the output voltage is at a minimum due to the applied nine levels. The harmonic spectra of the converters are shown in Figure 6-. The first carrier band of all investigated topologies occurs at about the first harmonic carrier band f Cb. 3L-NPC 5L-CLHB - - Normalized line-to-line voltage L-FLC L-FLC Normalized line-to-line voltage L-CLHB L-CLHB Frequency [Hz] Frequency [Hz] Figure 6- Harmonic spectrum of line-to-line voltage at constant frequency of the first carrier band (f C,3L-NPC = 45Hz, f C,3L-FLC = 5Hz, f C,4L-FLC = 5Hz, f C,5L-CLHB =.5Hz, f C,7L- CLHB = 75Hz, f C,9L-CLHB = 56.5Hz, f o = 5Hz, f Cb = 45Hz, m a =.5, cosϕ =.9, I ph,rms, = 6A), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Figure 6- shows the junction temperatures of IGBTs and diodes of one phase leg of the investigated topologies. It is apparent that all IGBTs and diodes reach their maximum junction temperature at the critical operating point, see Table 5-. Figure 6-a demonstrates that the junction temperatures of a 3L-NPC VC are not equally distributed, unlike in the other topologies (Figure 6-b through Figure 6-d). This non-

147 CONVERTER COMPARION 3 equality leads to the maximum junction temperature to the outer IGBTs (T and Τ ). Obviously both switches are subject to switching losses as well as substantial conduction losses at a large modulation index and unity power factor. In contrast, the inner switches (T and Τ ) cause only conduction losses at this operating point. ince there are no conduction and switching losses in the inverse diodes, the sum of conduction and switching losses and thus the junction temperatures of the NPC diodes (D, D ) are larger than those of the inner inverse diodes ( D,D ). T T Junction Temperature [ C] Junction Temperature [ C] 3L-NPC T T T T D T D T D T D T D D 4L-FLC T 3 T T T T T 3 D T3 D T D T D T D T DT3 3L-FLC T T T T D T D T D T D T 9L-CLHB T L T L T R T R D L D L D R DR Figure 6- Average junction temperature of IGBTs and diodes (,n = 68V, m a =.5, cosϕ =, T h = 8 C): (a) 3L-NPC VC (Eupec 6.5kV/74.4A IGBT, I ph,max = 6A, C = 4.3MVA, f C = 45Hz), (b) 3L-FLC VC (Eupec 6.5kV/863.4A IGBT, I ph,max = 99A, C = 6.6MVA, f C = 5Hz), (c) 4L-FLC VC (Mitsubishi 4.5kV/83A IGBT, I ph,max = 6A, C = 7.64MVA, f C = 5Hz), (d) 9L-CHB VC (Eupec.7kV/85.8A IGBT, I ph,max = 89A, C = 6.4MVA, f C = 56.5Hz) Comparison of 4.6kV, 4.3MVA Multi-Level Converters at Constant Efficiency The conditions for the fourth aspect of comparison are a constant converter efficiency of about 99% at a constant converter power of C = 4.3MVA, assuming a line-to-line voltage of 4.6kV. To compare the converter switch utilization of the three-level topologies (i.e. the 3L-NPC VC and 3L-FLC VC), 6.5kV IGBTs/diodes and a series connection of two 3.3kV IGBTs/diodes are considered. Table 6-5 summarizes the design of the power semiconductors while assuming a carrier frequency of f C = 45Hz in all topologies. In a second step, the carrier frequencies, the ideal rated IGBT/diode currents, and thus the installed switch powers were determined in an iterative simulation procedure to achieve both the efficiency requirement (η 99%) at the specified converter power and a junction temperature of

148 4 CONVERTER COMPARION T j,max = 5 C at one worst case operating point [5], [9]. Table 6-6 depicts the resulting ideal rated currents, installed switch powers, and carrier frequencies. The 3L-NPC VC is used as a reference. Figure 6-3b shows the efficiencies as a function of the phase current. It is remarkable that the efficiency of the 3L-NPC VC (f C = 45Hz) is higher and that there are thus smaller losses than in the other topologies in the entire current range. Table 6-5 Converter voltage and semiconductor specifications for a constant converter power and carrier frequency (U ll,rms, = 4.6kV, I ph,rms, = 6A, C = 4.3MVA, f C = 45Hz, T j,max = 5 C), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Converter line-to-line voltage U ll,rms, 4.6kV Dc link voltage,n 68.5V Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Rated device voltage U CE,n 6.5kV x3.3kv 6.5kV x3.3kv 4.5kV.7kV IGBT IGBT IGBT IGBT IGBT IGBT,n /,n / 4,n /,n / 4,n / 3,n / 8 Commutation voltage U com 359.V 59.6V 359.V 59.6V 39.5V 765V U com@fit 36V x8v 36V x8v 5V 9V U com /U com@fit Rated IGBT current I C,n (I F,n T j,max = 5 C, f C =45Hz, I ph,rms, = 6A Installed switch power Relative installed switch power R 74.4A 594.4A 768A 6.6A 68A 67.A.6 MVA 8.38 MVA MVA 7.47 MVA 8.74 MVA 74.3 MVA.6% % 6.6% 86.7%.4% 9.% Table 6-6 Carrier and harmonic carrier band frequencies, capacity of flying capacitors, and installed switch power for a converter efficiency of about 99% (U ll,rms, = 4.6kV, I ph,rms, = 6A, C = 4.3MVA), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) Converter topology 3L-NPC 3L-FLC 4L-FLC 9L-CLHB Nominal devices voltage 6.5kV x3.3kv 6.5kV x3.3kv IGBT IGBT IGBT IGBT 4.5kV IGBT.7kV IGBT Nominal devices current 74.4A 748A 768A 638.4A 734.A 655.7A Converter efficiency η 99.3% 98.95% 98.96% 98.88% 98.99% 98.9% Carrier frequency f C 45Hz 5Hz 475Hz 65Hz 6Hz 55Hz Frequency of the first harmonics carrier band f Cb 45Hz 5Hz 95Hz 3Hz 83Hz 94Hz Capacity of the flying capacitors C, µF 4µF 36µF - tored energy of the flying capacitors E C J 996J 478J - Installed switch power Relative installed switch power R.6 MVA 3.67 MVA 6.83 MVA MVA 87.4 MVA 79.3 MVA 97.5% % 58.7% 73.% 84.3% 76.5%

149 CONVERTER COMPARION 5 It is furthermore interesting to note that the application of two series connected 3.3kV IGBTs/diodes increases the installed switch power by.6% at a 77.8% higher switching frequency, compared to the use of 6.5kV IGBTs/diodes. The distribution of conduction and switching losses (Figure 6-3a) demonstrates that the series connection of 3.3kV IGBTs enables an almost equal share of switching and on state losses for f C = 5Hz. In contrast, the switching losses of 6.5kV IGBTs cause about two-thirds of the total losses at f C = 45Hz, because these devices are optimized for distinctly lower switching frequencies. Both on state and switching losses of the 3L-FLC VC are slightly higher, compared to the 3L- NPC VC, at an identical frequency of the first carrier band since the ideal current ratings of the switches in the 3L-FLC VC are distinctly lower due to the better loss distribution [], [4], [5]. The installed switch powers of the 3L-, 4L-FLC VCs, and the 9L-CLHB VC are reduced by 4.3%, 5.7%, and 3.5% respectively, in comparison to the 3L-NPC VC (f C = 5Hz), applying two series connection of a 3.3kV IGBT/diode (Figure 6-3c). Therefore, unlike the other topologies, the 3L-FLC VC enables maximum switch utilization (Figure 6-3d). The loss distribution shows an extremely low share of switching losses in the 9L-CLHB VC (Figure 6-3a). emiconductor losses distributions [kw] P cont P cond P ont P offt P offd (3.3kV) 6.5kV (3.3kV) 4.5kV.7kV 6.5kV 3L-NPC 3L-FLC 4L-FLC 9L-CLHB (a) Efficiency [%] L-NPC(6.5kV IGBT) 3L-NPC(*3.3kV IGBT) 3L-FLC(6.5kV IGBT) 3L-FLC(*3.3kV IGBT) 4L-FLC(4.5kV IGBT) 9L-CLHB(.7kV IGBT) Phase current [A] (b) 97.5% % 8 73.% 84.3% 76.5% R [%] % 6.5kV IGBT *(3.3kV IGBT) 6.5kV IGBT *(3.3kV IGBT) 4.5kV IGBT.7kV IGBT 3L-NPC 3L-FLC 4L-FLC 9L-CLHB (c) Figure 6-3 Loss distribution (a), efficiency (b), and relative installed switch power (c) ( c = 4.3MVA, I ph,rms, = 6A, f o = 5Hz, m a =.5, cosϕ =.9, T jmax = 5 C, f C,3L- NPC-6.5kV = 45Hz, f C,3L-NPC-3.3kV = 5Hz, f C,3L-FLC-6.5kV = 475Hz, f C,3L-FLC-3.3kV = 65Hz, f C,4L-FLC-4.5kV = 6Hz, f C,9LCLHB-.7kV = 5Hz), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3)

150 6 CONVERTER COMPARION The values of the flying capacitors are depicted in Table 6-6, according to equation (5-5). The stored energy in the flying capacitors of the 4L-FLC VC is more than the factors of.5 (f C = 475Hz) and (f C = 65Hz) and higher than that of the 3L-FLC VC, which results in substantially higher expenses of capacitors in the 4L-FLC VC. The simulated voltage ripple U C and current i C,rms of the flying capacitors are depicted in Figure 6-4 and Figure 6-5 as functions of the modulation index m a and the phase shift ϕ between the converter output voltage and current for the carrier frequency of f C = Hz [4], [9]. The maximum voltage ripple and current stress of the 3L-FLC VC occur at a modulation index of m a = ( U C,max = 46V, i C,max = 6A (see Figure 6-4)), while the maximum voltage ripple of the 4L-FLC VC occurs at m a =.88 and ϕ = 9 ( U C,max = 589V (see Figure 6-5)). The capacitor current of the 4L-FLC VC reaches a maximum in the modulation range of < m a <.33 independent of ϕ (i C,max = 489A (see Figure 6-5)). The voltage and current ripple of the 4L-FLC VC are about 9% higher and 8% lower respectively than that of the 3L-FLC VC [9] i C,rms [A] 4 U C [V] Phase shift [deg]..8.4 Modulation index m a 8 9 Phase shift [deg]..8.4 Modulation index m a (a) i C,max = m a =, ϕ = 8 (b) U C,max = m a =, ϕ = 8 Figure 6-4 Flying capacitor current (a) and voltage ripple (b) of a 3L-FLC VC as functions of the modulation index and phase shift (I ph,rms, = 6A, f C,3L-FLC = Hz, C = 77µF) 5 6 i C,rms [A] U C [V] Phase shift [deg]..8.4 Modulation index m a 8 9 Phase shift [deg]..8.4 Modulation index m a (a) i C,max = < m a <.33, ϕ = 8 (b) U C,max = 589V@ m a =.88, ϕ = 9 Figure 6-5 Flying capacitor current (a) and voltage ripple (b) of a 4L-FLC VC as functions of the modulation index and phase shift (I ph,rms, = 6A, f C,4L-FLC = Hz, C, = 58µF)

151 CONVERTER COMPARION 7 The harmonic spectra of the line-to-line output voltage of the considered converters are shown in Figure 6-6. The first carrier band of the line-to-line voltage of the 3L-NPC VC occurs at the carrier frequency of f C = 45Hz using 6.5kV IGBTs. On the other hand, the first carrier band of the line-to-line voltage of the 3L- and 4L-FLC VCs are increased by a factor of (f Cb = 95Hz) and 4 (f Cb = 83Hz) respectively, compared to the 3L-NPC VC (Table 6-6). In contrast, the first carrier band of the line-to-line output voltage of the 9L-CLHB VC (f Cb = 94Hz) is centred around twenty times the carrier frequency (f Cb = f C ) (Figure 6-6). Hence, an output filter of the 9L-CLHB VC could be smaller than the corresponding filters of the other topologies. f C,3L-NPC-6.5kV = 45Hz f C,3L-FLC-6.5kV = 475Hz - - Normalized line-to-line voltage f C,3L-NPC-3.3kV = 5Hz f C,4L-FLC-4.5kV = 6Hz Normalized line-to-line voltage f C,3L-FLC-3.3kV = 65Hz f C,9L-CHB-.7kV = 5Hz Frequency [khz] Frequency [khz] Figure 6-6 Harmonic spectrum of line-to-line voltage at constant efficiency (I ph,rms, = 6A, f o = 5Hz, m a =.5, cosϕ =.9, T jmax = 5 C, f C,3L-NPC-6.5kV = 45Hz, f C,3L-NPC-3.3kV = 5Hz, f C,3L-FLC-6.5kV = 475Hz, f C,3L-FLC-3.3kV = 65Hz, f C,4L-FLC-4.5kV = 6Hz, f C,9LCLHB-.7kV = 5Hz) 6.. Comparison of Power emiconductor Utilization and Loss Distribution for.3kv-6kv Multi-Level Converters (3L-NPC VC and CLHB VCs) Among the aforementioned medium voltage converters, this section takes only the 3L-NPC VC and the CLHB VCs into account. The converter output power and the semiconductor utilization are examined at the three different carrier frequencies of 45Hz, 75Hz, and 5Hz for line-to-line output voltages of.3kv, 3.3kV, 4.6kV, and 6kV. Table 6-7 depicts the technical data and conditions of the considered converter topologies. The loss distribution and the relative installed switch power of the investigated converter topologies are shown in Figure 6-7, assuming the constant carrier frequency (45Hz, 75Hz, and 5Hz) and a constant phase current (I ph,rms, = 6A). It is interesting to note that the 5L-, 7L-, and 9L-CLHB VCs generate higher converter losses than the corresponding 3L-NPC VCs in the output voltage classes of.3kv, 3.3kV, and 4.6kV. In contrast, for a line-to-line output voltage of 6kV, the converter losses of the L-CLHB VC are reduced by 8% at f C = 45Hz, 3.% at f C = 75Hz, and 8.9% at f C = 5Hz, compared to the 3L-NPC VCs. The switching losses of the CLHB VCs (5L-, 7L-, 9L-, and L) topologies are significantly lower than that of the 3L-NPC VCs in all considered output voltage classes and carrier

152 8 CONVERTER COMPARION frequencies (for example, % for.3kv, 39% for 3.3kV, and 59% for 4.6kV, and 6kV at f C = 45Hz), since the.7kv IGBTs generate distinctly less switching losses than the 3.3kV, 4.5kV, and 6.5kV IGBTs at their corresponding commutation voltage. On the other hand, the conduction losses of the CLHB VCs occurring at line-to-line output voltages of.3kv, 3.3kV, 4.6kV, and 6kV are increased in all considered carrier frequencies, compared to the 3L- NPC VC topology (6%, 45%, %, and 7% at f C = 75Hz). It is remarkable that the relative installed switch power R of the CLHB VCs decreases when increasing the line-to-line output voltage and the carrier frequency (Figure 6-7). Table 6-7 Power semiconductor design (I ph,rms, = 6A, m a =.5, cosϕ =.9) Converter line-to-line voltage U ll,rms, =.3kV Topology 3L-NPC VC 5L-CHLB VC 7L-CHLB VC IGBT/Diode 3.3kV/8A IGBT.7kV/6A IGBT.7kV/6A IGBT Device number FZ8R33KF FZ6R7KE3 FZ6R7KE3 U com [V] f C [Hz] f Cb [Hz] I C,n (I F,n ) [A] [MVA] R [%] % % % 89% 84% 8% 3% 3% 9% Converter line-to-line voltage U ll,rms, = 3.3kV Topology 3L-NPC VC 7L-CHLB VC IGBT/Diode 4.5kV/6A IGBT (3.3kV/8A IGBT).7kV/6A IGBT Device number CM6HB-9H (FZ8R33KF) FZ6R7KE3 U com [V] 46.7 (3.35) 88.9 f C [Hz] f Cb [Hz] I C,n (I F,n ) [A] [MVA] R [%] % % % % 5% 88% 9% 78% 6% Converter line-to-line voltage U ll,rms, = 4.6kV Topology 3L-NPC VC 9L-CHLB VC IGBT/Diode 6.5kV/6A IGBT (3.3kV/8A IGBT).7kV/6A IGBT Device number FZ6R65KF (FZ8R33KF) FZ6R7KE3 U com [V] 359. (59.6) f C [Hz] f Cb [Hz] I C,n (I F,n ) [A] [MVA] R [%] % % % 74.4% 64% 58% 73.5% 6% 5% Converter line-to-line voltage U ll,rms, = 6kV Topology 3L-NPC VC L-CHLB VC IGBT/Diode (6.5kV/6A IGBT) 3 (3.3kV/8A IGBT).7kV/6A IGBT Device number (FZ6R65KF) 3 (FZ8R33KF) FZ6R7KE3 U com [V] (6.) 3 (47.7) 88.5 f C [Hz] f Cb [Hz] I C,n (I F,n ) [A] [MVA] R [%] % % % 67% 57% 5% 56% 45% 38%

153 CONVERTER COMPARION 9 Power loss distribution [kw] P cont P cond 3*3.3kV *6.5kV P ont.7kv P offt.7kv *3.3kV *3.3kV P offd.7kv.7kv 6.5kV.7kV 3.3kV 4.5kV 3L-NPC 5L-CLHB 7L-CLHB 3L-NPC 3L-NPC 7L-CLHB 3L-NPC 3L-NPC 9L-CLHB 3L-NPC 3L-NPC L-CLHB.3kV 3.3kV 4.6kV 6kV Relative installed switch power [%] %3 % % % % % %89 %9 %74 %74 %67 3L-NPC (3.3kV IGBT) 5L-CLHB (.7kV IGBT) 7L-CLHB (.7kV IGBT) 3L-NPC (4.5kV IGBT) 3L-NPC (*3.3kV IGBT) 7L-CLHB (.7kV IGBT) 3L-NPC (6.5kV IGBT) 3L-NPC (*3.3kV IGBT) 9L-CLHB (.7kV IGBT) 3L-NPC (*6.5kV IGBT) 3L-NPC (3*3.3kV IGBT).3kV 3.3kV 4.6kV 6kV L-CLHB(.7kV IGBT) %56 (a) f C = 45Hz Power loss distribution [kw] P cont *6.5kV P 3*3.3kV cond.7kv P ont P.7kV offt *3.3kV *3.3kV P 6.5kV offd.7kv.7kv.7kv 3.3kV 4.5kV 3L-NPC 5L-CHB 7L-CHB 3L-NPC 3L-NPC 7L-CHB 3L-NPC 3L-NPC 9L-CHB 3L-NPC 3L-NPC L-CHB.3kV 3.3kV 4.6kV 6kV Relative installed switch power [%] %3 %5 % % % % %84 %78 %64 %6 3L-NPC (3.3kV IGBT) 5L-CLHB (.7kV IGBT) 7L-CLHB (.7kV IGBT) 3L-NPC (4.5kV IGBT) 3L-NPC (*3.3kV IGBT) 7L-CLHB (.7kV IGBT) 3L-NPC (6.5kV IGBT) 3L-NPC (*3.3kV IGBT) 9L-CLHB(.7kVIGBT) 3L-NPC (*6.5kV IGBT) %57 3L-NPC(3*3.3kVIGBT).3kV 3.3kV 4.6kV 6kV %45 L-CLHB (b) f C = 75Hz Power loss distribution [kw] P cont P cond P ont P *3.3kV.7kV offt *3.3kV 6.5kV P offd.7kv.7kv.7kv 4.5kV 3.3kV *6.5kV 3L-NPC 5L-CHB 7L-CHB 3L-NPC 3L-NPC 7L-CHB 3L-NPC 3L-NPC 9L-CHB 3L-NPC 3L-NPC L-CHB.3kV 3.3kV 4.6kV 6kV 3*3.3kV.7kV Relative installed switch power [%] %9 % % % % %88 %8 %6 3L-NPC (3.3kV IGBT) 5L-CLHB (.7kV IGBT) 7L-CLHB (.7kV IGBT) 3L-NPC (4.5kV IGBT) 3L-NPC (*3.3kV IGBT) 7L-CLHB(.7kVIGBT) 3L-NPC (6.5kV IGBT) %58 %5 3L-NPC(*3.3kVIGBT) 9L-CLHB(.7kV) 3L-NPC (*6.5kV IGBT) %5 3L-NPC(3*3.3kV).3kV 3.3kV 4.6kV 6kV %38 L-CLHB (c) f C = 5Hz Figure 6-7 emiconductor loss distribution and relative installed switch power occurring at line-to-line output voltages of.3kv, 3.3kV, 4.6kV, and 6kV at the different switching frequencies of 45Hz, 75Hz, and 5Hz (I ph,rms, = 6A, f o = 5Hz, m a =.5, cosϕ =.9, T jmax = 5 C), (6.5kV/6A: FZ6R65KF, 4.5kV/6A: CM6HB-9H, 3.3kV/8A: FZ8R33KF,.5kV/A: FZR5KF,.7kV/6A: FZ6R7KE3) For all examined output voltage classes and carrier frequencies, the CLHB VCs enable a minimum installed switch power which is decreased, for example, by 8% for.3kv, 38% for

154 3 CONVERTER COMPARION 3.3kV, 5% for 4.6kV, and 6% for 6kV at the carrier frequency of f C = 5Hz, in comparison to the corresponding 3L-NPC VCs (Table 6-7). Furthermore, the first carrier band of the line-to-line output voltage of the 3L-NPC VC occurs around the carrier frequency (f Cb = f C ), whereas the first carrier band of the line-to-line output voltage of the 5L-, 7L-, 9L-, and L-CLHB VCs are centred around four, six, eight, and ten times the carrier frequency respectively. Hence, an output filter of the CLHB VCs could be smaller than the corresponding filters of the 3L-NPC VC topology Comparison of the DC Link Capacitor for a 4-pulse, 4.6kV, 4.3MVA, 3L-NPC VC and 9L-CLHB VC Comparison of the dc link capacitor for a 4-pulse, 4.6kV, 4.3MVA, 3L-NPC VC and 9L- CLHB VC is the purpose of this section (refer to Figure 4-). Design criteria like the dc link voltage ripples and the dc link capacitor storage energy are considered to determine the suitable size of the dc link capacitor. In a first step, the maximum value of the ripple in the dc link capacitor current is computed, considering the influence of the operating parameters at the inverter mode, e.g. load angle (ϕ = ) and the modulation index (m a =.5). Due to capacitor voltage balancing in the 3L-NPC VC, the dc link capacitors are replaced by constant ideal voltage sources, of which each is one-half of the dc link voltage. A three-phase sinusoidal current source with a constant amplitude of 85A is assumed as a load. Figure 6-8 illustrates the root mean square (rms), average and ripple current at the dc rail of the capacitor bank (according to Figure 3-6 and Figure 3-39) as a function of the modulation index m a and load angle ϕ. They show that the result is symmetrical concerning the axle of the load angle, and the maximum value of the ripple current occurs at m a =.6 and ϕ =, ±8 in the 3L-NPC VC (Figure 6-8c) and m a =.5 and ϕ =, ±8 in the 9L-CLHB VC (Figure 6-8f). In a second step, to investigate the dc link voltage ripple, the grid, and load currents (according to Figure 4-) the modulation index of m a =.6 (for the 3L-NPC VC) and m a =.5 (for the 9L-CLHB VC) are accepted. The minimum size of the dc link capacitor is determined by using equation (5-3) for the 3L-NPC VC and equation (5-4) for the 9L-CHB VC, applying a voltage ripple of 5%, and equation (5-5), assuming a stored energy of 6J/kVA and J/kVA. A standard three-phase symmetric load model was realized by applying a load power factor cosϕ =.9 and a machine leakage inductance of L L = % (.37mH). The machine resistance is assumed insignificant. The system is simulated by a MATLAB program. Figure 6-8Figure 6-9 through Figure 6-8 present the simulation results in the steady state at % load for carrier frequency f C = 75Hz. Figure 6-9 and Figure 6- show the grid currents, the transformer primary and secondary winding currents in each -pulse transformer, and their harmonic spectrum at a stored energy of 6J/kVA and J/kVA for the 3L-NPC VC respectively. Because of the first dominant utility grid, the phase current harmonics are 3 rd and 5 th ; then the low-frequency harmonic waves are eliminated. The first dominant transformer primary current harmonics are th and 3 th. The transformer secondary winding currents have harmonic components with low ordinal numbers (h=6k ±, where k=,...). It is evident that the amplitude of all harmonics are reduced applying a stored energy of J/kVA instead of 6J/kVA. The rectifier output voltage, the rectifier output current, the capacitor voltage ripples, and their harmonic spectrum are depicted in Figure 6-3 and Figure 6-4 at a stored energy of 6J/kVA and J/kVA for the 3L-NPC VC respectively. The results show that the dc link voltage ripple and the dc link current are about.3% and 4.96% for the stored energy of 6J/kVA, while they

155 CONVERTER COMPARION 3 enable a reduction by 55% and by 47.6% at twice the stored energy. It is to remark that the dc link voltage ripple of each H-bridge cell of the 9L-CLHB VC is larger than the acceptable value of 5%, assuming a stored energy of J/kVA (Figure 6-, Figure 6-5). Therefore, in order to place the dc link voltage ripple at a permissible limit, an increase in the dc link capacitor by the factor of.83 and a recalculation of the stored energy of 34J/kVA are necessary, compared to the stored energy of J/kVA (Figure 6-, Figure 6-6). Figure 6-7 and Figure 6-8 illustrate the capacitor currents, the output phase-midpoint voltage, the load phase currents, and their harmonic spectrum at a stored energy of 6J/kVA and J/kVA respectively. It can be seen that the odd harmonics in the phase-midpoint voltage U am centred around the switching frequency and its multiples.

156 3 CONVERTER COMPARION (a) (d) (b) (e) (c) (f) Figure 6-8 The effective, average, and ripple capacitor current as a function of the modulation index and load angle in the 3L-NPC VC according to Figure 3-6: (a-c) (i dc,eff,max /i ph,peak = 85.6% at φ = ±8, and m a =.5), (i dc,avg,max /i ph,peak = 8.3% at φ = and m a =.5), (i dc,rip,max /i ph,peak = 45.8% at φ = ±8, and m a =.6), and in the 9L-CLHB VC according to Figure 3-39 (d-f).(i dc,eff,max /i ph,peak = 68.7% at φ = ±8, and m a =.5), (i dc,avg,max /i ph,peak = 57.5% at φ = and m a =.5), (i dc,rip,max /i ph,peak = 54.3% at φ = ±9, and m a =.5), (i ph,rms, = 6A, f C = 75Hz, f o = 5Hz)

157 CONVERTER COMPARION 33 i s,x [A] - i sa i sb i sc Amplitude i s,x Time [sec.] (a) Harmonics order (b) 5 I p,x [A] -5 I pu I pv I pw Amplitude I px Time [sec.] (c) Harmonics order (d) 4 I s,x [A] I s,u I s,u I s3,u I s4,u Amplitude I s,x Time [sec.] (e) Harmonics order (f) Figure 6-9 (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VC, (c, d): transformer primary phase currents of the -pulse transformer and their harmonic spectra in the 3L-NPC VC, (e, f): transformer secondary phase currents of the -pulse transformer and their harmonic spectra in the 3L-NPC VC (E = 6J/kVA, C = C =.77mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

158 34 CONVERTER COMPARION i s,x [A] - i sa i sb i sc Amplitude i s,x Time [sec.] (a) Harmonics order (b) 5 I p,x [A] -5 I pu I pv I pw Amplitude I p,x Time [sec.] (c) Harmonics order (d) 4 I s,x [A] I s,u I s,u I s3,u I s4,u Amplitude I s,x Time [sec.] (e) Harmonics order (f) Figure 6- (a, b): Utility grid phase current and its harmonic spectra in the 3L-NPC VC, (c, d): transformer primary phase currents of the -pulse transformer and their harmonic spectra in the 3L-NPC VC, (e, f): transformer secondary phase currents of the -pulse transformer and their harmonic spectra in the 3L-NPC VC (E = J/kVA, C = C = 5.54mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

159 CONVERTER COMPARION 35 i sx [A] i sa i sb i sc Amplitude i sx Time [sec.] (a) Harmonics order (b) 5 I px [A] -5 I pu I pv I pw Amplitude I px Time [sec.] (c) Harmonics order (d) 4 I s 5 I s I sx [A] I s3 I s4 Amplitude I sx Time [sec.] (e) Harmonics order (f) Figure 6- (a, b): Utility grid phase current and its harmonic spectra in the 9L-CLHB VC, (c, d): transformer primary phase currents of the -pulse transformer and their harmonic spectra in the 9L-CLHB VC, (e, f): transformer secondary phase currents of the -pulse transformer and their harmonic spectra in the 9L-CLHB VC (E = J/kVA, C = C = 4.8mF, f C = 75Hz, f o = 5Hz, m a =.5, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

160 36 CONVERTER COMPARION i sx [A] i sa i sb i sc Amplitude i sx Time [sec.] (a) Harmonics order (b) 5 I px [A] I p I p I p3 Amplitude I px Time [sec.] (c) Harmonics order (d) 5 I sx [A] Amplitude I sx Time [sec.] (e) Harmonics order (f) Figure 6- (a, b): Utility grid phase current and its harmonic spectra in the 9L-CLHB VC, (c, d): transformer primary phase currents of the -pulse transformer and their harmonic spectra in the 9L-CLHB VC, (e, f): transformer secondary phase currents of the -pulse transformer and their harmonic spectra in the 9L-CLHB VC (E = 34J/kVA, C = C = 44mF, f C = 75Hz, f o = 5Hz, m a =.5, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

161 CONVERTER COMPARION [V] Amplitude Time [sec.] (a) Harmonics order (b) 33 3 i dc [A] 3 3 Amplitude i dc Time [sec.] (c) Harmonics order (d) 384 U C U C U Cx [V] 37 Amplitude U Cx Time [sec.] (e) Harmonics order (f) Figure 6-3 (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VC, (c, d): dc link current and its harmonic spectra, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VC (E = 6J/kVA, C = C =.77mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

162 38 CONVERTER COMPARION 65 4 [V] Amplitude Time [sec.] (a) Harmonics order (b) 33 3 i dc [A] 3 3 Amplitude i dc Time [sec.] (c) Harmonics order (d) 348 U C 4 U C U Cx [V] 3 Amplitude U Cx Time [sec.] (e) Harmonics order (f) Figure 6-4 (a, b): DC link voltage ripple and its harmonic spectra in the 3L-NPC VC, (c, d): dc link current and its harmonic spectra in the 3L-NPC VC, (e, f): capacitor voltage ripples and their harmonic spectra in the 3L-NPC VC (E = J/kVA, C = C = 5.54mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

163 CONVERTER COMPARION 39 8 HB [V] 6 4 HB, HB, HB,3 Amplitude,HB HB, Time [sec.] (a) Harmonics order (b) 8 i dc i dc i dcx [A] 6 4 i dc3 i dc4 Amplitude,HB Time [sec.] (c) Harmonics order (d) U an [V] Time [sec.] (e) Amplitude U an Harmonics order (f) Figure 6-5 (a, b): DC link voltage ripple and its harmonic spectra in the 9L-CLHB VC, (c, d): dc link current and its harmonic spectra in the 9L-CLHB VC, (e, f): phase output voltage and its harmonic spectra in the 9L-CLHB VC (E = J/kVA, C = C = 4.8mF, f C = 75Hz, f o = 5Hz, m a =.5, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

164 4 CONVERTER COMPARION 8 HB [V] 6 4 HB, HB, HB,3 Amplitude i dc,x HB, Time [sec.] (a) Harmonics order (b) 8 i dc i dc i dcx [A] 6 4 i dc3 i dc4 Amplitude i dc,x Time [sec.] (c) Harmonics order (d) U an [V] Time [sec.] (e) Amplitude U an Harmonics order (f) Figure 6-6 (a, b): DC link voltage ripple and its harmonic spectra in the 9L-CLHB VC, (c, d): dc link current and its harmonic spectra in the 9L-CLHB VC, (e, f): phase output voltage and its harmonic spectra in the 9L-CLHB VC (E = 34J/kVA, C = C = 44mF, f C = 75Hz, f o = 5Hz, m a =.5, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

165 CONVERTER COMPARION 4 5 i C [A] i C [A] Time [sec.] 3 (a) Amplitude i C Harmonics order 4 (b) U am [V] - Amplitude U am Time [sec.] (c) Harmonics order (d) 5 i L,x [A] -5 i La i Lb i Lc Amplitude i L,x Time [sec.] (e) Harmonics order (f) Figure 6-7 (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VC (E = 6J/kVA, C = C =.77mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

166 4 CONVERTER COMPARION 5 i C [A] i C [A] Time [sec.] (a) Amplitude i C Harmonics order (b) 3 4 U am [V] - - Amplitude U am Time [sec.] (c) Harmonics order (d) 5 i L,x [A] -5 i La i Lb i Lc Amplitude i L,x Time [sec.] (e) Harmonics order (f) Figure 6-8 (a, b): Capacitor current ripples and their harmonic spectra in the 3L-NPC VC, (c, d): phase-midpoint output voltage and its harmonic spectra in the 3L-NPC VC, (e, f): phase output load currents and their harmonic spectra in the 3L-NPC VC (E = J/kVA, C = C = 5.54mF, f C = 75Hz, f o = 5Hz, m a =.6, V ll,rms, = 4.6kV, I ph,rms, = 6A, cosφ =.9)

167 7. CONCLUION AND DICUION In this thesis, different multi-level converters (the L-VC, 3L-NPC VC, 3L-, 4L-FLC VCs, CLHB VCs, and C3LHB VCs) have been investigated in terms of the feasibility of their utilization in medium voltage applications. The medium voltage drives in the.4mva to 6.MVA range with voltage ratings from.3kv to 6kV have been studied, applying.7kv,.5kv, 3.3kV, 4.5kV, and 6.5kV IGBT modules. The modelling of the converter has been derived and the principles of operation that include the structure, the design of the power semiconductor devices and passive components, the design of the dc link capacitor, and the function of the multi-pulse isolation transformer have been discussed. To evaluate the converter topologies for a variety of applications, three commercially available MV topologies (i.e. the 3L-NPC VC, FLC VCs, and CLHB VCs) have been compared in detail and the simulation results (regarding the converter losses, the semiconductor loss distribution, the efficiency, the installed switch power, and the harmonic spectrum) have been investigated, assuming a maximum junction temperature of T j, max = 5 C at a phase current of I ph,rms, = 6A and a carrier frequency of f C = 45Hz...5Hz. In the first comparison, a constant carrier frequency f C and a constant installed switch power (which is a measure for the expense of semiconductors) have been examined to compare the maximum converter output power C,max and the semiconductor utilization of the considered converter topologies. The simulation results show that the CLHB VCs provided the maximum converter output power C,max in all investigated line-to-line output voltage classes. The switching losses of the CLHB VC topologies were significantly lower than those of the other topologies in all considered output voltage classes, since the.7kv IGBTs generate distinctly less switching losses than other IGBTs at their corresponding commutation voltage. An output filter of the CLHB VCs could be smaller than the corresponding filters of other topologies due to the first carrier band of the line-to-line output voltage of the 5L-, 7L-, 9L-, and L-CLHB VCs being centred around four, six, eight, and ten times the carrier frequency. The weighted total harmonic distortion WTHD of the L-CLHB VC was significantly lower than that of other topologies due to the eleven-level characteristic of its output voltage. In the second comparison, a constant installed switch power as well as an equal output current (I ph,rms, = 6A) and a constant converter output power C with line-to-line output voltages of.3kv, 3.3kV, and 4.6kV have been assumed to calculate the maximum carrier frequency f C,max of the considered converter topologies. The simulation results illustrate that the CLHB VCs realized a higher maximum carrier frequency than that of all investigated topologies for all the considered line-to-line output voltages. Moreover, the first carrier band f Cb of the line-to-line output voltage of the 5L-, 7L-, and 9L-CLHB VC occurred around 6.34kHz, 7.8kHz, and 7.6kHz at f C = 45Hz, and.khz, 3.5kHz, and 6.6kHz at f C = Hz respectively. Thus, for all considered output voltage classes, the CLHB VCs could enable the smallest sine output filters, compared to other topologies. When comparing the WTHD at the maximum possible carrier frequency, the 9L-CLHB VC featured the minimum value, since the harmonics of the first carrier band (f Cb = 7.6kHz at f C = 45Hz, and f Cb = 6.6kHz at f C = Hz) are strongly damped. The conditions for the third comparison were the constant installed switch power as well as the constant frequency of the first harmonic carrier band f Cb, which enables the design of an

168 44 CONCLUION AND DICUION output filter of about the same size and cost. To place the first harmonic carrier band at the frequency occurring in the 3L-NPC VC (f Cb = f C = 45Hz / Hz), the carrier frequencies of the different topologies have been reduced. The maximum apparent converter output power C,max of the 5L-, 7L-, and 9L-CLHB VCs have been increased by 5%,.5%, and 37% at f C = 45Hz and by 34.3%, 74.3%, and 9.4% at f C = Hz, in comparison to the 3L-NPC VC in the corresponding output voltage classes of.3kv, 3.3kV, and 4.6kV. In comparison to the corresponding 3L-NPC VC topologies, the switching losses of the 5L-, 7L-, and 9L- CLHB VCs were significantly lower due to using the.7kv-igbts (for example, by 76% for.3kv, by 88% for 3.3kV, and by 94% for 4.6kV at f C = 45Hz), while their conduction losses were increased (for example, by 5% for.3kv, by 8% for 3.3kV, and by 7% for 4.6kV at f C = 45Hz). Both the THD and the WTHD of the 9L-CLHB VC were still the smallest, since the distortion of the output voltage was at a minimum due to the applied ninelevels (f C = 45Hz). The conditions for the fourth comparison were a constant converter efficiency of about 99% at a constant converter power of C = 4.3MVA, assuming a line-to-line voltage of 4.6kV for a medium switching frequency of f C = 45Hz in all considered topologies.the efficiency of the 3L-NPC VC at f C = 45Hz was higher and there were thus smaller losses than in the other topologies. The comparison of 6.5kV IGBTs/diodes and a series connection of two 3.3kV IGBTs/diodes per switch position in a (4.6kV, 4.3MVA) 3L-NPC VC and a 3L-FLC VC shows that 3.3kV IGBT modules enable a substantially higher converter switch utilization and efficiency in the examined switching frequency range of f C khz [9]. The application of a series connection of two 3.3kV IGBT/diode increased the installed switch power by.6% at a 77.8% higher switching frequency, compared to the use of 6.5kV IGBTs/diodes. The distribution of conduction and switching losses demonstrates that the series connection of 3.3kV IGBTs enable an almost equal share of switching and on state losses for f C = 5Hz. In contrast, the high share of switching losses of 6.5kV IGBTs cause about two-thirds of the total losses at f C = 45Hz and a reduction of the installed switch power, because these devices are optimized for distinctly lower switching frequencies. A maximum first carrier band frequency of f Cb = 9Hz can be achieved by supposing an installed switch power of =.6MVA. The unsymmetrical loss distribution within the 3L-NPC VC [9], [8], [9], [9] and the additional neutral point clamp diodes are the reason for the 3L-NPC VC requiring the highest installed switch power among the different ML topologies. In comparison to the 3L-NPC VC, the installed switch powers of the FLC VCs are reduced and the maximum first carrier band frequencies of the 3L-FLC VC as well as 4L-FLC VC are increased. However, both of the FLC VCs required a substantial expense of flying capacitors at low and medium switching frequencies. Therefore, the flying capacitor topology is not competitive in applications that require only low and medium switching frequencies (f Cb 5-8Hz) [9]. till, the symmetrical semiconductor loss distribution and the resulting high first carrier band frequency of the converter voltage make this topology attractive for high speed drives or applications with very low current ripple requirements (e.g. test benches) [9]. The 9L-CLHB VC requires a lower installed switch power than the 3L-NPC VC (by 3.5% at f C = 5Hz, applying two series connection of a 3.3kV IGBT/diode). Furthermore, an extremely low share of switching losses and an extraordinary high maximum first carrier band of the line-to-line output voltage of the 9L-CLHB VC (f Cb = 94Hz) can be achieved at a given installed switch power. Hence, an output filter of the 9L-CLHB VC could be smaller than the corresponding filters of other topologies. When taking only the 3L-NPC VC and the CLHB VCs into account, the 5L-, 7L-, and 9L- CLHB VCs generate higher converter losses than the corresponding 3L-NPC VCs in the output voltage classes of.3kv, 3.3kV, and 4.6kV, assuming a constant carrier frequency

169 CONCLUION AND DICUION 45 (45Hz, 75Hz, and 5Hz) and a constant phase current (I ph,rms, = 6A), while the converter losses of the L-CLHB VC are reduced by 8% at f C = 45Hz, 3.% at f C = 75Hz, and 8.9% at f C = 5Hz, compared to the 3L-NPC VCs for a line-to-line output voltage of 6kV. Furthermore, the switching losses of the CLHB topologies are significantly lower (%, 39%, 59%, and 59% at f C = 45Hz) than those of the 3L-NPC VCs in all considered output voltage classes (.3kV, 3.3kV, 4.6kV, and 6kV) and carrier frequencies (45Hz, 75Hz, and 5Hz), whereas the conduction losses of the CLHB VCs are increased in all considered carrier frequencies and output voltage classes (6%, 45%, %, and 7% at f C = 75Hz). Thus, for all examined output voltage classes and carrier frequencies, the CLHB VCs enable a minimum installed switch power, which is decreased, for example, by 8% for.3kv, 38% for 3.3kV, 5% for 4.6kV, and 6% for 6kV at the carrier frequency of f C = 5Hz. In the last section, the dimensioning of the dc link capacitor has been investigated for a 4- pulse, 4,6kV, 4.3MVA, 3L-NPC VC and the 9L-CLHB VC, assuming the dc link voltage ripples of 5% and the dc link capacitor storage energy of 6J/kVA and J/kVA at f C = 75Hz. The simulation results show that the maximum value of the ripple current occurred at modulation index m a =.6 and load angle ϕ =, ±8 for the 3L-NPC VC, and m a =.5 and ϕ = ±9 for the 9L-CLHB VC. It is to remark that the dc link voltage ripple and the dc link current are about.3% and 4.96% for the stored energy of 6J/kVA, while they enable a reduction by 55% and by 47.6% at twice the stored energy for the 3L-NPC VC. Furthermore, the dc link voltage ripple of each H-bridge cell of the 9L-CLHB VC is larger than the acceptable value of 5%, assuming a stored energy of 6-J/kVA. Therefore, in order to place the dc link voltage ripple at a permissible limit, an increase in the dc link capacitor by the factor of.8 and a recalculation of the stored energy of 34J/kVA are necessary, compared to the stored energy of J/kVA. In conclusion, the 3L-NPC VC is a competitive and widely used topology for a large variety of low and medium switching frequency applications (e.g. f C 5Hz) in a voltage range of.3kv V ll 4kV [9]. A simple grid transformer, a small dc link capacitor, and the possible modular realization of common dc bus configurations are attractive additional features of this topology [9]. However, for the more than three-level configuration, the NPC voltage imbalance problem cannot be overcome by utilizing control techniques. Therefore, an increase of the output voltage of the 3L-NPC-VC requires the use of the series connection of commercially available 3.3kV-6.5kV IGBTs or IGCTs or development of new devices with increased blocking voltages (e.g. kv IGCTs) [8]. is makes the NPC unsuccessful in high voltage applications. To synthesize the same number of voltage levels, the CLHB requires the least number of total main components. Another dominant advantage of the CLHB is its circuit layout flexibility. Each level has the same structure and there are no extra clamping diodes or voltage balancing capacitors, which are required in the NPC and the FLC topologies. The number of output voltage levels can then be easily adjusted by changing the number of H-bridge cells. Moreover, redundancy can be easily applied to enhance the reliability of the entire system. The high converter switch utilization, the high maximum carrier frequencies, and the low total harmonic distortions of the converter voltage and current are attractive features of the CLHB VC topology, compared to the 3L- NPC VC which is widely used in MV applications today. The modular topology structure of the CLHB enables a simple extension of the converter voltage range to U ll,rms, > 4kV [9]. However, the high number of semiconductors, a complex and expensive multi-pulse isolation transformer, increased dc link capacitance values and the absence of a common dc voltage bus are disadvantages of this topology [9], [9]. Overall, the CLHB VC is an attractive topology for manifold MVDs, including high speed drives [9].

170

171 APPENDIX A A.. MODULATION METHOD There are different PWM methods which have been extended for the use in H-bridge converters by using multiple carriers. These methods are described in many publications in the technical literature [6-3]. They can be categorized into three groups: Phase hifted (P), which is linked to FLC VC and CHB VCs, Carrier Disposition (CD), which is used for NPC VC, and Hybrid (H) methods. The following subsections describe these methods. I. Phase hifted (P) Method This PWM method uses four carrier signals of the same amplitude and frequency, which are phase shifted by T C /4, where T C is the period of the carrier signal. The modulation method for a 5-level H-Bridge is shown in Figure A-a. II. Carrier Disposition (CD) Methods This carrier disposition can be classified into the following three methods, which are usually applied to the neutral point clamped topology [33], [34]. These methods may not be used naturally for the H-Bridge converter applications. However, an implementation strategy has been suggested to apply PD method to the H-Bridge converter [3], which uses discontinuous PWM reference signals with phase-shifted carriers.. Phase Disposition (PD) Method: This PD method has all carrier waveforms in phase, as shown in Figure A-b. The zero reference is placed in the middle of the carrier sets.. Phase Opposition Disposition (POD) Method: With the POD method the carrier waveforms above or below the zero reference value are in phase. However, they are phase shifted by 8 between the carrier waveforms above and below zero, as shown in Figure A-c. 3. Alternative Phase Opposition Disposition (APOD) Method: All carrier waveforms in this APOD method are phase-displaced by 8 alternatively, as shown in Figure A-d. III. Hybrid (H) method This method is the combination of the P and CD methods [3], [35]. Figure A-e shows a triangular carrier, which is divided into a set of carrier signals. The gate signal of one switch is determined by the comparison of this set of carrier signals and the reference signal. The gate signals for the remaining switches are generated by phase shifting the set of carriers by T C /4 of the carrier set frequency. IV. pace vector method The space vector modulation (VM) is based on the description of symmetrical three-phase systems in the α-ß reference frame. The three-phase reference voltages are represented as a single reference phasor with constant length and angular speed. It substitutes the demanded voltage space vectors by the nearest real voltage space vectors in an appropriate combination in each sampling interval. The basic principles of the VM are shown in Figure A- for threelevel converters, which involves 7 different converter switch states (= number of level) 3.

172 48 APPENDIX A A.. Output Waveforms and pectrum The line-to-line output voltage waveform of the 5L-H-Bridge VC is depicted in Figure A- (ei) for different PWM methods. The spectra of the line-to-line output voltage waveforms are depicted in Figure A-3 at m =. 5 and m = 5 for different PWM methods. a f Compared to the PWM modulation method for an 5L-H-Bridge converter, the CD methods have unbalanced switch utilization, dependent on m a, and the first carrier band of the line-toline voltage centred around in the carrier frequency. In contrast, the P method offers a balanced switch utilization and simple implementation. The first carrier band of the line-to-line voltage for the P and H methods is centred around four times the carrier frequency. Although, the H method has the same switch utilization as the P method, it is the most complex to implement. β Vref α Figure A- pace vector modulation of three-level converters

173 APPENDIX A 49 / - / - / - / - / - / - / - / - / (a) (b) (c) (d) (e) P PD POD APOD Figure A- Different PWM methods and their line-to-line output voltage waveforms of the 5L-H- Bridge VC / - - H - H P PD POD APOD (e) (f) (g) (h) (i)

174 5 APPENDIX A - ( U ) U ab dc h (a) m f = 5, m a =.5 P ( U ) U ab dc h (b) m f = 5, m a =.5 PD Harmonic Magnitude (p.u.) ( U ) U ab dc ( U ) U ab dc h h (c) m f = 5, m a =.5 (d) m f = 5, m a =.5 POD APOD - - ( U ) U ab dc h (e) m f = 5, m a =.5 H -.5 m f m f 3m f 4m f Harmonic Order Figure A-3 Harmonic spectra of the line-to-line output voltage for the 5L-H-Bridge VC

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