Application Note AN-11001

Transcription

1 Application ote A-00 Revision: Issue Date: repared by: Ingo Staudt Key Words: 3L, C, TC, C, MC, Multilevel, Loss Calculation, SemiSel 3L C & TC Topology General... Difference L 3L... Switching pattern of a 3L converter... 3 Commutations and commutation paths L converter... 6 Module consideration... 6 Setup with standard L modules... 6 Dedicated 3L modules... 7 SEMIKRO 3L modules... 7 Driving 3L devices... 7 ormal operation sequences... 7 Emergency shut-down... 8 rotection of 3L devices against voltage overshoots... 8 Snubber... 8 Active Clamping L loss calculation... 9 SemiSel... Symbols and Terms used... References... This application note provides information on two three level topologies: the three level C (3L C; eutral oint Clamped and the three level TC (3L TC; T-type eutral oint Clamped. The reader will gain insight in elementary thoughts of how these 3L devices work; where advantages and disadvantages are. Some hints concerning the layout/setup of 3L modules are given as well. However, the information given is not exhaustive and the responsibility for a proper design remains with the user. General One benefit of using 3L C or 3L TC topology is the lower current THD; that reduces the filtering effort (less copper needed, lower losses in the filter. A major advantage of 3L C is the possibility to use IGBTs and diodes with breakdown voltages that are lower than the actual link voltage. The lower blocking devices produce lower losses and so the efficiency can be increased. By using the same blocking voltage as in a L applications higher link voltages can be realized. Compared to a L phase leg module one phase leg of a 3L C module consists of 0 instead of 4 semiuctors (Fig. : 4 IGBTs ( -, 4 antiparallel Free-Wheeling Diodes (FWD; - and Clamping Diodes (CD; and. by SEMIKRO Rev04 /

2 Application ote A-00 Fig. : Green box: content of a 3L C phase leg C link voltage. The inner itches (indices and 3 connect to eutral and must be able to block half of the link voltage. In 3L TC topology the uction paths are either through one higher blocking semiuctors (outer itch or two lower blocking devices in series (inner itches. aming the semiuctors as shown in Fig. and Fig. inherits the advantage that the exact same itching pattern can be used for both 3L C and 3L TC topology. Difference L 3L C Four power terminals connect the module to and to the link:, and (neutral. The link is split in two symmetric halves connected in series; the upper half connecting and and the lower half connecting and. In this 3L topology every uction path consists of two semiuctors in series and it can either handle higher link voltages or the blocking voltage of the itches can be reduced in comparison to a L topology. The difference between L and 3L topology is not only the number of semiuctor devices. While the wellknown L converter itches either or to the terminal (Fig. 3, the 3L versions connect the either to, or. (eutral is the midpoint voltage between and and forms the third voltage level where the three level topology has its name from. Fig. 3: oltage and current waveforms of L - -DC DC 0 Output voltage (line to line Output current Fig. : Green box: content of a 3L TC phase leg Fig. 4: oltage and current waveforms of 3L C - -DC DC 0 Output voltage (line to line Output current C The benefit of 3L TC is the 3L output voltage waveform while there are no restrictions to the itching scheme as in 3L C (especially in emergency shutdown. A 3L TC phase leg (Fig. consists of only 8 semiuctors: 4 IGBTs ( - and 4 antiparallel Free-Wheeling Diodes (FWD; -. As a 3L C the TC is connected to the split link at, and. The fourth power terminal provides the output. In 3L TC topology semiuctors with different breakdown voltages are used: and (which are ered to as outer itches need to withstand the full By introducing a third voltage level the waveform of the output voltage is approximated closer to the desired sine waveform (Fig. 4 and the current THD can be reduced. Thus strong requirements concerning grid quality (when feeding to the grid can be met more easily. Comparison of L 3L C/TC: C & TC: For reaching the same current THD value with 3L topology the itching frequency can be / Rev04 by SEMIKRO

3 Application ote A-00 C: TC: reduced leading to reduced itching power losses. Subsequently operation at a working point producing the same itching frequency as in L topology the current THD can be reduced in 3L topology. In 3L applications the itching frequency can be reduced compared to L applications, still improving the THD and reducing the filtering effort. As the number of IGBTs has increased from to 4 also the number of gate drivers increases. The auxiliary power consumption grows as well as the control effort. The number of itches in the active current path in 3L C topology is doubled; that increases the uction power losses. In 3L C applications semiuctors with a lower blocking voltage capability may be used; example: link voltage of 750 can be handled with 00 L or 650 3L modules (each itch only needs to block 375. The lower losses of the lower blocking devices compensate the additional losses due to the increased number of devices in the current path. The maximum link voltages are 800 DC using 650 semiuctors, 500 DC using 00 semiuctors and 400 DC using 700 semiuctors. The number of itches in the active current path in 3L TC topology is either similar to L (outer itches producing the same losses or doubled (with lower blocking voltage; inner itches leading to higher uction but lower itching losses. The maximum link voltages are as for a L module: 400 DC using 650 semiuctors, 800 DC using 00 semiuctors and 00 DC using 700 semiuctors. Switching pattern of a 3L converter The control of 3L applications is more sophisticated than L. While the L itching pattern is pretty simple (TO and BOT IGBTs always itch inversely it gets more complicated at 3L as certain itches (namely and are itched on for quite a while depending on the value of cos (up to a half period for cos =. The number of possible itching states increases from 4 in L topology (TO/BOT: 0/0, 0/, /0, / to 6. At 3L C a distinction is drawn between allowed, potentially destructive and destructive states (Fig. 5. Fig. 5: Switching states C state allowed potentially destructive destructive Allowed states: All IGBTs are in off-state; the converter is itched off. Either or may be itched on solely. Each state where two adjacent IGBTs are itched on (/, /, /. otentially destructive states: Either or is itched on solely or together. Two not adjacent IGBTs are itched on (/ or /. The consequences depend on the itching pattern applied to the modules of the other phase legs. Destructive states: Three adjacent IGBTs are itched on (// shorting upper half of link; // shorting lower half of link Three not adjacent IGBTs are itched on (// full link voltage applies to ; // full link voltage applies to Four IGBTs itched on, and shorted. At 3L TC the distinction is drawn only between allowed and destructive states (Fig. 6. Fig. 6: Switching states TC state allowed destructive Allowed states: All IGBTs are in off-state; the converter is itched off. Any one of the IGBTs may be itched on solely. Each state where two adjacent IGBTs are itched on (/, / or /. Destructive states: Two not adjacent IGBTs are itched on (/ shorting upper half of link; / shorting lower half of link; / shorting and. by SEMIKRO Rev04 3 /

4 Application ote A-00 Three not adjacent IGBTs are itched on (same consequences as above: shorting either upper half or lower half or the full link Four IGBTs itched on, and shorted. 4. voltage is greater and current is less than 0 ( > 0, : L: T BOT D TO 3L C: / / (long commutation path 3L TC: / Commutations and commutation paths C & TC: Fig. 7 shows a sine voltage (blue trace and the related current (red trace at inductive load. The inverter operation can be divided in four operating areas. For cos = + (no phase shift voltage and current waveforms are in phase; only working areas and 3 are active. For cos - (80 phase shift only working areas and 4 are active. Fig. 7: Operating areas C: While in a short commutation path the commutation affects only one of the two active itches (e.g. the current through the other active itch does not change (e.g.. In a long commutation path (e.g. / / both devices are affected. The name short/long commutation path also indicates the geometric length of the commutations; while the short commutation takes place either within the upper or the lower half of the 3L module in a long commutation the current changes from the upper to the lower half (or vice versa. 0.9 Fig. 8: Short commutation path in operating area. oltage Current I i( t u( t < 0 < 0 I I t For any value of cos between - and + the phase shift changes and so do the time shares of the four working areas. The active itches and the commutations for these four working areas are listed below:. both voltage and current are greater than 0 ( > 0, : L: T TO D BOT 3L C: / / (short commutation path 3L TC:. voltage is less and current is greater than 0 ( < 0, : L: T TO D BOT 3L C: / / (long commutation path 3L TC: / 3. both voltage and current are less than 0 ( < 0, I < 0: L: T BOT D TO 3L C: / / (short commutation path 3L TC: / 3 The short commutation (Fig. 8 in the upper half of the module (device indices, and 5 is active in operating area (Fig. 9; both voltage and current are positive. The commutation goes back and forth between and ; the current flows from via and to the terminal as long as is itched on. When itches off, the current commutates to the clamping diode ; now the current flow is from via and to. stays itched on all the time. Fig. 9: Operating area 0.9 oltage Current I i U( ( tx I ( x u ( t < 0 3 The long commutation for positive output current (Fig. 0 goes back and forth between / in the upper half of the module and / in the lower half => across the entire device. 4 / Rev04 by SEMIKRO

5 Application ote A-00 Fig. 0: Long commutation path in operating area Fig. 3: Operating area 3 I. This commutation across the entire device is due to the fact that in operating area (Fig. the current is still positive (flowing from the link towards the load while the output voltage is negative. Fig. : Operating area 0.9 i ( t u ( t 0.9 I oltage Current I t 0 x < 0 The long commutation path for negative current (Fig. 4 goes back and forth between / in the lower half of the module and / in the upper half across the entire device. Fig. 4: Long commutation path in operating area 4 4. oltage Current I U I ( x ( x < 0 < 0 I I t 3 The other short commutation path is active in operating area 3 (Fig. & Fig. 3, in the lower half of the module. Output current and voltage are negative. Fig. : Short commutation path in operating area 3 The long commutation in operating area 4 (Fig. 4 comes with negative output current (flowing from the terminal towards the link and positive voltage. Fig. 5: Operating area 4 I 3. I 0.9 oltage Current I i ( t u ( t < 0 3 x 0 The commutation goes back and forth between and ; the current flows from the terminal across and to as long as is itched on. As soon as itches off, the current commutates to the clamping diode ; the new uction path is from vie and to. stays itched on all the time. TC: There are no short or long commutation paths in TC topology; all paths are of the same geometric length and inherit one outer itch (indices or 4; either IGBT or diode and two inner itches (either and or and. In normal operation the commutation always affects one outer and two inner itches; there is no commutation between / and / except when an emergency shut-down happens. In operating area (Fig. 6 & Fig. 9 output voltage and current are positive, the current flows towards the terminal. The commutation goes back and forth between and /; the current flows from via to the by SEMIKRO Rev04 5 /

6 Application ote A-00 terminal as long as is itched on. When itches off, the current commutates to the inner itches /; the current now flows from via and to. stays itched on all the time; as soon as is itched on, the diode blocks the voltage and so avoids a short cut of the upper half of the link. In operating area 4 (Fig. 9 the output current is negative while the voltage is positive (Fig. 5. The current commutates back and forth between the inner itches / and the diode. Fig. 9: Commutation path in operating area 4 Fig. 6: Commutation path in operating area 4.. I I I I In operating area (Fig. 7 the output current is still positive while the voltage is negative (Fig.. It commutates back and forth between the inner itches / and the diode. Fig. 7: Commutation path in operating area I. Fig. 8 shows the uction paths of operating area 3; the current commutates between and the inner itches /. The current flows from the terminal to the link and, current and voltage are negative (see Fig. 3. stays itched on permanently; as long as is itched on as well the diode blocks the voltage and avoids shorting the negative half of the link. I 3L converter Module consideration When a 3L module is designed especially the commutation paths find consideration: large commutation paths inherit large stray inductances. When the load current through a uction path with large stray inductance is itched off high voltage overshoots occur. To avoid a destruction of the semiuctor the voltage overshoot must stay below its blocking voltage. That can be reached by either reducing the maximum allowed DClink voltage and allowing higher overshoots or by reducing the stray inductances producing less overshoots. Of course the aim is to reduce the stray inductance and allow higher link voltages (that increases the possible output voltage and so the module power. Setup with standard L modules Theoretically 3L topologies can be set up with already existing standard L modules (Fig. 0 & Fig.. The assembly would require bus bar interconnection of the modules and would be very scalable. Fig. 8: Commutation path in operating area 3 3. I I C: ractically the C setup from L modules (Fig. 0 inherits always very long uction paths, especially for the commutations across module borders (that gets even worse for the long commutation paths. Due to the stray inductance these large commutation paths produce very high voltage overshoots so that the shown setups offer no advantages in regard to L designs. 6 / Rev04 by SEMIKRO

7 Application ote A-00 Fig. 0: L configurations to set up a 3L C module R GB GB GB L GB SEMIKRO 3L modules SEMIKRO provides a number of 3L modules that have been specially redesigned to minimize stray inductance. The module range starts with SEMITO at a rated chip current of 0A to 50A followed by MiniSKii (75A - 00A up to SKiM modules with 00A - 600A rated current. While SEMITO and MiniSKii are available for link voltages of up to approx. 800, SKiM modules allow for up to 500. The output power range goes as far as 50kA (Fig.. As soon as even higher power is required several modules need to be connected in parallel. Fig. : SEMIKRO 3L module portfolio SEMITO 3 & 4 In the TC setup from L modules (Fig. every commutation path is across module borders. Similar to the C setup stray inductances lead to high voltage overshoots which make this solution unattractive. TC: 0 A 50A MiniSKii & 3 75A 00A Fig. : L configurations to set up a 3L TC module SKiM 4 00A 600A [ka] GM GB The major benefit of the 00 C module is that a maximum output voltage of 000 can be realised at 500 link. So it is possible to stay right within the low voltage directive (harmonised standards apply on the one hand and reduce the converter current on the other without a change to the output power. Dedicated 3L modules As the 3L topology setup from L modules appears not to be the best solution a new module design has been made facing the special requirements coming with the 3L technology. At the very beginning a choice must be made concerning the module size and the related electric module power: the bigger the module shall become the more power it can provide as large chip area is available. Unfortunately larger module size also stands for higher stray inductances leading to high itching voltage overshoots thus limiting the maximum current. High power can either be realized by one large module or by many smaller modules in parallel. The latter solution requires an equally high number of driving units that need to be parallelized (with known problems: cost, space, jitter of separate drivers, compensation current when using paralleled drivers. Driving 3L devices ormal operation sequences C: When all devices are itched off and the C converter starts operation it must be one of the inner IGBTs to be itched on first. In case of positive output voltage that is. After a short while (when is entirely itched on may be pulsed. For the itch-off sequence the reverse order must be maintained: it must be made sure that is thoroughly itched off before may be turned off. That can be achieved by turning off a short time (..3µs after the turn-off signal for has occurred; this dead time is well known as interlock-time between TO and BOT itch at SEMIKRO L gate drivers. by SEMIKRO Rev04 7 /

8 Application ote A-00 When an inner IGBT ( or is itched off before the corresponding outer IGBT ( or the inner itch would be exposed to the full link voltage. In case this voltage was higher than the blocking voltage of that semiuctor it would be destroyed. As shown in Fig. 4 there are itching patterns that are not allowed because they are destructive. Those states must be avoided if the device shall not be destroyed. TC: There is no mandatory itching sequence for the TC converter: any IGBT may be itched on and off at any time because there is no danger that one semiuctor is exposed to a voltage higher than its blocking voltage. C & TC: The gate signals of and ( and respectively are invers. It has to be made sure that one IGBT is securely itched off before the other one is itched on. Emergency shut-down There are several events that may occur which in L application lead to immediate itch-off by the driver to protect the semiuctors. Imaginable events are: - thermal overload - current overload or - desaturation. Any of these scenarios must lead to a quick shut-down in 3L application as well. C: But it must be made sure that the correct itch-off sequence is maintained: outer IGBT first ( or, inner IGBT afterwards ( or to avoid destruction due to voltage breakdown. Where thermal overload or a slowly rising current can be monitored with TC/TC and current sensors and leave some time for the supervising controller to react in an appropriate time, a desaturation event leaves a maximum of 0µs time for itch-off. When an outer itch ( or desaturates it may be itched off immediately by the driver. After..3µs the according inner IGBT is to be itched off as well. It gets more complicated, when the desaturation happens at an inner itch ( or : when the event is monitored the driver must have the information if an according outer itch is itched on as well or not. If it is itched on the gate driver must itch off the outer IGBT immediately, wait..3µs and then itch off the inner IGBT as well. If no outer IGBT is itched on the driver must itch off the inner IGBT immediately. In any case the driver generates an error message so that the controller can shut down the other devices of the converter as well and so establish a secure state. TC: Again it is much easier in TC topology because no itch-off sequence must be maintained. o matter if thermal or current overload or a desaturation event happens, the converter may be itched off immediately. rotection of 3L devices against voltage overshoots As soon as a current path is interrupted (by itching off an IGBT or a diode the voltage across the itched off device begins to rise. This voltage overshoot is caused by the energy stored as magnetic field of the current path. The energy increases linearly with rising stray inductance L S (E = 0.5*L S*i²; e.g. doubled parasitic inductance L S causes doubled energy E. The voltage overshoot ( = L S*di/dt is added to the link voltage; the sum must not exceed the blocking voltage of the semiuctor as it would be destroyed. Due to the fact that a 3L module is larger than a L device and a uction path inherits two itches the current paths are longer and hence the stray inductances higher. Especially the long commutation paths (C topology; / / or / / must be payed attention to when the module is designed. While with a good design low values of the stray inductances can be realised (e.g. SKiM4 MLI: 8nH per itch, approx. 60nH for the long commutation path it is not possible to construct a low inductive 3L setup with standard L modules. The long commutation path passes at least three modules in C topology (see Fig. 0 or two ot three modules in TC topology (Fig. what leads to a stray inductance of about 00nH. That is more than three times as much as in the dedicated 3L module. Assuming the di/dt is the same this setup produces more than three times as much voltage overshoot. For that reason SEMIKRO recommends the use of dedicated 3L modules. If there are no further possibilities to reduce the voltage overshoot at its root cause (i.e. even shorter connections between the semiuctors which at a certain point is not possible any more the overshoot needs to be handled in a way protecting the semiuctors. Snubber Snubber capacitors can be connected to and respectively and. They must be positioned as close to the module as possible and can be chosen according to the hints given in SEMIKRO Application ote A Active Clamping Another way to handle harmful voltages is to use an active clamping network at the IGBTs (Fig / Rev04 by SEMIKRO

9 Application ote A-00 This network consists of several in series connected transient voltage suppressor (TS diodes providing a breakdown voltage which is slightly below the IGBT s breakdown voltage. The clamping network is connected between collector and gate of the device that shall be protected. When the itch is turned off and the voltage across increases above the breakdown voltage of the TS diodes they start ucting a current into the gate of the IGBT. The IGBT starts ucting as well; that leads to a voltage breakdown across the device as soon as the energy stored as magnetic field is exhausted, the TS diodes go into blocking mode again and the IGBT itches off. Fig. 3: Simple active clamping circuit Gate driver TS 3L loss calculation For choosing a 3L module that is best suited for a certain application it is necessary to calculate the power losses that emerge in the different semiuctors. Subsequently the equations for calculating the power losses in 3L C and 3L TC are shown. C: The power losses of the 0 semiuctors in 3L C topology can be calculated according to: & : M 3 cos( sin( r cos( ce0 ce K cos( GI f E I & : 3M cos( sin( r 3 M cos( ce0 ce K cos( GI f E I & : ˆ 3M cos( sin( r I 3 4M cos ( f 0 f K cos( GI f E I by SEMIKRO Rev04 9 /

10 Application ote A-00 & : M 3 cos( sin( r cos( f 0 f K cos( GI f E I & : M 0 3 cos( sin( r cos( f 0 f TC: The power losses of the eight semiuctors in 3L TC topology are different from those of 3L C and can be calculated as follows: & : M 3 cos( sin( r cos( ce0 ce K cos( GI f E I & : ˆ 6M cos( sin( 3M cos( r I 3 4M cos ( ce0 ce K cos( GI f E I & : ˆ 3M cos( sin( 3M cos( r I 3 4M cos ( f 0 ce K cos( GI f E I & : M 3 cos( sin( r cos( f 0 f K cos( GI f E I 0 / Rev04 by SEMIKRO

11 Application ote A-00 C & TC: The equations are valid for M = 0. The modulation index M correlates link voltage and RMS voltage: M 3 RMS DC Typical values of K, and G I for SEMIKRO modules are shown in Fig. 6. Fig. 6: Typ. K, and G I values for SEMIKRO modules IGBT Diode K G I.5 SemiSel SemiSel is SEMIKRO s online simulation tool to calculate losses and temperatures of power semiuctors in customer specific applications. From specific values for cooling (e.g. type and performance of the heatsink, ambient temperature and electric parameters (e.g. input/output voltage, itching frequency, load current, etc. SemiSel calculates the power losses and junction temperatures of all IGBTs and diodes within a few ses. By changing certain parameters the optimum setup (which type of module, itching frequency, can easily be found. SemiSel 4.0 has been extended to calculate the 3L C topology in the same convenient way as L designs. Symbols and Terms used Letter Symbol Term L Two level 3L Three level CD Clamping Diode cos ower factor CS Collector Sense of IGBT ositive potential (terminal of a direct voltage source egative potential (terminal of a direct voltage source di/dt Rate of rise and fall of current E Electrical energy E SW f SW FWD L R GB G I GM i Î I C,OM IGBT I peak I I RMS K L S M C TC Sum of energy dissipation during turn-on and turn-off-time Switching frequency Free Wheeling Diode Single Switch Chopper, low IGBT Chopper, high IGBT Half-bridge Adaptation factor for the non-linear semiuctor characteristics Half-bridge with anti-serial itches (IGBT and antiparallel diode Time dependant value of current eak value of current ominal collector current Insulated Gate Bipolar Transistor eak value of current Reference current value of the itching loss measurement terminal current Conduction angle Exponent for the current dependency of itching losses Exponent for the voltage dependency of itching losses arasitic inductance / stray inductance Modulation index eutral potential (terminal of a direct voltage source; midpoint between and eutral oint Clamped Temperature sensor with negative temperature coefficient by SEMIKRO Rev04 /

12 Application ote A-00 SW TC Q r CE r f RMS R th S t THD T j TC TS CE ce0 f0 CEsat DC RMS Active power Conduction power losses Switching power losses Temperature sensor with positive temperature coefficient Reactive power On-state slope resistance (IGBT On-state slope resistance (diode Root Mean Square Thermal resistance Apparent power Time Total Harmonic Distortion Junction temperature T-type eutral oint Clamped Transient voltage suppressor diode oltage Collector-emitter supply voltage Collector-emitter voltage Forward threshold voltage (IGBT Collector-emitter threshold voltage (diode Collector-emitter saturation voltage Total supply voltage ( to Reference voltage value of the itching loss measurement terminal voltage References [] [] A. Wintrich, U. icolai, W. Tursky, T. Reimann, Application Manual ower Semiuctors, ISLE erlag 0, ISB [3] J. Lamp, "IGBT eak oltage Measurement and Snubber Capacitor Specification", Application ote A-7006, SEMIKRO [4] I. Staudt et al, umerical loss calculation and simulation tool for 3L C converter design, CIM uremberg, 0 [5] M. Sprenger et al, Characterization of a new.k IGBT 3L-C phase-leg module for low voltage applications, EE 0 DISCLAIMER SEMIKRO reserves the right to make changes without further notice herein to improve reliability, function or design. Information furnished in this document is believed to be accurate and reliable. However, no representation or warranty is given and no liability is assumed with respect to the accuracy or use of such information. SEMIKRO does not assume any liability arising out of the application or use of any product or circuit described herein. Furthermore, this technical information may not be considered as an assurance of component characteristics. o warranty or guarantee expressed or implied is made regarding delivery, performance or suitability. This document supersedes and replaces all information previously supplied and may be superseded by updates without further notice. SEMIKRO products are not authorized for use in life support appliances and systems without the express written approval by SEMIKRO. SEMIKRO ITERATIOAL GmbH.O. Box ürnberg Deutschland Tel: Fax: [email protected] / Rev04 by SEMIKRO