AN Designing RC snubbers
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1 AN60 Rev. 25 April 202 Application note Document information Info Keywords Abstract Content RC snubber, commutation, reverse recovery, leakage inductance, parasitic capacitance, RLC circuit and damping, MOSFET This document describes the design of a simple RC snubber circuit
2 AN60 Revision history Rev Date Description v initial version Contact information For more information, please visit: For sales office addresses, please send an to: AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
3 AN60. Introduction 2. Test circuit This document describes the design of a simple RC snubber circuit. The snubber is used to suppress high-frequency oscillations associated with reverse recovery effects in power semiconductor applications The basic circuit is a half-bridge and shown in Figure. V DD HS driver Q inductor V CC LS driver Q2 0V aaa Fig. The half-bridge circuit Q and Q2 are BUK76R6-40E devices. The inductor could also be connected to 0 V rather than V DD. Inductor current is established in the red loop; Q2 is off and current is flowing through Q body diode. When Q2 is turned on, current commutates to the blue loop and the reverse recovery effect occurs in Q. We observe the effect of Q reverse recovery on the V DS waveform of Q2; see Figure 2. AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
4 AN60 Q2 V DS (5V/div) oscillation frequency 3.25 MHz aaa Fig 2. Reverse recovery-induced oscillation in Q2 V DS The equivalent circuit is shown in Figure 3. stray inductance (LLK) Q Coss (CLK) VDD Q2 Q2 VDS aaa Fig 3. Equivalent circuit We are primarily interested in the parasitic elements in the circuit: L LK is the total stray or leakage inductance comprised of PCB trace inductance, device package inductance, etc. The parasitic capacitance is mainly due to C oss of the upper (Q) device. Q2 is treated as a simple switch. The oscillation can be eliminated (snubbed) by placing an RC circuit across Q drain-source; see Figure 4 AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
5 AN60 stray inductance (LLK) Q Coss (CLK) RS CS VDD Q2 Q2 VDS aaa Fig 4. Equivalent circuit with snubber components R S and C S 3. Determining and L LK Before we can design the snubber, we must first determine and L LK. We could attempt to measure and L LK directly, but a more elegant method can be used. For this LC circuit, we know that: f RING π L LK () where f RING0 is the frequency of oscillation without a snubber in place; see Figure 2. If we add an etra additional capacitor across Q (C add ), the initial oscillation frequency from f RING0 to f RING (f RING < f RING0 ) will change. It can be shown that (see Section 7 Appendi A; determining from C add, f RING0 and f RING ): C add (2) where: f RING0 f RING (3) So if we measure f RING0 (without C add ), then add a known C add and measure f RING, we can determine and L LK (two equations, two unknowns). C add 3200 pf was added in circuit, and f RING found to be 22.2 MHz (f RING0 previously found to be 3.25 MHz; see Figure 2). from Equation 3: (4) and from Equation 2: 3200pF pF.4 2 (5) AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
6 AN60 Rearranging Equation : L LK ( 2πf RING0 ) 2 (6) So with f RING MHz and 3239 pf: L LK H 8.0nH ( 2 π ) (7) and with f RING 22.2 MHz and ( + C add ) 3239 pf pf 6439 pf: L LK H 8.0nH ( 2 π ) (8) In other words, the calculated value of L LK remains almost unchanged when we add the additional 3200 pf capacitance. This is a good sanity check of the method for determining and L LK. 4. Designing the snubber - theory If we replace C S in Figure 4 with a short-circuit, then we simply have the classic RLC circuit found in tet books. The response of this circuit to a step change in voltage (that is Q2 turning on) depends on the degree of damping (ζ or zeta) in the circuit; see Figure aaa () (2) (3) (4) (5) (6) (7) (ϖ) () ζ 0. (2) ζ 0.. (3) ζ 0.2. (4) ζ 0.4. (5) ζ 0.7. (6) ζ. (7) ζ 2. Fig 5. Step response of an RLC circuit for various values of zeta (ζ) AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
7 AN60 In theory the circuit oscillates indefinitely if ζ zero, although this is a practical impossibility as there is always some resistance in a real circuit. As ζ increases towards one, the oscillation becomes more damped that is, tends to decrease over time with an eponential decay envelope. This is an underdamped response. The case ζ one is known as critically damped and is the point at which oscillation just ceases. For values of greater than one (overdamped), the response of the circuit becomes more sluggish with the waveform taking longer to reach its final value. There is therefore more than one possible degree of damping which we could build into a snubber, and choice of damping is therefore part of the snubber design process. For this configuration of RLC circuit, the relationship between ζ, R S, L LK and is: ς R S L LK (9) The snubber capacitor C S does not appear in Equation 9. In some circuits, it is possible to damp the oscillations with R S alone. However, in typical half-bridge circuits we cannot have a resistor mounted directly across Q drain source. If we did, then Q is permanently shorted by the resistor and the circuit as a whole would not function as required. The solution is therefore to put C S in series with R S, with the value of C S chosen so as not to interfere with normal operation. The snubber is a straightforward RC circuit whose cut-off frequency f C is: F C πR S C S (0) Again, we must choose which value of f C to be used, and there is no single correct answer to this question. The cut-off frequency of the snubber must be low enough to effectively short-circuit the undamped oscillation frequency f RING0, but not so low as to present a significant conduction path at the operating frequency of the circuit (for eample 00 khz or whatever). A good starting point has been found to be f C f RING0. 5. Designing the snubber - in practice We now have sufficient information to design a snubber for the waveform shown in Figure 2. To recap: 3239 pf L LK 8.0 nh f RING MHz ς R S L LK () F C f 2πR S C RING0 S (2) The first task is to choose a value of damping (Figure 5). We have chosen ζ, that is, critical damping. Rearranging Equation we have: AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
8 AN60 L LK R S ζ Ω 9 (3) use 2.5 Ω in parallel to give 0.75 Ω. Rearranging Equation 2 we have: C S nF 2πR S f RING0 2 π (4) use 4.7 nf nf to give 6.9 nf. The snubber was fitted across Q drain source. The resulting waveform is shown in Figure 6 together with the original (non-snubbed) waveform from Figure 2 aaa aaa a. Without snubber b. With snubber Fig 6. Vertical scale is 2 V/div. Q2 V DS waveform with and without snubber As seen in Figure 6, the snubber has almost eliminated the ringing in the V DS waveform. This technique could also be applied to the MOSFET in the Q2 position. 6. Summary Reverse recovery effects in power devices can induce high frequency oscillations in devices connected to them. A common technique for suppressing the oscillations is the use of an RC snubber. Design of an effective snubber requires the etraction of the circuit parasitic capacitance and inductance. A method has been demonstrated for doing this. The snubbed circuit has been shown to be a variation on the classic RLC circuit. AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
9 AN60 A method of determining values of snubber components has been demonstrated. The method has been shown to work well, using the eample of BUK76R6-40E MOSFETs 7. Appendi A; determining from C add, f RING0 and f RING We know that: f RING π L LK (5) where f RING0 is the frequency of oscillation without a snubber in place and L LK and are the parasitic inductances and capacitances respectively. If we add capacitor C add across Q drain-source, f RING0 is reduced by an amount where: f RING0 therefore π L LK ( + C add ) (6) π L LK π L LK ( + C add ) (7) L LK L LK ( + C add ) (8) L L LK ( + C add ) LK C + C add LK X 2 2 C add ( 2 ) C add (9) (20) (2) (22) C add (23) where: f RING f RING (24) AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
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AN60 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Application note Rev. 25 April of
11 AN60 9. Contents Introduction Test circuit Determining and L LK Designing the snubber - theory Designing the snubber - in practice Summary Appendi A; determining from C add, f RING0 and f RING Legal information Definitions Disclaimers Trademarks Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: [email protected] Date of release: 25 April 202 Document identifier: AN60
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The 74LVC1G04 provides one inverting buffer.
Rev. 12 6 ugust 2012 Product data sheet 1. General description The provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in
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CAN bus ESD protection diode
Rev. 04 15 February 2008 Product data sheet 1. Product profile 1.1 General description in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package designed to protect two automotive Controller
Output Filter Design for EMI Rejection of the AAT5101 Class D Audio Amplifier
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XSON1 Rev. 1 26 January 215 Product data sheet 1. Product profile 1.1 General description The device is designed to protect high-speed interfaces such as SuperSpeed USB 3.1 at 1 Gbps, High-Definition Multimedia
UM10689. SSL2109ADB1121 4-channel DC-to-DC LED driver demo board. Document information
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MOSFET N-channel enhancement switching transistor IMPORTANT NOTICE. http://www.philips.semiconductors.com use http://www.nxp.com
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ESD protection for high-speed interfaces
Rev. 1 1 October 212 Product data sheet 1. Product profile 1.1 General description The device is designed to protect high-speed interfaces such as High-Definition Multimedia Interface (HDMI), DisplayPort,
8-bit synchronous binary down counter
Rev. 5 21 April 2016 Product data sheet 1. General description The is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its
74HC573; 74HCT573. 1. General description. 2. Features and benefits. Octal D-type transparent latch; 3-state
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74HC4067; 74HCT4067. 16-channel analog multiplexer/demultiplexer
Rev. 6 22 May 2015 Product data sheet 1. General description The is a single-pole 16-throw analog switch (SP16T) suitable for use in analog or digital 16:1 multiplexer/demultiplexer applications. The switch
74HC32; 74HCT32. 1. General description. 2. Features and benefits. Quad 2-input OR gate
Rev. 5 4 September 202 Product data sheet. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages
Hex buffer with open-drain outputs
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Buffer with open-drain output. The 74LVC1G07 provides the non-inverting buffer.
Rev. 11 29 June 2012 Product data sheet 1. General description The provides the non-inverting buffer. The output of this device is an open drain and can be connected to other open-drain outputs to implement
NPN wideband silicon germanium RF transistor
Rev. 1 29 April 211 Product data sheet 1. Product profile 1.1 General description NPN silicon germanium microwave transistor for high speed, low noise applications in a plastic, 4-pin dual-emitter SOT343F
N-channel TrenchMOS logic level FET
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General purpose low power phase control General purpose low power switching Solid-state relay. Symbol Parameter Conditions Min Typ Max Unit V DRM
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AN10441. Level shifting techniques in I 2 C-bus design. Document information
Rev. 01 18 June 2007 Application note Document information Info Keywords Abstract Content I2C-bus, level shifting Logic level shifting may be required when interfacing legacy devices with newer devices
AN11014. BGX7100 evaluation board application note. Document information
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60 V, 360 ma N-channel Trench MOSFET. Symbol Parameter Conditions Min Typ Max Unit V DS drain-source T amb = 25 C - - 60 V
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TPN4R712MD TPN4R712MD. 1. Applications. 2. Features. 3. Packaging and Internal Circuit. 2014-12 2015-04-21 Rev.4.0. Silicon P-Channel MOS (U-MOS )
MOSFETs Silicon P-Channel MOS (U-MOS) TPN4R712MD TPN4R712MD 1. Applications Lithium-Ion Secondary Batteries Power Management Switches 2. Features (1) Low drain-source on-resistance: R DS(ON) = 3.8 mω (typ.)
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Rev. 8 29 November 2012 Product data sheet 1. General description The provides the single D-type flip-flop with 3-state output. The flip-flop will store the state of data input (D) that meet the set-up
74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications
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PRTR5V0U2F; PRTR5V0U2K
Rev. 02 19 February 2009 Product data sheet 1. Product profile 1.1 General description Ultra low capacitance double rail-to-rail ElectroStatic Discharge (ESD) protection devices in leadless ultra small
74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset
Rev. 9 19 January 2015 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
74HC4066; 74HCT4066. Quad single-pole single-throw analog switch
Rev. 8 3 December 2015 Product data sheet 1. General description The is a quad single pole, single throw analog switch. Each switch features two input/output terminals (ny and nz) and an active HIGH enable
APN1001: Circuit Models for Plastic Packaged Microwave Diodes
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Power MOSFET. IRF510PbF SiHF510-E3 IRF510 SiHF510. PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 100 V Gate-Source Voltage V GS ± 20
Power MOSFET PRODUCT SUMMARY (V) 100 R DS(on) () = 0.54 Q g max. (nc) 8.3 Q gs (nc) 2.3 Q gd (nc) 3.8 Configuration Single D TO220AB G FEATURES Dynamic dv/dt rating Available Repetitive avalanche rated
