Panel Level Embedded Technology

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1 System in a Package Global Summit 2013 Panel Level Embedded Technology Dr. Dyi-Chung Hu Sr. VP. Unimicron

2 Outline Introduction to panel level embedded technology Panel level embedded technology Line embedded Passive components embedded Active devices embedded Many components Embedded Summary and conclusions

3 Mobile Device Everywhere Everyone has mobile device(smart phone or tablet) and can use it everywhere. Everyone can be connected and interact with each other anytime anywhere.

4 Mobile Applications Drive the Package Development System packaging needs Small form factor High performance High bandwidth Low power consumption Low cost Small form factor Lower power consumption Lower Cost High Bandwidth

5 WLP and PLP Wafer Level Package (WLP) Panel Level Package (PLP) Processing Size or larger Material Base Equipment Major is silicon, but glass and organic are possible Semiconductor centric; Stepper, coater, sputter.. Density Capabilities Down to 1 um L/S, via 5 um Major organic but glass or a-silicon are possible Organic substrate centric; Laser via, e-less, lamination of dielectric.. Down to 5 um L/S, via 30 um Cost down Potential Baseline Better

6 Line Embedded Technology Line First PLP Line Last PLP Copper Line Formation Copper line formed before dielectric Copper line formed after dielectric Cavity/line formation SAP copper Photo sensitive Dielectric, Laser trench Structure Formation Lamination Copper plating + Planaration Density capabilities Down to 5 um, via 30 um Down to 5 um, via 30 um Cost down Potential Better Basic

7 Line Last Embedded Technology Laser or photosensitive dielectric trench formation L/S < 8/8 um fine pitch trench can be formed Better adhesion than SAP process Challenges: Materials availability Copper line revealing process 6/6 um 8/8 um 10/10 um

8 Line First Embedded Technology SAP copper trace formation L/S < 8/8 um can be formed Better copper trace adhesion than SAP process Challenges: More than one LE layer Packaging industry acceptance

9 Unimicron UTS-EP (Ultra Thin Substrate Embedded Pattern) Benefits: Z height reduction, low profile Better copper trace adhesion Good BOL assembly reliability Proven 15/15 um reliability Challenges Warpage control Packaging Industry acceptance SR Prepreg SR Embedded Trace Pattern Total Thickness :130±30um

10 Advantages of Embedded Passive/Active Substrate Form factor reduction Normal Embedded Packaging area reduction PoP thickness reduction Enhance electrical performance* SMT MLCC Noise Embedded MLCC Noise reduction* *: Murata

11 Embedded Passive Panel Level Process Method I Method II Component fixing method Solder Joint & PPG Filling PPG Resin Filling Via connection Method Company Solder Joint DNP, Clover, ATS, etc. Via Connection by Cu Plating Unimicron, Semco, etc Structure Features 1. Sn solder terminal 2. Bigger embedded area required 3. Single side connection. 4. Compactible with current PCB Process 1. Cu Terminal needed 2. Dual side connection possible 3. Compactible with current PCB Process 4. Smaller cavity Size

12 Embedded Passive Substrate Process Key Items Components placement accuracy MLCC Interface Adhesion with Dielectric Layer MLCC MLCC Warpage Control

13 MLCC Cross Section Pitch between electrode: 2.0 um MLCC Information: Size: 0402 Thickness: 0.11mm Capacitance: 100nF

14 Embedded Component Substrate Process Core Layer MLCC Embedding Build up Solder Mask Surface Finishing Through hole Drilling Cavity Formation Taping Strip Forming Patterning MLCC Placement MLCC Shipping Lamination side 1 MLCC Lamination side 2 MLCC Confidential 14

15 Roadmap of Embedded Passive Substrate Year Size Embedded Component Type MLCC Resistor Inductor Multi- Components R C C R Discrete numbers per cavity Structure Design Core Thk. 100um 60um W/O core Inner 2L;1/2/1 Coreless 1/0/1

16 Comparison of Embedded Active & Passive Components Active Passive Embedded Component Size Large Small Thickness < 100 um 100 um min. I/Q Counts Many Few Embedded Quantities One, Few Many Material Base Silicon Ceramic/glass Surface Base PI Ceramic/glass Electrode Base Plated Cu Plated Cu Component Package Placement Equipment Wafer / Tray / Tape & Reel Chip Shooter / Die Bonder Tape & Reel Chip Shooter

17 FOWLP and PLP Process Comparison FOWLP PLP Structure Substrate Size O Symmetrical Build No Yes* L/S-Routing Density O Thickness O Equipment Cost O 3D Extendibility O O Cost Down Potential O O: Good ; :OK *: Single side possible

18 Structure Roadmap of Embedded Active Substrate Embedded Package Multi-Chip Embedded Package PLP Package PoP Dual Die Module Active +Passive FOWLP Package FOWLP PoP

19 Embedded Interposer Carrier (EIC) Features: Combine interposer and organic substrate. Eliminates the solder joints between interposer and organic substrate. Benefits: Layer reduction compare with conventional organic substrate. Alternative solution for high density SiP. Cost reduction by interposer/carrier integration. Interposer I P D C A P Organic Laminated Substrate Embedded Interposer Carrier (EIC)

20 Chip on Interposer on Substrate vs. FC-EIC Chip Chip CoIoS FC-EIC Chip on Interposer on Substrate: (CoIoS) Interposer need double side RDL/Bumping and assembly process. Four testing steps are used: Interposer, carrier, Interposer+carrier, chip+interposer +carrier.. FC-EIC : Flip Chip Embedded Interposer Carrier Interposer needs to be embedded into the substrate. Only two testing steps are used: interposer, and interposer+carrier. Risk of thin wafer handling process is reduced.

21 FC-EIC Benefits FC-EIC has low profile and cost benefit than ColoS. This structure eliminates the solder joining between the interposer and the laminated organic substrate. The connections of interposer to carrier in EIC structure are copper to copper which have less resistance and inductance compare to the conventional solder joints; better electrical performance. Know good EIC substrate, reduce chip assemble loss. Interposer is protected by the carrier in EIC structure. Large interposer sizes are possible. Thin interposers (30 or 50 um thickness) can be included in EIC structure. Thin interposers have a lower processing cost in via forming and via plating. EIC structure has a lower profile than CoIoS. EIC structure is compatible with current backend infrastructure.

22 EIC Structure Cross Section View C4 I1 I0 C3 C2 C1 EIC ABF 4 ABF 3 ABF 2 V 0 ABF 1 Silicon Interposer ABF Via Silicon Interposer TSV Si Interposer Die Build Up Layer Unit: µm Die Thk. (um) 97 T / B (um) 49.6 /48.8 TSV Via CD I 0 CD (um) 59 I 0 Metal Thk. (um) 1 PBO 1 Thk. (um) 5 I 1 Layer PBO 1 CD (um) 39 I 1 Metal Thk. (um) 4 ABF 1 Thk. (um) 31 C1 Layer V0 T CD (um) 69 V0 B CD (um) 36 C1 Thk. (um) 23 C2 Layer* ABF 2 Thk. (um) 59 C3 Layer C4 Layer ABF 3 Thk. (um) ABF 4 Thk. (um) C3 Thk. (um) C4 Thk. (um) *:, TJ Tseng, YH Chen, WJ Lo ECTC 2013

23 The Changing Role of Substrate New Role of Substrate in 3D ERA - Panel Level Module Integration - Optical Fiber Now Future

24 Summary and Conclusions 1. Panel level embedded technology is becoming a fast growing technology to achieve the packaging requirement of; small form factor, high performance and low cost. 2. Currently embedded passive components is in mass production, and embeding active device is emerging. 3. Panel Level Packing has potential cost advantage over FOWLP due to her PCB centric production infrastructure. 4. Equipment and material improvement will expend the scope of panel level embedded technology. 5. New concept such as embedded interposer or other components into the substrate is emerging. 6. The role of laminate substrate is emerging as a system integrator based on panel level embedding technology.

25 Thank you for your Attention!

A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages

A Manufacturing Technology Perspective of: Embedded Die in Substrate and Panel Based Fan-Out Packages Bernd K Appelt Director WW Business Development April 24, 2012 Table of Content Definitions Wafer Level