ICM7228. Features. 8-Digit, Microprocessor-Compatible, LED Display Decoder Driver. Applications. Data Sheet August 19, 2015

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1 Data Sheet August 9, 205 F Digit, Microprocessor-Compatible, LED Display Decoder Driver The Intersil ICM722 display driver interfaces microprocessors to an -digit, 7-segment, numeric LED display. Included on chip are two types of 7-segment decoder, multiplex scan circuitry, LED display segment drivers, LED display digit drivers and an -byte static memory as display RAM. Data can be written to the ICM722A and ICM722B s display RAM in sequential -digit update or in single-digit update format. Data is written to the ICM722C display RAM in parallel random access format. The ICM722A and ICM722C drive common anode displays. The ICM722B drives common cathode displays. All versions can display the RAM data as either Hexadecimal or Code B format. The ICM722A and ICM722B incorporate a o Decode mode allowing each bit of each digit's RAM word to drive individual display segments resulting in independent control of all display segments. As a result, bargraph and other irregular display segments and formats can be driven directly by this chip. The Intersil ICM722 is an alternative to both the Maxim ICM72 and the Intersil ICM72 display drivers. otice that the ICM722A/B has an additional single digit access mode. This could make the Intersil ICM72A/B software incompatible with ICM722A/B operation. Features Pb-Free Plus Anneal Available (RoHS Compliant) Improved 2nd Source to Maxim ICM72 Fast Write Access Time of 200ns Multiple Microprocessor Compatible Versions Hexadecimal, Code B and o Decode Modes Individual Segment Control with o Decode Feature Digit and Segment Drivers On-Chip on-overlapping Digits Drive Common Anode and Common Cathode LED Versions Low Power CMOS Architecture Single 5V Supply Applications Instrumentation Test Equipment Hand Held Instruments Bargraph Displays umeric and on-umeric Panel Displays High and Low Temperature Environments where LCD Display Integrity is Compromised CAUTIO: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. --ITERSIL or Intersil (and design) is a registered trademark of Intersil Americas LLC Copyright Intersil Americas LLC , 205. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Ordering Information PART UMBER PART MARKIG DATA ETRY PROTOCOL DISPLAY TYPE TEMP. RAGE ( C) PACKAGE PKG. DWG. # ICM722AIBI (o longer available, ICM722AIBI Sequential Common Anode -40 to 5 2 Ld SOIC M2.3 recommended replacement: ICM722AIBIZ) ICM722AIBIZ (ote) 722AIBIZ Sequential Common Anode -40 to 5 2 Ld SOIC (Pb-free) M2.3 ICM722AIPI (o longer available, recommended replacement: ICM722AIPIZ) ICM722AIPI Sequential Common Anode -40 to 5 2 Ld PDIP E2.6 ICM722AIPIZ (ote) ICM722AIPI Sequential Common Anode -40 to 5 2 Ld PDIP* (Pb-free) E2.6 ICM722BIBI (o longer available, ICM722BIBI Sequential Common Cathode -40 to 5 2 Ld SOlC M2.3 recommended replacement: ICM722BIBIZ) ICM722BIBIZ (ote) ICM722BIBIZ Sequential Common Cathode -40 to 5 2 Ld SOlC (Pb-free) M2.3 ICM722BIPI (o longer available, recommended replacement: ICM722BIPIZ) ICM722BIPI Sequential Common Cathode -40 to 5 2 Ld PDIP E2.6 ICM722BIPIZ (ote) ICM722BIPIZ Sequential Common Cathode -40 to 5 2 Ld PDIP (Pb-free) E2.6 ICM722CIBI (o longer available, ICM722CIBI Random Common Anode -40 to 5 2 Ld SOlC M2.3 recommended replacement: ICM722CIBIZ) ICM722CIBIZ (ote) ICM722CIBIZ Random Common Anode -40 to 5 2 Ld SOlC (Pb-free) M2.3 ICM722CIPI (o longer available, recommended replacement: ICM722CIPIZ) ICM722CIPI Random Common Anode -40 to 5 2 Ld PDIP E2.6 ICM722CIPIZ (ote) ICM722CIPI Random Common Anode -40 to 5 2 Ld PDIP (Pb-free) E2.6 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. OTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD

3 Pinouts ICM722A (PDIP, SOIC) COMMO AODE TOP VIEW ICM722B (PDIP, SOIC) COMMO CATHODE TOP VIEW SEG c 2 DIGIT 4 2 SEG e 2 27 SEG a DIGIT DIGIT 7 SEG b 3 26 SEG g DIGIT DIGIT 5 DP 4 25 SEG d DIGIT 4 25 DIGIT 2 ID6 (HEXA/CODE B) 5 24 SEG f ID6 (HEXA/CODE B) 5 24 DIGIT ID5 (DECODE) 6 23 DIGIT 3 ID5 (DECODE) 6 23 SEG g ID7 (DATA COMIG) 7 22 DIGIT 6 ID7 (DATA COMIG) 7 22 SEG f WRITE 2 DIGIT 7 WRITE 2 SEG e MODE 9 20 DIGIT 4 MODE 9 20 SEG c ID4 (SHUTDOW) 0 9 ID4 (SHUTDOW) 0 9 ID DIGIT ID SEG d ID0 2 7 DIGIT 5 ID0 2 7 SEG b ID2 3 6 DIGIT 2 ID2 3 6 SEG a ID3 4 5 DIGIT ID3 4 5 DP ICM722C (PDIP, SOIC) COMMO AODE TOP VIEW SEG c SEG e 2 SEG b 3 DP 4 DA0 (DIGIT ADDRESS 0) 5 DA (DIGIT ADDRESS ) 6 ID7 (IPUT DP) 7 WRITE HEXA/CODE B/SHUTDOW 9 DA2 (DIGIT ADDRESS 2) 0 ID ID0 2 ID2 3 ID SEG a SEG g SEG d SEG f DIGIT 3 DIGIT 6 DIGIT 7 DIGIT 4 DIGIT DIGIT 5 DIGIT 2 DIGIT 3

4 Functional Block Diagram ICM722A, ICM722B ICM722C ID0 - ID7 IPUT DATA ID4 - ID7 COTROL IPUTS MODE WRITE 4 HEXADECIMAL/ CODE B/ SHUTDOW ID0 - ID3 ID7 DATA IPUT WRITE 5 DA0 - DA2 DIGIT ADDRESS 3 DECODE HEXA/CODE B COTROL LOGIC SHUTDOW THREE LEVEL IPUT LOGIC SHUTDOW -BYTE STATIC RAM WRITE ADDRESS COUTER -BYTE STATIC RAM WRITE ADDRESS COUTER 7 4 READ ADDRESS, DIGIT MULTIPLEXER 4 READ ADDRESS MULTIPLEXER HEXADECIMAL/ CODE B DECODER MULTIPLEX OSCILLATOR HEXADECIMAL/ CODE B DECODER MULTIPLEX OSCILLATOR DECODE O-DECODE 7 DECIMAL POIT ITERDIGIT BLAKIG 7 DECIMAL POIT ITERDIGIT BLAKIG SEGMET DRIVERS DIGIT DRIVERS SEGMET DRIVERS DIGIT DRIVERS 4

5 Absolute Maximum Ratings Supply Voltage ( - ) V Digit Output Current mA Segment Output Current mA Input Voltage (ote ) (Any Terminal).. ( -0.3V)<V I <( +0.3V) Operating Conditions Operating Temperature Range o C to 5 o C Thermal Information Thermal Resistance (Typical, ote 2) JA ( o C/W) PDIP Package* SOIC Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 50 o C Maximum Lead Temperature (Soldering 0s) o C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTIO: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. OTES:. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than or less then may cause destructive device latchup. For this reason, it is recommended that no inputs row sources operating on a different power supply be applied to the device before its own supply is established, and when using multiple supply systems the supply to the ICM722 should be turned on first. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details. Electrical Specifications = +5.0V ±0%, = 0V, Unless Otherwise Specified T A = 25 o C -40 o C TO 5 o C PARAMETER TEST CODITIOS MI TYP MAX MI TYP MAX UITS Supply Voltage Range, V SUPPLY Operating V Power Down Mode Quiescent Supply Current, I Q Shutdown, ICM722A, IMC722B A Shutdown, 722C Operating Supply Current, I DD Digit Drive Current, I DIG Common Anode, ICM722A/C Segments = O; Outputs = OPE Common Anode, ICM722A/C Segments = OFF; Outputs = OPE Common Cathode, ICM722B Segments = O; Outputs = OPE Common Cathode, ICM722B Segments = OFF; Outputs = OPE Common Anode, ICM722A/C V OUT = - 2.0V Common Cathode, ICM722B V OUT = +.0V A ma Digit Leakage Current, I DLK Shutdown Mode, V OUT = 2.0V Common Anode, ICM722A/C Shutdown Mode, V OUT = 5.0V Common Cathode, 722B A Peak Segment Drive Current, I SEG Segment Leakage Current, I SLK Common Anode, ICM722A/C V OUT = +.0V Common Cathode, 722B V OUT = - 2.0V Shutdown Mode, V OUT = Common Anode, ICM722A/C Shutdown Mode, V OUT = Common Cathode, ICM722B ma A

6 Electrical Specifications = +5.0V ±0%, = 0V, Unless Otherwise Specified (Continued) T A = 25 o C -40 o C TO 5 o C PARAMETER TEST CODITIOS MI TYP MAX MI TYP MAX UITS Input Leakage Current, I IL All Inputs Except Pin 9, ICM722C, A V I = All Inputs Except Pin 9, ICM722C, V I = 5.0V Display Scan Rate, f MUX Per Digit Hz Inter-Digit Blanking Time, t IDB s Logical Input Voltage, V IH Three Level Input: Pin 9 ICM722C, Hexadecimal = 5V Floating Input, V IF Three Level Input: Pin 9 ICM722C, Code B, = 5V Logical 0 Input Voltage, V IL Three Level Input: Pin 9 ICM722C, Shutdown, = 5V V V V Three Level Input Impedance, Z I V CC = 5V, Pin 9 of ICM722C k Logical Input Voltage, V IH Logical 0 Input Voltage, V IL All Inputs Except, Pin 9 of ICM722C, = 5V All Inputs Except, Pin 9 of ICM722C, = 5V V V SWITCHIG SPECIFICATIOS = +5.0V 0%, = 0V, V IL = +0.4V, V IH = +2.4V Write Pulsewidth (Low), t WL ns Write Pulsewidth (High), t WH ns Mode Hold Time, t MH ICM722A, ICM722B ns Mode Setup Time, t MS ICM722A, ICM722B ns Data Setup Time, t DS ns Data Hold Time, t DH ns Digit Address Setup Time, t AS ICM722C ns Digit Address Hold Time, t AH ICM722C ns 6

7 Timing Diagrams MODE t MS t MH MODE WRITE WRITE IPUT DATA t WL t DS VALID t DH t WH (D) WRITE DATA PULSES COTROL WORD TYPE OF DECODER?ID6 DECODE/O DECODE? ID5 SHUTDOW?ID4 DATA COMIG ID7 (D) DO T CARE COTROL WORD TYPE OF DECODER?ID6 DECODE/O DECODE? ID5 SHUTDOW? ID4 DATA COMIG ID7 FIGURE. ICM722A/B WRITE CYCLE FIGURE 2. ICM722A/B SEQUETIAL -DIGIT RAM UPDATE DIGIT ADDRESS DAO-DAZ t AS VALID t AH WRITE t WL t WH t DS t DH DATA VALID DATA FIGURE 3. ICM722C WRITE CYCLE ITERDIGIT BLAKIG ITERAL SIGAL D2 D5 D D7 0 s (TYP) FREE RUIG ITERDIGIT BLAKIG 320 s (TYP) FREE RUIG (PER DIGIT) TYPICAL DIGITS PULSES D D6 D4 D3 FIGURE 4. DISPLAY DIGITS MULTIPLEX (COMMO AODE DISPLAY) 7

8 Typical Performance Curves o C 25 o C 25 o C o C I DIG (ma) o C 25 o C I SEG (ma) o C 25 o C o C V DIG (V) V SEG (V) FIGURE 5. COMMO AODE DIGIT DRIVER I DIG vs ( - V DIG ) FIGURE 6. COMMO AODE SEGMET DRIVER I SEG vs V SEG -55 o 25 o C C o C 20 I DIG (ma) o C 25 o C I SEG (ma) o C V DIG (V) -V SEG (V) FIGURE 7. COMMO CATHODE DIGIT DRIVER I DIG vs V DIG FIGURE. COMMO CATHODE SEGMET DRIVER I SEG vs ( - V SEG ) TABLE. ICM722A PI ASSIGMETS AD DESCRIPTIOS PI O. AME FUCTIO DESCRIPTIO SEG c Output LED Display Segments c, e, b and Decimal Point Drive Lines. 2 SEG e 3 SEG b 4 DP 5 ID6, (HEXA/CODE B) Input When MODE Low: Display Data Input, Bit 7. When MODE High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. 6 ID5, (DECODE) Input When MODE Low: Display Data Input, Bit 6. When MODE High: Control Bit, Decode/o Decode Selection: High, o Decode; Low, Decode. 7 ID7, (DATA COMIG) Input When MODE Low: Display Data Input, Bit, Decimal Point Data. When MODE High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, o Data Coming. WRITE Input Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE.

9 TABLE. ICM722A PI ASSIGMETS AD DESCRIPTIOS (Continued) PI O. AME FUCTIO DESCRIPTIO 9 MODE Input Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. 0 ID4, (SHUTDOW) Input When MODE Low: Display Data Input, Bit 5. When MODE High: Control Bit, Low Power Mode Select: High, ormal Operation; Low, Oscillator and Display Disabled. ID Input When MODE Low: Display Data Input, Bit 2. When MODE High and ID7 (DATA COMIG) Low: Digit Address, Bit 2, Single Digit Update Mode. 2 ID0 Input When MODE Low: Display Data Input, Bit. When MODE High and ID7 (DATA COMIG) Low: Digit Address, LSB, Single Digit Update Mode. 3 ID2 Input When MODE Low: Display Data Input, Bit 3. When MODE High and ID7 (DATA COMIG) Low: Digit Address, MSB, Single Digit Update Mode. 4 ID3 Input When MODE Low: Display Data Input, Bit 4. When MODE High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM Bank B 5 DIGIT Output LED Display Digits, 2, 5 and Drive Lines. 6 DlGlT 2 7 DIGIT 5 DlGlT 9 Supply Device Positive Power Supply Rail. 20 DIGIT 4 Output LED Display Digits 4, 7, 6 and 3 Drive Lines. 2 DlGlT 7 22 DlGlT 6 23 DIGlT 3 24 SEG f Output LED Display Segments f, d, g and a Drive Lines. 25 SEG d 26 SEG g 27 SEG a 2 Supply Device Ground or egative Power Supply Rail. TABLE 2. ICM722B PI ASSIGMETS AD DESCRIPTIOS PI O. AME FUCTIO DESCRIPTIO DIGIT 4 Output LED Display Digits 4, 6, 3 and Drive Lines. 2 DlGlT 6 3 DIGIT 3 4 DlGlT 5 ID6, (HEXA/CODE B) Input When MODE Low: Display Data Input, Bit 7. When MODE High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. 6 ID5, (DECODE) Input When MODE Low: Display Data Input, Bit 6. When MODE High: Control Bit, Decode/o Decode Selection: High, o Decode; Low, Decode. 7 ID7, (DATA COMIG) Input When MODE Low: Display Data Input, Bit, Decimal Point Data. When MODE High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, o Data Coming. 9

10 TABLE 2. ICM722B PI ASSIGMETS AD DESCRIPTIOS (Continued) PI O. AME FUCTIO DESCRIPTIO WRITE Input Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE. 9 MODE Input Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. 0 ID4, (SHUTDOW) Input When MODE Low: Display Data Input, Bit 5. When MODE High: Control Bit, Low Power Mode Select: High, ormal Operation; Low, Oscillator and Display Disabled. ID Input When MODE Low: Display Data Input, Bit 2. When MODE High and ID7 (DATA COMIG) Low: Digit Address, Bit 2, Single Digit Update Mode. 2 ID0 Input When MODE Low: Display Data Input, Bit. When MODE High and ID7 (DATA COMIG) Low: Digit Address, LSB, Single Digit Update Mode. 3 ID2 Input When MODE Low: Display Data Input, Bit 3. When MODE High and ID7 (DATA COMIG) Low: Digit Address, MSB, Single Digit Update Mode. 4 ID3 Input When MODE Low: Display Data Input, Bit 4. When MODE High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM Bank B. 5 DP Output LED Display Decimal Point and Segments a, b, and d Drive Lines 6 SEG a 7 SEG b SEG d 9 Supply Device Positive Power Supply Rail. 20 SEG c Output LED Display Segments c, e, f and g Drive Lines. 2 SEG e 22 SEG f 23 SEG g 24 DIGIT Output LED Display Digits, 2, 5 and 7 Drive Lines. 25 DIGIT 2 26 DIGIT 5 27 DIGIT 7 2 Supply Device Ground or egative Power Supply Rail. TABLE 3. ICM722C PI ASSIGMETS AD DESCRIPTIOS PI O. AME FUCTIO DESCRIPTIO SEG c Output LED Display Segments c, e, band Decimal Point Drive Lines. 2 SEG e 3 SEG b 4 DP 5 DA0 Input Digit Address Input, Bit LSB. 6 DA Input Digit Address Input, Bit 2. 7 ID7, (IPUT DP) Input Display Decimal Point Data Input, egative True. WRITE Input Data Input Will Be Written to Display RAM on Rising Edge of WRITE. 0

11 9 HEXA/CODE B/SHUTDOW TABLE 3. ICM722C PI ASSIGMETS AD DESCRIPTIOS (Continued) PI O. AME FUCTIO DESCRIPTIO Input Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B Decoding; Low, Oscillator, and Display Disabled. 0 DA2 Input Digit Address Input, Bit 3, MSB. ID Input Display Data Inputs. 2 ID0 3 ID2 4 ID3 5 DIGIT Output LED Display Digits, 2, 5 and Drive Lines. 6 DlGlT 2 7 DIGIT 5 DlGlT 9 Supply Device Positive Power Supply Rail. 20 DIGIT 4 Output LED Display Digits 4, 7, 6 and 3 Drive Lines. 2 DlGlT 7 22 DlGlT 6 23 DIGlT 3 24 SEG f Output LED Display Segments f, d, g and a Drive Lines. 25 SEG d 26 SEG g 27 SEG a 2 Supply Device Ground or egative Power Supply Rail. Detailed Description System Interfacing and Data Entry Modes, ICM722A and ICM722B The ICM722A/B devices are compatible with the architectures of most microprocessor systems. Their fast switching characteristics makes it possible to access them as a memory mapped I/O device with no wait state necessary in most microcontroller systems. All the ICM722A/B inputs, including MODE, feature a 250ns minimum setup and 0ns hold time with a 200ns minimum WRITE pulse. Input logic levels are TTL and CMOS compatible. Figure 9 shows a generic method of driving the ICM722A/B from a microprocessor bus. To the microprocessor, each device appears to be 2 separate I/O locations; the Control Register and the Display RAM. Selection between the two is accomplished by the MODE input driven by address line A0. Input data is placed on the ld0 - ld7 lines. The WRITE input acts as both a device select and write cycle timing pulse. See Figure and Switching Specifications Table for write cycle timing parameters. The ICM722A/B have three data entry modes: Control Register update without RAM update, sequential -digit update and single digit update. In all three modes a control word is first written by pulsing the WRITE input while the MODE input is high, thereby latching data into the Control Register. The logic level of individual bits in the Control Register select Shutdown, Decode/o Decode, Hex/Code B, RAM bank A/B and Display RAM digit address as shown in Tables and 2. The ICM722A/B Display RAM is divided into 2 banks, called bank A and B. When using the Hexadecimal or code B display modes, these RAM banks can be selected separately. This allows two separate sets of display data to be stored and displayed alternately. otice that the RAM bank selection is not possible in o-decode mode, this is because the display data in the o-decode mode has bits, but in Decoded schemes (Hex/Code B) is only 4 bits (ld0 - ld3 data). It should also be mentioned that the decimal point is independent of selected bank, a turned on decimal point will remain on for either bank. Selection of the RAM banks is controlled by ld3 input. The ld3 logic level (during Control Register update) selects which bank of the internal RAM to be written to and/or displayed. Control Register Update without RAM Update The Control Register can be updated without changing the display data by a single pulse on the WRITE input, with MODE high and DATA COMIG low. If the display is being decoded (Hex/Code B), then the value of ld3 determines which RAM bank will be selected and displayed for all eight digits.

12 Sequential -Digit Update The logic state of DATA COMIG (ld7) is also latched during a Control Register update. If the latched value of DATA COMIG (ld7) is high, the display becomes blanked and a sequential -digit update is initiated. Display data can now be written into RAM with successive WRITE pulses, starting with digit and ending with digit (See Figure 2). After all RAM locations have been written to, the display turns on again and the new data is displayed. Additional write pulses are ignored until a new Control Register update is performed. All digits are displayed in the format (Hex/Code B or o Decode) specified by the control word that preceded the digit update. If a decoding scheme (Hex/Code B) is to be used, the value of ld3 during the control word update determines which RAM bank will be written to. Single Digit Update In this mode each digit data in the display RAM can be updated individually without changing the other display data. First, with MODE input high, a control word is written to the Control Register carrying the following information; DATA COMIG (ld7) low, the desired display format data on ld4 - ld6, the RAM bank selected by ld3 (if decoding is selected) and the address of the digit to be updated on data lines ld0 - ld2 (See Table 4). A second write to the ICM722A/B, this time with MODE input low, transfers the data at the ld0 - ld7 inputs into the selected digit s RAM location. In single digit update mode, each individual digit s data can be specified independently for being displayed in Decoded or o-decode mode. For those digits which decoding scheme (Hex/Code B) is selected, only one can be effective at a time. Whenever a control word is written, the specified decoding scheme will be applied to all those digits which selected to be displayed in Decoded mode. DATA BUS D0-D7 MICROPROCESSOR SYSTEM I/O OR MEMORY WRITE PULSE A-A5 DECODER EABLE ADDRESS DECODER D0 - D7 DEVICE SELECT AD WRITE PULSE A0 ID0 ID7 WRITE MODE ITERSIL ICM722A/B SEGMETS DRIVE DIGITS DRIVE LED DISPLAY ADDRESS BUS A0 - A5 TABLE 4. DIGITS ADDRESS, ICM722A/B IPUT DATA LIES D2 ld2 ld0 SELECTED DIGIT DlGlT 0 0 DlGlT DIGlT 3 0 DlGlT DIGIT 5 0 DlGlT 6 0 DlGlT 7 DlGlT System Interfacing, ICM722C The ICM722C is directly compatible with the architecture of most microprocessor systems. Its fast switching characteristics make it possible to access them as a memory mapped I/O device with no wait state necessary in most microcontroller systems. All the ICM722C inputs, excluding HEXA/CODE B/SHUTDOW, feature a 250ns minimum FIGURE 9. ICM722A/B MICROPROCESSOR SYSTEM ITERFACIG setup and 0ns hold time with a 200ns minimum WRITE pulse. Input logic levels are TTL and CMOS compatible. Figure 0 shows a generic method of driving the ICM722C from a microprocessor bus. To the microprocessor, the bytes of the Display RAM appear to be separate I/O locations. Loading the ICM722C is quite similar to a standard memory write cycle. The address of the digit to be updated is placed on lines DA0 - DA2, the data to be written is placed on lines ID0 - ld3 and ID7, then a low pulse on WRITE input will transfer the data in. See Figure 3 and Switching Characteristics Table for write cycle timing parameters. The ICM722C does not have any control register, and also does not provide the o Decode display format. Hexadecimal or Code B character selection and shutdown mode are directly controlled through the three level input at Pin 9, which is accordingly called HEXA/CODE B/SHUTDOW. See Table 3 for input and output definitions of the ICM722C. 2

13 Display Formats The ICM722A and ICM722B have three possible display formats; Hexadecimal, Code B and o Decode. Table 5 shows the character sets for the decode modes and their corresponding input code. The display formats of the ICM722A/B are selected by writing data to bits ID4, ID5 and ID6 of the Control Register (See Table and 2 for input Definitions). Hexadecimal and Code B data is entered via ID0-lD3 and ID7 controls the decimal point. TABLE 5. DISPLAY CHARACTER SETS IPUT DATA CODE DISPLAY CHARACTERS ID3 ID2 ID ID0 HEXADECIMAL CODE B TABLE 5. DISPLAY CHARACTER SETS (Continued) IPUT DATA CODE DISPLAY CHARACTERS ID3 ID2 ID ID0 HEXADECIMAL CODE B A - 0 b E 0 0 C H 0 d L 0 E P F (Blank) DATA BUS D0 - D7 5 MICROPROCESSOR SYSTEM I/O OR MEMORY WRITE PULSE A3 - A5 DECODER EABLE ADDRESS DECODER DEVICE SELECT AD WRITE PULSE A0 - A2 ID0 - ID3 AD ID7 ITERSIL ICM722C SEGMETS DRIVE WRITE DA0 - DA2 DIGITS DRIVE LED DISPLAY ADDRESS BUS A0 - A5 FIGURE 0. ICM722C MICROPROCESSOR SYSTEM ITERFACIG a f b g e c d DP An input high level turns on the respective segment, except for the decimal point, which is turned on by an input low level on ID7. The o Decode mode can be used in different applications such as bar graph or status panel driving where each segment controls an individual LED. The o Decode mode of the ICM722A and ICM722B allows the direct segment-by-segment control of all 64 segments driven by the device. In the o Decode mode, the input data directly control the outputs as shown in Table 6. TABLE 6. O DECODE SEGMET LOCATIOS DATA IPUT ID7 ID6 ID5 ID4 ID3 ID2 ID ID0 Controlled Segment FIGURE. DIGITS SEGMET ASSIGMETS Decimal Point a b c e g f d The ICM722C has only the Hexadecimal and Code B character sets. The HEXA/CODE B/SHUTDOW input, pin 9, requires a three level input. Pin 9 selects the Hexadecimal format when pulled high, the Code B format when floating or driven to mid-supply, and the shutdown mode when pulled low (See Table 3). Table 5 also applies to the ICM722C. Shutdown and Display Banking When shutdown, the ICM722 enters a low power standby mode typically consuming only A of supply current for the ICM722A/B and 2.5 A for the ICM722C. In this mode the ICM722 turns off the multiplex scan oscillator as well as the digit and segment drivers. However, input data can still be 3

14 entered when in the shutdown mode. Data is retained in memory even with the supply voltage as low as 2V. The ICM722A/B is shutdown by writing a control word with Shutdown (ld4) low. The ICM722C is put into shutdown mode by driving pin 9, HEXA/CODE B/SHUTDOW, low. The ICM722 operating current with the display blanked is within 00 A A for all versions. All versions of the ICM722 can be blanked by writing Hex FF to all digits and selecting Code B format. The ICM722A and ICM722B can also be blanked by selecting o Decode mode and writing Hex 0 to all digits (See Tables 5and 6). Common Anode Display Drivers, ICM722A and ICM722C The common anode digit and segment driver output schematics are shown in Figure 2. The common anode digit driver output impedance is approximately 4. This provides a nearly constant voltage to the display digits. Each digit has a minimum of 200mA drive capability. The -Channel segment driver s output impedance of 50 limits the segment current to approximately 25mA peak current per segment. Both the segment and digit outputs can directly drive the display, current limiting resistors are not required. ghosting (a faint display of data from previous digit superimposed on the next digit). The interdigit blanking time is 0 s typical with a guaranteed 2 s minimum. The ICM722 turns off both the digit drivers and the segment drivers during the interdigit blanking period. The digit multiplexing sequence is: D2, D5, D, D7, D, D6, D4 and D3. A typical digit s drive pulses are shown on Figure 4. Due to the display multiplexing, the driving duty cycle for each digit is 2% (00 x / ) This means the average current for each segment is / of its peak current. This must be considered while designing and selecting the displays. Driving Larger Displays If very high display brightness is desired, the ICM722 display driver outputs can be externally buffered. Figures 4 thru 6 show how to drive either common anode or common cathode displays using the ICM722 and external driver circuit for higher current displays. Another method of increasing display currents is to connect two digit outputs together and load the same data into both digits. This drives the display with the same peak current, but the average current doubles because each digit of the display is on for twice as long, i.e., / 4 duty cycle versus /. Individual segment current is not significantly affected by whether other segments are on or off. This is because the segment driver output impedance is much higher than that of the digit driver. This feature is important in bar graph applications where each bar graph element should have the same brightness, independent of the number of elements being turned on. DIGIT STROBE ITERDIGIT BLAKIG P 200mA Common Cathode Display Driver, ICM722B The common cathode digit and segment driver output schematics are shown in Figure 3. The -channel digit drivers have an output impedance of approximately 5. Each digit has a minimum of 50mA drive capability. The segment drivers have an output impedance of approximately 00 with typically 0mA peak current drive for each segment. The common cathode display driver output currents are only / 4 of the common anode display driver currents. Therefore, the ICM722A and ICM722C common anode display drivers are recommended for those applications where high display brightness is desired. The ICM722B common cathode display driver is suitable for driving bubble-lensed monolithic 7 segment displays. They can also drive individual LED displays up to 0.3 inches in height when high brightness is not required. Display Multiplexing Each digit of the ICM722 is on for approximately 320 s, with a multiplexing frequency of approximately 390Hz. The ICM722 display drivers provide interdigit blanking. This ensures that the segment information of the previous digit is gone and the information of the next digit is stable before the next digit is driven on. This is necessary to eliminate display SHUTDOW 2k 2k COMMO AODE DIGIT OTE: When SHUTDOW goes low ITERDIGIT BLAKIG also stays low. FIGURE 2A. DIGIT DRIVER 4

15 SEGMET DATA ITERDIGIT BLAKIG SHUTDOW P 2k COMMO AODE SEGMET 75 ICM722A/C DIGIT UP TO 4A FIGURE 2B. SEGMET DRIVER FIGURE 2. COMMO AODE DISPLAY DRIVERS SEGMET 0K DIGIT STROBE ITERDIGIT BLAKIG SHUTDOW P 2k COMMO CATHODE DIGIT 5 FIGURE 4. DRIVIG HIGH CURRET DISPLAY, COMMO AODE ICM722A/C TO COMMO AODE FIGURE 3A. DIGIT DRIVER 00 SEGMET 2229 ICM722B 4 (00mA PEAK ) SEGMET DATA ITERDIGIT BLAKIG SHUTDOW P 2k 2k mA COMMO CATHODE SEGMET 5 DIGIT 4mA A PEAK FIGURE 5. DRIVIG HIGH CURRET DISPLAY, COMMO CATHODE ICM722B TO COMMO CATHODE DISPLAY OTE: When SHUTDOW goes low ITERDIGIT BLAKIG also stays low. FIGURE 3B. SEGMET DRIVER FIGURE 3. COMMO CATHODE DISPLAY DRIVERS 5

16 Power Supply Bypassing 00 SEGMET K.4A PEAK Connect a minimum of 47 F in parallel with 0. F capacitors between and of ICM722. These capacitors should be placed in close proximity to the device to reduce the power supply ripple caused by the multiplexed LED display drive current pulses. ICM722B 5 DIGIT 300 K K 25 (00mA PEAK ) 2229 FIGURE 6. DRIVIG HIGH CURRET DISPLAY, COMMO CATHODE ICM722B TO COMMO AODE DISPLAY Three Level Input, ICM722C As mentioned before, pin 9 is a three level input and controls three functions: Hexadecimal display decoding, Code B display decoding and shutdown mode. In many applications, pin 9 will be left open or permanently wired to one state. When pin 9 can not be permanently left in one state, the circuits illustrated in Figure 7 can be used to drive this three level input. HIGH = HEX LOW = SHUTDOW 74C26 THREE-STATE BUFFER PI 9 HIGH = HEX OR SHUTDOW LOW = CODE B HIGH = HEX LOW = SHUTDOW HIGH = HEX OR SHUTDOW LOW = CODE B HIGH = CODE B LOW = HEX CD406 CD4066 COTROL CD PI 9 PI 9 HIGH = SHUTDOW LOW = CODE B CD PI 9 HIGH = SHUTDOW LOW = HEX HIGH = SHUTDOW LOW = CODE B CD4069 OPE DRAI OR OPE COLLECTOR PI 9 PI 9 FIGURE 7. ICM722C PI 9 DRIVE CIRCUITS 6

17 Test Circuit + 5V ID6 (HEXA/CODE B) 5 ID5 (DECODE) 6 ID7 (DATA COMIG) 7 WRITE MODE 9 ID4 (SHUTDOW) 0 ID ID0 2 ID2 3 ID F +0. F ICM722A COMMO AODE DISPLAY D D7 D6 D5 D4 D3 D2 D f d g a c e b DP FIGURE. FUCTIOAL TEST CIRCUIT # Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISIO CHAGE August 9, 205 F360.9 Updated Ordering Information table and moved it from page to page 2. Added Revision History and About Intersil sections. Updated POD M2.3 to current revision. Changes: Added land pattern About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at 7

18 Dual-In-Line Plastic Packages (PDIP) IDEX AREA BASE PLAE SEATIG PLAE D B -C- -A- 2 3 /2 B D e D E OTES:. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ASI Y4.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication o Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.25mm). 9. is the maximum number of terminal positions. 0. Corner leads (,, /2 and /2 + ) for E.3, E6.3, E.3, E2.3, E42.6 will have a B dimension of inch ( mm). -B- A 0.00 (0.25) M C A A2 L B S A e C E C L e A C e B E2.6 (JEDEC MS-0-AB ISSUE B) 2 LEAD DUAL-I-LIE PLASTIC PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A A B B C D D E E e 0.00 BSC 2.54 BSC - e A BSC 5.24 BSC 6 e B L Rev. 2/00

19 Small Outline Plastic Packages (SOIC) IDEX AREA 2 3 D e B 0.25(0.00) M C A M E -B- -A- -C- SEATIG PLAE A B S H 0.25(0.00) M B A a 0.0(0.004) L M h x 45o C M2.3 (JEDEC MS-03-AE ISSUE C) 2 LEAD WIDE BODY SMALL OUTLIE PLASTIC PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A B C D E e 0.05 BSC.27 BSC - H h L o o 0 o o - Rev., /3 TYPICAL RECOMMEDED LAD PATTER (.50mm) (9.3mm) (.27mm TYP) (0.5mm TYP) OTES:. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication umber Dimensioning and tolerancing per ASI Y4.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.024 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO900 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. o license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 9