5800 AND BiMOS II LATCHED DRIVERS UCN5800L UCN5800A

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1 800 AND 80 Data Sheet B* CLEAR IN IN 2 IN 3 IN GROUND UCN800L UCN800A LATCHES V DD OUTPUT ENABLE SUPPLY OUT COMMON Dwg. PP-0A The UCN800A/L and UCN80A/EP/LW latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of or 8 data ( D type) latches with associated common CLEAR,, and OUTPUT ENABLE circuitry. The power outputs are bipolar npn Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or microprocessor I/O. The UCN800A and UCN800L each contain four latched drivers; the UCN80A, UCN80EP, and UCN80LW contain eight latched drivers. The UCN800A/L and UCN80A/EP/LW supersede the original BiMOS latched-input driver ICs (UCN00A and UCN80A). These second-generation devices are capable of much higher data input rates and will typically operate at better than MHz with a V logic supply. Circuit operation at 2 V affords substantial improvement over the MHz figure. The CMOS inputs are compatible with standard CMOS and NMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/power loads: relays, lamps, solenoids, small dc motors, etc. Note the UCN800A (DIP) and the UCN800L (SOIC) are electrically identical and share a common terminal number assignment. ABSOLUTE IMUM RATINGS at +2 C Free-Air Temperature Output Voltage, V CE V Supply Voltage, V DD V Input Voltage Range, V IN V to V DD V Continuous Collector Current, l C ma Package Power Dissipation, P D See Graph Operating Temperature Range, T A C to +8 C Storage Temperature Range, T S C to +0 C Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 00 ma and will withstand at least 0 V in the OFF state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability. The UCN800A is furnished in a standard -pin DIP; the UCN800L and UCN80LW in surface-mountable SOICs; the UCN80A in a 22-pin DIP with 0.00" (0.6 mm) row centers; the UCN80EP in a 28-lead PLCC. FEATURES To. MHz Data Input Rate High-Voltage, High-Current Outputs CMOS, NMOS, TTL Compatible Inputs Output Transient Protection Internal Pull-Down Resistors Low-Power CMOS Latches Automotive Capable Always order by complete part number, e.g., UCN80EP.

2 FUNCTIONAL BLOCK DIAGRAM SUPPLY V DD COMMON IN N OUT N CLEAR GROUND OUTPUT ENABLE COMMON MOS CONTROL TYPICAL MOS LATCH TYPICAL BIPOLAR DRIVE Dwg. FP-06- TYPICAL INPUT CIRCUIT V DD IN Dwg. EP-00-A ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS PIN DIP, RθJA = 6 C/W 28-LEAD PLCC, RθJA = 68 C/W -PIN DIP, RθJA = 73 C/W 2-LEAD SOIC, RθJA = 8 C/W -LEAD SOIC, RθJA = 20 C/W AMBIENT TEMPERATURE IN C Dwg. GP-023-A Northeast Cutoff, Box 036 Worcester, Massachusetts (08) Copyright 98, 2002 Allegro MicroSystems, Inc.

3 ELECTRICAL CHARACTERISTICS at T A = +2 C, V DD = V (unless otherwise noted). Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units Output Leakage Current I CEX V CE = 0 V, T A = +2 C 0 µa V CE = 0 V, T A = +70 C 00 µa Collector-Emitter V CE(SAT) I C = 00 ma 0.9. V Saturation Voltage I C = 200 ma..3 V I C = 30 ma, V DD = 7.0 V.3.6 V Input Voltage V IN(0).0 V V IN() V DD = 2 V 0. V V DD = 0 V 8. V V DD =.0 V (See Note) 3. V Input Resistance r IN V DD = 2 V kω V DD = 0 V kω V DD =.0 V kω Supply Current I DD(ON) V DD = 2 V, Outputs Open ma (Each Stage) V DD = 0 V, Outputs Open ma V DD =.0 V, Outputs Open ma I DD(OFF) V DD = 2 V, Outputs Open, Inputs = 0 V 200 µa (Total) V DD =.0 V, Outputs Open, Inputs = 0 V 0 00 µa Clamp Diode I R V R = 0 V, T A = +2 C 0 µa Leakage Current V R = 0 V, T A = +70 C 00 µa Clamp Diode Forward Voltage V F I F = 30 ma V NOTE: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to ensure a minimum logic. IN NC 3 ST 2 NC C CLEAR OUTPUT ENABLE 28 OE SUPPLY IN V DD 26 NC OUT UCN80EP (additional pinout diagrams are on next page) IN2 IN3 IN IN LATCHES K NC NC NC OUT OUT 6 IN7 OUT 7 IN8 GROUND LAMP DIODE COMMON OUT 8 Dwg. PP-037

4 UCN80A CLEAR F CLEAR 22 OUTPUT ENABLE IN 2 V 2 DD 3 SUPPLY 20 OUT OUTPUT ENABLE IN N A C B C B G A C B G IN 2 9 D E E IN 3 8 OUT N IN IN 6 LATCHES OUT TIG CONDITIONS (Logic Levels are V DD and Ground) Dwg. No. A-0,89A IN 6 IN OUT 6 OUT 7 A. Minimum Data Active Time Before Strobe Enabled (Data Set-Up Time)...0 ns IN 8 GROUND OUT 8 COMMON B. Minimum Data Active Time After Strobe Disabled (Data Hold Time)...0 ns Dwg. PP-0 C. Minimum Strobe Pulse Width...2 ns D. Typical Time Between Strobe Activation and Output On to Off Transition...00 ns UCN80LW E. Minimum Time Between Strobe Activation and Output Off to On Transition...00 ns F. Minimum Clear Pulse Width ns CLEAR IN IN 2 IN V DD OUTPUT ENABLE SUPPLY 22 OUT 20 G. Minimum Data Pulse Width...22 ns Information present at an input is transferred to its latch when the is high. A high CLEAR input will set all latches to the output OFF condition regardless of the data or input levels. A high OUTPUT ENABLE will set all outputs to the OFF condition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. IN IN IN 6 IN 7 IN 8 GROUND NO CONNECTION LATCHES NC NC 3 OUT OUT 6 OUT 7 OUT 8 COMMON NO CONNECTION Dwg. PP-0- TRUTH TABLE OUT OUTPUT N IN N CLEAR ENABLE t- t X OFF 0 0 X ON X X X X OFF X X X X OFF X ON ON X OFF OFF X = irrelevant. t- = previous output state. t = present output state. Northeast Cutoff, Box 036 Worcester, Massachusetts (08)

5 TYPICAL APPLICATION UNIPOLAR STEPPER-MOTOR DRIVE +30 V OUTPUT ENABLE (ACTIVE LOW) µρ CLEAR IN IN 2 IN 3 IN LATCHES V DD V DD OUT 7 8 UCN-800A +30 V Dwg. No. B-37 UNIPOLAR WAVE DRIVE UNIPOLAR 2-PHASE DRIVE IN IN IN 2 IN 2 IN 3 IN 3 IN IN OUT OUT Dwg. GP-060 Dwg. GP-060-

6 UCN800A Dimensions in Inches (controlling dimensions) Dwg. MA-00-A in Dimensions in Millimeters (for reference only) Dwg. MA-00-A mm NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. Northeast Cutoff, Box 036 Worcester, Massachusetts (08)

7 UCN800L Dimensions in Inches (for reference only) TO Dwg. MA-007- in Dimensions in Millimeters (controlling dimensions) TO NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. Dwg. MA-007-A mm

8 22 UCN80A Dimensions in Inches (controlling dimensions) Dwg. MA in 22 Dimensions in Millimeters (for reference only) NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below. Dwg. MA mm Northeast Cutoff, Box 036 Worcester, Massachusetts (08)

9 UCN80EP Dimensions in Inches (controlling dimensions) INDEX AREA Dwg. MA-00-28A in Dimensions in Millimeters (for reference only) INDEX AREA Dwg. MA-00-28A mm NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative.

10 2 3 UCN80LW Dimensions in Inches (for reference only) TO Dimensions in Millimeters (controlling dimensions) 3 Dwg. MA-008-2A in TO Dwg. MA-008-2A mm NOTES:. Exact body and lead configuration at vendor s option within limits shown. 2. Lead spacing tolerance is non-cumulative. Northeast Cutoff, Box 036 Worcester, Massachusetts (08)

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12 POWER INTERFACE DRIVERS Function Output Ratings* Part Number SERIAL-INPUT 8-Bit (saturated drivers) -20 ma 0 V 89 8-Bit 30 ma 0 V 82 8-Bit 30 ma 80 V Bit 30 ma 0 V 8 8-Bit 30 ma 80 V 82 8-Bit (constant-current LED driver) 7 ma 7 V Bit (constant-current LED driver) 20 ma 2 V Bit (DMOS drivers) 20 ma 0 V 69 8-Bit (DMOS drivers) 30 ma 0 V 6A9 8-Bit (DMOS drivers) 00 ma 0 V 6B9 0-Bit (active pull-downs) -2 ma 60 V Bit (active pull-downs) -2 ma 60 V 8 6-Bit (constant-current LED driver) 7 ma 7 V Bit (active pull-downs) -2 ma 60 V Bit (active pull-downs) -2 ma 60 V Bit 00 ma 30 V Bit (saturated drivers) 00 ma 0 V 832 PARALLEL-INPUT -Bit 30 ma 0 V Bit -2 ma 60 V 8 8-Bit 30 ma 0 V 80 8-Bit (DMOS drivers) 00 ma 0 V 6B273 8-Bit (DMOS drivers) 20 ma 0 V 6273 SPECIAL-PURPOSE DEVICES Addressable 8-Bit Decoder/DMOS Driver 20 ma 0 V 629 Addressable 8-Bit Decoder/DMOS Driver 30 ma 0 V 6A29 Addressable 8-Bit Decoder/DMOS Driver 00 ma 0 V 6B29 Addressable 28-Line Decoder/Driver 0 ma 30 V 687 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Internal transient-suppression diodes included for inductive-load protection. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. Northeast Cutoff, Box 036 Worcester, Massachusetts (08)