First IEEE International High Speed Interconnects Symposium From Silicon to Systems

Transcription

1 First IEEE International High Speed Interconnects Symposium From Silicon to Systems Sponsored by IEEE UTD Students Branch and IEEE CAS Dallas Chapter Semiconductor Research Corporation (SRC)

2 Sponsor IEEE UTD Students Branch Sponsor Dr. Cyrus Cantrell Andres Zevallos (President) Ryan Marcotte (Treasurer) Jasmine Singh (Secretary) Anubha Vashistha (Public Relations) Kenneth Livingston (Vice Presedent)

3 Sponsors IEEE Dallas CAS Society Arjun Rajagopal Industrial Liaisons Chair Texas Instruments IEEE CAS Society Chair, Dallas Chapter Saqib Malik Finance Chair Texas Instruments IEEE CAS Society Chair, Dallas Chapter

4 SRC David Yeh Jonathan Candelaria Bill Joyner Sponsors Semiconductor Research Corporation

5 Program Chairs and Steering Committee Program Chairs: David Pan Professor, UT Austin Ram Achar Professor, Carleton University, Ottawa, Canada Steering Committee: Poras Balsara Professor, UT Dallas Bobby Chang Director, Global Leadership EMBA, UT Dallas Andrew Kahng Professor, Univ. of San Diego Bill Krenik Texas Instruments Koduri Sreenivasan Texas Instruments Shankar Balachandran Professor, IIT Madras, India Juan Rey Senior Director, Mentor Graphics Corporation Andrzej Strojwas Professor, CMU Bharadwaj Amrutur Professor, Indian Institute of Science, India Krishna Saraswat Professor, Stanford University Sachin Sapatnekar Professor, Univ. of Michigan Azad Naeemi Professor, Georgia Tech

6 Program Committee Maira Azzolini Global Leadership EMBA, UT Dallas Ben Huang Global Leadership EMBA, UT Dallas Mike Moore Global Leadership EMBA, UT Dallas James Hume Global Leadership EMBA, UT Dallas Arvind NV Texas Instruments India

7 Interconnect Continuum Paradigm The fascinating field of interconnects span from the trenches of ultra-deep-submicron silicon technologies to millimeter to kilometers of interconnects in systems. The fundamentals of Electromagnetics developed over 150 years ago govern the operations in the whole spectrum, while the adaptations of techniques are different at different levels. In the Interconnect Continuum paradigm, global optimization of interconnects for overall silicon to system performance and cost benefits can be achieved, circumventing local minima. Nagaraj NS General Chair of the Symposium This symposium covers several topics from silicon manufacturing, variability, SoC design, package/board design, reliability effects and emerging interconnects by eminent speakers in academia and semiconductor industry.

8 Local vs. Global Optimum Local optimization is necessary, but not sufficient Double or triple patterning at lower level metals Clock layer assignments Power-grid design Package/board design However interconnect continuum enables global optimum Avoids too much padding in separate segments Enables new research and development Modeling algorithms Adaptive techniques Cost reduction Nagaraj NS

9 Manufacturing and Design Variations Manufacturing Variations Transistor and interconnect variations Transistor: Idrive, Vt, Cg resulting from variations in Tox, W, L, stress, strain Interconnect: R and C resulting from variations in geometries of metal/dielectric Within-die, die to die, wafer to wafer, lot to lot and fab to fab Local variations in a small region and global variations Within-die Die to die Wafer to wafer Lot to lot Fab to fab Design Induced Variations Voltage drop variations Temperature variations Jitter variations (Clocks) Reliability variations (NBTI/PBTI) IR-Drop Thermal Gradients Source: Gradient DA Nagaraj NS IEEE DAC /IITC Tutorials

10 Applications to Variability Circuit performance, signal and power integrity are function of multiple process variables Silicon, package and systems Joint density function helps in determining the combined behavior of multiple distributions Let V 1,.,V n are n random variables with means m 1,., m n and sigma of s 1,.,s n. Let a 1,.,a n are numerical weighting factors Let S be the sum of a i V i, with mean n m and sigma s S i 1 a i V i If X 1,.,X n are independent random variables, m n i 1 a i m i s n i 1 a 2 s 2 i i Manufacturing steps of transistors, silicon interconnect, package interconnect and system interconnect are independent of each other. Leverage it!! Nagaraj NS