High-Efficiency Power Conversion for Renewable Energy and Distribution Generation

Transcription

1 High-Efficiency Power Conversion for Renewable Energy and Distribution Generation November 2, 29 Presentation at PEDS 29 Taipei, Taiwan Professor Jih-Sheng (Jason) Lai Future Energy Electronics Center irginia Polytechnic Institute and State University 16 Plantation Road Blacksburg, A JSL 1 Outline Part A High Efficiency DC-DC Converters 1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter 3. High Boost Ratio DC-DC Converters Part B High Efficiency Inverters 1. Half-Cycle Asymmetrical Unipolar PWM 2. Single-Stage Power Conversion 3. Dual Buck Converters 4. H5 Inverter 5. Isolated Single-Stage Design 6. Soft-Switching Inverters Part C Energy Efficiency Standards JSL 2

2 Outline Part A Part A High Efficiency DC-DC Converters 1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter 3. High Boost Ratio DC-DC Converters Part B High Efficiency Inverters 1. Half-Cycle Asymmetrical Unipolar PWM 2. Single-Stage Power Conversion 3. Dual Buck Converters 4. H5 Inverter 5. Isolated Single-Stage Design 6. Soft-Switching Inverters Part C Energy Efficiency Standards JSL 3 Outline Part A-1 Part A High Efficiency DC-DC Converters 1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter 3. High Boost Ratio DC-DC Converters Part B High Efficiency Inverters 1. Half-Cycle Asymmetrical Unipolar PWM 2. Single-Stage Power Conversion 3. Dual Buck Converters 4. H5 Inverter 5. Isolated Single-Stage Design 6. Soft-Switching Inverters Part C Energy Efficiency Standards JSL 4

3 Why Single-Switch DC-DC Converters are Inefficient? Forward: <5% Flyback: <5% i M-pk Magnetizing current i M t B i M Half-bridge: 1% Push-pull: 1% Full-bridge: 1% B i M-pk t Ni M-pk H Ni M-pk Ni M-pk H Core is half utilized Core is fully utilized JSL 5 2 >25A M 1 a Half-Bridge DC/DC Converter C 1 1 >5A i 1 1 : n i 2 D 5 D 7 i L L 4 5 kw in M 2 b C 2 D 6 D 8 v d C R vo Low device count Low voltage device Device sees twice current Unbalance due to split capacitors High leakage due to twice transformer turns ratio JSL 6

4 2 >25A Push-Pull DC/DC Converter 4 i L L 4 5 kw a 1:1:n i 2 D 5 D 7 C R vo M in 1 M 2 b D 6 D 8 Simple non-isolated gate drives Suitable for low-voltage low-power applications Device sees twice input voltage need high voltage MOSFET High conduction voltage drop, low efficiency Center-tapped transformer Difficult to make low-voltage high-current terminations Prone to volt-second unbalance (saturation) JSL 7 v d 2 >25A M 1 M 3 a in M 2 M 4 Full-Bridge DC/DC Converter b 2 >25A i 1 1 : n i 2 D 5 D 6 D 7 D 8 i L v d L 4 5 kw C R vo Most popular circuit today for high-power applications Soft switching possible Reasonable device voltage ratings High component count from the look High conduction losses JSL 8

5 Device oltage and Current Stresses Device voltage stress Push-pull: 2% Half-bridge: 1% Full-bridge: 1% Device current stress Half-bridge: 2% Push-pull: 1% Full-bridge: 1% Output diode voltage stress Center tap: 2% Full-bridge: 1% JSL 9 Ripple Currents with Full-Bridge Converters 15A 5A -5A -15A 15A 1A 5A SEL>> -5A I(Ld3) I(Cin) (Iac) Filter inductor current AC load current Input capacitor current 33% 6A 4A 2A -I(fc) Source current Load step Load dump 33% 3 2 Source voltage 1 s 2ms 4ms 6ms 8ms 1ms (fc) JSL Time 1

6 Switching Waveforms with Full-Bridge Converter 1A 5A A -5A 15 A Ripple frequency = 1 khz -1A I(Cin) Zero-voltage switching is achieved (M1:d)-(M1:s) (M1:g)-(M1:s) 1A 75A 5A 25A SEL>> -25A 4.998ms 5.ms 5.2ms 5.4ms 5.6ms 5.8ms 5.1ms I(M1:d) I(M3:d) Time JSL 11 Fuel Cell or other voltage source v in C f A Three-Phase Bridge Converter S 3 S 5 A i A B S 4 S 6 S 2 C 3-phase bridge inverter 2 >167A i C 1 : n HF AC Xformer JSL 12 n D 1 i a D 4 a D 3 b D 6 D 5 c D 2 L C o RectifierLC filter Hard switching With 4 devices in parallel per switch Efficiency 95% i L vo Active Load

7 Source oltage and Current with 3-Phase Bridge Converter Case 15A 5A -5A -15A 15A 1A 5A A -5A 6A SEL>> 2A I(Ld3) -I(fc) (Iac) Filter inductor current AC load current A significant reduction in capacitor ripple current I(Cin) Input capacitor current No reduction in low-freq. source ripple current Source current Load step Load dump 8% 33% 3 2 Source voltage 1 s 5ms 1ms (fc) JSL 13 Time Switching Waveforms with 3-Phase Bridge Converter 5A 25A A 35 A SEL>> -5A I(Cin) 4 Ripple frequency = 3 khz Zero-voltage switching is achieved (M1:d)-(M1:s) (M1:g)-(M1:s) 1A 75A 5A 25A A -25A 4.998ms 5.ms 5.2ms 5.4ms 5.6ms 5.8ms 5.1ms I(M1:d) I(M4:d) Time JSL 14

8 Further Expansion to Six-Phase Bridge (6) Converter 2 >83A Source Active Load HF AC Xformer Six-phase bridge converter RectifierLC filter JSL 15 Key Feature of 6 DC-DC Converter Soft switching with zero-current turn-on and lagging leg zero-voltage turn-on (ZCZS) High efficiency operation over a wide load range with a peak efficiency of 98% Double output voltage with transformer connected in open -Y connection reduce turns ratio and associated leakage inductance Interleaved multiple phase operation to eliminate input high-frequency current ripple cost and size reduction on input capacitor C in Output DC link inductor L o current ripple elimination cost and size reduction on inductor Low-frequency (single-phase inverter load) ripple reduction with active dual-loop control better utilization of source energy and size and cost reduction on input capacitor C in Efficiency Input Power (W) A. in = 25 using custom-made commercial transformer B. in = 5 using custom-made commercial transformer C. in = 5 using in-house developed transformer JSL 16 99% 98% 97% 96% 95% 94% 93% 92% 91% C B A Commercial transformer Home-made transformer

9 Waveform Comparison between Full-Bridge and 6 Converters Full Bridge Converter 6 Converter v d i L v d i L Secondary inductor current is ripple-less; and in principle, no dc link inductor is needed Secondary voltage swing is eliminated with <4% voltage overshoot as compared to 25% JSL 17 Low-Frequency AC Current Ripple Problems 12Hz 6Hz Fuel Cell DC-DC converter dc A High-side cap. 12Hz S ap S bp B L f AC filter LC C f R o S an S bn Inverter AC current ripple propagates back to fuel cell Fuel cell requires a higher current handling capability Cost penalty to fuel cell stack Ripple current can cause hysteresis losses and subsequently more fuel consumption Cost penalty to fuel consumption State-of-the-art solutions are adding more capacitors or adding an external active filters Size and cost penalty The solution without cost penalty is to use existing 6 converter with active ripple cancellation technique to eliminate the ripple No penalty JSL 18

10 Active Ripple Cancellation Technique Adding a current loop to regulate the output current G vc G ic d = d in L f v ref R v1 R v2 C v1 C v2 i ref R i1 C i1 R i2 d PWM m d i Lf R cf C f R L o C i2 v sense i sense H i (a) Without ripple reduction v in (1/div) 2 avg i in (2A/div) 168A avg i L (1A/div) i ac (2A/div) 12.7A rms JSL 19 H v (b) With ripple reduction v in (1/div) 2 avg i in (2A/div) 162A avg i L (1A/div) i ac (2A/div) 12.7A rms 2. Energy Management Using Bidirectional DC/DC Converter DC Bus Fuel Cell, P, or H Battery DC/DC converter Inverter Load dc feedbacks ac I ac batt L battery or super capacitor Bidirectional dc/dc converter Low voltage battery or super capacitor controlling DC bus through a bidirectional dc/dc converter. The main application is to help start-up and transient conditions for E, HE, fuel cell PCS, etc. JSL 2

11 Circuit Diagram of a 4-Phase Bidirectional DC- DC Converter with Coupled Inductors u S 2u S 3u S 4u L 12 L 34 i 1 i 2 i 3 i 4 1 = 2 =18 3 =9 C high 4 =27 high low C low d S 2d S 3d S 4d Multiphase interleaved to reduce input and output capacitor current ripples Coupled inductors effectively increase the inductance or reduce the core size Hard or soft switching can be configured depending on inductor size and switching frequency JSL 21 Timing Diagram of 4-Phase Bidirectional DC-DC Converter complementary complementary complementary complementary u D D d S 2u S 2d S 3u S 3d S 4u S 4d T s /4 T s /2 T s kw, kw 2-4 JSL 22

12 Test Setup of a 1.5-kW Bidirectional DC-DC Converter Using Ultra-capacitor and ABC-15 I 1 I 2 Ultracapacitor Pack 1 Bidirectional DC/DC Converter 2 ABC-15 Channel 2 oltage Mode Test Computer (PC) Screw Terminal Connector Block Data Acquisition Card (NIDAQ) Remote Operating System Both channels alternate between sinking and sourcing current The magnitude of the current is based off of the power command given to the converter. JSL 23 Boost Mode : 1.5-kW Output Power Input oltage 36- Output oltage Output oltage 48- Input oltage Phase Current 1.42-A Command 1.5-kW Input Current Input Current A JSL 24

13 Experimental Results of Bidirectional Charging Mode Transition Operation In/Out oltages Output Current Output Current In/Out oltages Command Command Input Current Input Current JSL 25 Continuous and Discontinuous Conducting Modes (CCM and DCM) CCM operation i L high L low I pk low L i L DCM operation high L low I pk low L I avg I avg DT s T L 2 D' D T s Ts R 2 (1 D) s 2 2 CCM occurs with Larger inductance L Smaller R (heavy load) Higher switching frequency t R D 1 T s T L 2 D 2 T s D 3 T s 2 Ts D2 R (1 D1 ) 2 s 2 DCM occurs with Smaller inductance L Larger R (heavy load) Lower switching frequency JSL 26 R t

14 CCM-DCM Boundary Mode and Synchronous Conducting Mode (SCM) CCM-DCM Boundary operation i L high L low I pk low L SCM operation i L high L low I pk low L I avg I DT s D T s L low pk pk 1 low hi T DCM-CCM features Device turns on at zero current Device turns off at twice the average load current Applicable to any dc-dc converters s t Iavg I P I pk low pk low L 1 2 low SCM features Device turns on at zero voltage Device turns off at a current higher than twice the average Only applicable to bidirectional dc-dc converters hi T t s JSL 27 Simulated SCM Operated oltage and Current Waveforms at 5 khz Switching v gs v ds ds1-d =28 gs1-d =15 ZS >> -2 1 (M17:g) 2 (M17:d) 7A 6A 5 5A 4A i L3 i L2 i L4 3A 3 2A 1A 1 i L1 : 4 A pk-pk i L-all =57A average 16A pk-pk SEL>> 1-1A 9.95ms 9.96ms 9.97ms 9.98ms 9.99ms 1.ms I(RLa)-I(RLb)-I(RLc)-I(RLd) 1 -I(RLa) 2 -I(RLb) 3 -I(RLc) 4-I(RLd) Time 5 Time (µs) JSL 28

15 Experimental SCM Operated oltage and Current Waveforms at 5 khz Switching v gs-1d v ds-1d ZS D T s DT s i L-all =57A average i L1 i L3 i L2 i L4 16A pk-pk i L : 4 A pk-pk Time (5µs/div) JSL 29 Multiphase Bidirectional DC-DC Converter with Coupled Inductor and SCM Operation Similar to DCM operation, SCM has a high peak-to-peak inductor current. With multiphase interleaved, the current ripples cancel each other, and the total current can be significantly reduced. Device can switch at true zero voltage conduction, thus it is better to use power MOSFET as the switching device. Turn-off loss can be reduced with a paralleled capacitor (resonant capacitor) across the device. Coupled inductor allows core loss reduction and increases equivalent inductance. Overall efficiency can be very high with proper design of inductor and selection of device. JSL 3

16 Efficiency of Bidirectional DC-DC Converter Operating in Synchronous Conduction Mode Efficiency (%) 1.% 99.5% 99.% 98.5% 98.% 97.5% 97.% low = 24, high = 4 With 2-kHz frequency With 22-kHz frequency Power (kw) Use two identical 4-phase converters with regenerative connection to measure losses One converter operates in buck mode, and the other operates in boost mode The total supply power is the loss of two converters, but the output voltage and current are actual load condition. Measured peak efficiency exceeds 99.1% at 2 khz switching. JSL 31 Efficiency (%) Possible Efficiency Improvement with ariable Frequency Control 5kHz 4kHz 3kHz 2kHz 18kHz Power (W) If high efficiency at light load is desired, it is possible to vary the switching frequency. High frequency at light load allows much reduced peak current, thus increasing the efficiency. Experimental results showed that >99.2% at 5 khz switching was achieved. JSL 32

17 in in 3. High oltage Conversion Ratio Reboost Converters g g L L Q 1 1:n Flyback d Boost Q 1 s D 1 D 2 C C 1 2 L C 1 in D 2 1 n D 1 D o = C1 C2 Non-isolated output with high boost ratio Suitable for low input voltages such as fuel cells and solar cells Significant reduction on switch voltage stress JSL 33 g Q 1 1:n D 1 C 2 o in Reboost Converter Operating Modes 1:n D 1 1:n D 1 1:n D 1 1:n D 1 L M L lk1 L lk2 L M L lk1 L lk2 L M L lk1 in Co in Co in Co in D 2 Q o D D 2 o 2 1 Q o Q 1 1 Q 1 g g g g C 2 L M L lk1 L lk2 C 2 C 2 D 2 L lk2 C 2 o Co (a) (b) (c) (d) (a) (b) (c) (d) Initially, Q 1 is off, magnetizing inductor current continues circulating to supply the secondary current. The boost capacitor C 2 is discharging to output capacitor C o through diode D 1 and L lk2. D 2 is off. o = C2 n LM. Lk2 = n LM = n in. Current in L lk1 reflects the current in L lk2. Switch Q 1 turns on. With reverse biasing, current in D 1 starts reducing. L m is charged. oltage across L lk2 is Lk2 = n LM = o C2. Since LM = in, Lk2 = n in. Current in D 1 drops to. For non-ideal diodes, there will be a reverse recovery period. Capacitor C o has been charged by sum of voltage across L lk2 and C 2. o = C2 n in. Device Q 1 is fully turned on, and L m current is increasing. Switch turns off, diode D 2 is turned on, and C 2 gets charged. After C 2 is fully charged, diode D 2 will be turned off. Current in L k2 starts increasing until it reaches steady state. JSL 34

18 Derivation of oltage Conversion Ratio for the Reboost Converter Assume capacitors are large enough that their voltage maintains constant during steady-state operation. Also assume the transformer windings are perfectly coupled. During off period (Mode-a and Mode-d), s of L k2 is D Lk2. With s balance, D Lk2 = n D in. Thus Lk2 = n D in /D, and C2 = in /D. During on period (Mode-c), o = C2 n in. With constant C2, o C2 Lk 2 in 1 D 1 nd n D' D' D' in The voltage conversion ratio becomes o in 1 nd 1 D Actual voltage conversion ratio will be slightly lower with non-perfectly coupled transformer. JSL 35 oltage Conversion Ratio of Reboost DC-DC Converter oltage conversion ratio Duty cycle n=8 n=4 n=2 Reboost cases Boost converter case JSL 36

19 Further Derivation Recharged Boost Converter in g L 1 L 2 D 2 Q 1 C 2 D 1 C o (a) Reboost converter: Treat flyback as coupledinductor converter 1 n D 1 D o in L C 1 in D 2 g Q 1 1:n D 1 C 2 in g C 1 L 1 L 2 Q 1 D 2 C 2 D 3 D 1 C o (b) Recharged-boost converter: Add D 3 and C 1. when Q 1 turns on, C 1 is charged through D 3 and L 2. 2 n 1 D o in JSL 37 Basic Operating Principle of Recharge-Boost Converter (a) Initially, Q 1 is off, magnetizing inductor current charges boost capacitor C 2 through diode D 2 and output capacitor C o through C 1, L 2, and D 1. D 3 is off. o = in Lm C1 n Lm. C2 = in Lm. L2 = n Lm. Current in L 1 reflects the current in L 2. (b) Switch Q 1 turns on. D 2 is turned off. L m is charged. oltage across L 2 is L2 = n Lm = o C1. Since Lm = in, L2 = n in. With reverse biasing, current in D 1 starts reducing. (c) Current in D 1 drops to. For non-ideal diodes, there will be a reverse recovery period. Capacitor C 1 is charged by sum of voltage across L 2 and C 2. C1 = C2 n in. Device Q 1 is fully turned on, and L m current is increasing. (d) Switch turns off, diode D 2 is turned on, and C 2 gets charged with C2 = in Lm. D 3 is now reverse-biased, and its current starts reducing. Current in L 2 starts reversing until it reaches. There will be a reverse recovery period due to non-ideal D 3. After that, the mode returns to Mode (a). L k1 1:n L k2 D 1 L k1 1:n L k2 D 1 L k1 1:n L k2 D 1 L k1 1:n L k2 D 1 in L m Q 1 L 1 L 2 C 1 D 3 C o o D 2 C 2 in Q 1 L m L 1 C 1 L 2 D 3 C o o D 2 C2 in Q 1 L m L 2 L 1 C in 1 C D o 3 o D 2 C2 Q 1 L m L 1 L 2 C 1 C D o 3 o D 2 C 2 (a) (b) (c) (d) JSL 38

20 Derivation of oltage Conversion Ratio Assume capacitors are large enough that their voltage maintains constant during steady-state operation. Also assume the transformer windings are perfectly coupled. During off period (Mode-a and Mode-d), s of L 2 is D L2. With s balance, D L2 = n D in. Thus L2 = n D in /D, and Lm = D in /D C2 = in D in /D = (1D/D ) in = in /D. During on period (Mode-c), C1 = C2 n in. With constant C2, C1 = (1/D n) in. Again with C1 being constant, under Mode-a condition, we have 1 1 D 2 n o C 2 C1 L2 in ( n) n in D' D' D' D' D' boost The voltage conversion ratio becomes recharge 2 n 1 D Actual voltage conversion ratio will be slightly lower with non-perfectly coupled transformer. JSL 39 o in flyback in Q 1 L k1 L m C 1 1:n L 1 L 2 L k2 D 3 D 1 C o o D 2 C2 oltage conversion ratio oltage Conversion of Recharged Boost Converter Duty cycle Recharge boost case with n=8 Reboost case with n=8 Recharge boost case with n=4 Reboost case with n=4 Recharge boost case with n=2 Reboost case with n=2 Boost converter case JSL 4

21 in Key oltage and Current Waveforms of Recharged- Boost Converter Q 1 L k1 L m 1:n L 1 L 2 C 1 L k2 D 3 D 1 C o o D 2 C2 > > A A A A (TX1:1)-(TX1:2) I(D3) o c1 I(D1) L2 L1 I D3 I D1 (TX1:4)-(TX1:3) Slow turn-off of D 1 and D 3 shows problem of reverse recovery (SiC Schottky diodes may be used). With limited duty cycle range, C 2 voltage can be limited, and Si Schottky can be used for D 2. With large enough capacitors, voltages of capacitors are flat during steady-state operation. 5.98ms 5.984ms 5.988ms 5.991ms JSL 41 A A A A (y)-(x) (c) (o) (M1:g) Q1 I L1 gs (M1:d) I L2 c2 I Lm Design Examples with High Boost Ratio DC-DC Converters Boost converter Inverter Boost converter Reboost converter Recharge boost converter P array L 1 Q 1 D 1 filter L 1 L 2 D 1 C 1 L 1 L 2 D 1 in g Q 1 D 2 C 2 C o in g Q 1 D 2 C 2 D 3 C o Reboost converter Recharge boost converter JSL 42

22 oltage Conversion Ratio and Duty Cycle Constraint At 1, G v = 2/1 = 2, at 2, G v = 1 At 6, G v = 2/6 = 3.33, 7, G v = 2/7 = 2.86 Assume duty cycle is limited to between.1 and.9 For boost converter case, D at 1 needs to be.95 (difficult to implement) The reboost converter with n = 8 case has the best suitable duty cycle range for the wide input voltage range case. For recharge-boost converter with n =.58 case, D at 7 needs to be.1, not effective utilization of the switch. Duty cycle at different P voltages P input Boost Reboost (n = 8) Recharge boost (n =.58) JSL 43 Duty Cycle Comparison Between Boost and Reboost, and Recharge-Boost Converters oltage gain recharge boost with n =.58 reboost with n = Duty Duty cycle range Boost:.65 at 7 to.95 at 1 Reboost:.17 at 7 to.68 at 1 Recharge boost:.1 at 7 to.87 at 1 boost converter Boost needs to be excluded due to duty cycle constraint. Recharge boost works in theory, but fails in actual implementation at 1. JSL 44

23 Switch Q 1 oltage Stresses in in g g L 1 L 2 D 1 Q 1 voltage stress is the voltage across C 2 and can be calculated as the boost converter output. Q 1 D 2 1 C o o C 2 in 1 D C 1 L 1 L 2 Q 1 C 2 D 2 C 2 D 3 D 1 C o o a. For boost case, At 1 input, D =.95, C2 = 2, At 7 input, D =.21, C2 = 2, b. For reboost case with n = 8, At 1 input, D =.68, C2 = 31, At 7 input, D =.17, C2 = 84, c. For recharge boost case with n =.6, At 1 input, D =.87, C2 = 78, At 7 input, D =.1, C2 = 78, Both reboost and recharge-boost can be designed to maintain the voltage stress of C 2 to below 1. JSL 45 Turns Ratio versus oltage Stress for the Reboost Case Higher turns ratio, less voltage stress on switch, clamping diode, and clamping capacitor, but higher voltage stress on output diode and more transformer leakage inductance. Assume o = 2, in_max = 7, and clamp_max = in_max /(1 D) = 85 o 1 nd 1 D in 1 nd 1 D o in in clamp n 1 D 1 D 1 D o clamp n 7.66 clamp in clamp in Assume output diode D 1 stress is limited to 7 d 1 o clamp n 8.36 d1 o clamp nin in Therefore, n = 8 should allow reasonable device voltage stress (85 ) and clamping diode voltage stress (7 ). JSL 46 in 1 n 1 D in clamp n in n clamp

24 Simulation results of oltage stress (a) Switch voltage (b) Output diode voltage With turns ratio n = 8, in = 7, o = 2, simulation results agree with the calculated voltage stress of active device and output diode. Device voltage has small overshoot during turn-off. Additional margin is needed. JSL 47 5A Simulated oltages and Device Current at 7- Input, 1-kHz Switching 25A A 1 I(M1:d) Device current 19 A 44 A I(M1:d) 5 2 SEL>> 85 8 (M1:d) Time (µs) (a) Reboost Device voltage > (M1:d) Output voltage 2 C 2 voltage Time (µs) (b) Recharge boost 4 5 Simulation results match the calculated results Device voltage stress is nearly the same, but the current stress in recharge boost is much higher due to smaller duty cycle JSL 48

25 Diode Current Stresses for Reboost Converter Assume capacitors and magnetizing inductance are large enough that capacitor voltages and magnetizing current maintain constant throughout the entire steady-state cycle. Average output current I o = P o / o = 3/2 = 1.5 A At 2- input, the average input current I in = 3/2 = 15 A With duty cycle D =.5, the primary switch current is I Q1 = I in /D = 22.5 A. The output diode current during switch turn-off period is I D1 = I o /D = 3 A I(M1:d) I I(D2) I(Cc) C2 I(D1) 3 I LM 2 1 I Lk Time (µs) Diode D 2 conducts when the switch is turned off but only in a very short period to charge the capacitor C 2. The peak current of D 2 is the peak switch current, or I D2-peak = I sw-peak, but the average I D2 is very small. JSL 49 I Q1 I D1 I D2 Two Phases Interleaved Recharge Boost Converter L 11 C r1 L 12 D o1 in C i Q 1 D c1 C c1 D r1 C o o L 21 C r2 L 22 D o2 D c2 D r2 Q 2 C c2 Multiphase interleaved operation allows ripple reduction Current sharing among phases is good for high power applications JSL 5

26 Two-phase Interleaved Recharge Boost Converter with Cross Coupling L 11 C r1 L 12 L 23 D o1 in C i Q 1 D c1 C c1 D r1 C o o L 21 C r2 L 22 L 13 D o2 Q 2 D c2 C c2 D r2 Cross coupling helps balance equal current sharing JSL 51 Summary of State-of-the-Art High Boost Ratio DC-DC Converters Conventional boost converter simply cannot be considered as a high boost ratio converter. Reboost converter: Requires high turns ratio for high boost ratio and low device voltage stress. High turns ratio tends to increase output diode voltage stress and lower device utilization. Recharge boost converter: Super high boost ratio with low turns ratio Relatively low device voltage stress Difficulty to operate in a wide range input voltage due to duty cycle constraint at low input voltages High peak current stress on switch when operating at high input voltage where duty cycle is low JSL 52

27 in in g g Q 1 Q 1 Charge Pump Reboost Converter C 1 L 1 L 2 D 2 C 2 C 1 L 1 L 2 D 2 C 2 D 3 D 3 D 1 C o D 1 C o A new improved high boost ratio dc-dc converter is proposed using charge pump idea oltage boost ratio is reduced to allow a wider input voltage range while maintaining reasonable voltage stresses on devices Direct charge pump allows L2 current to be regulated to avoid low-frequency ripple propagation back to the source JSL 53 2 n 1 D o in o 2 nd 1 D o in Basic Operation of the Charge Pump Reboost Converter (a) Initially, Q 1 is off, magnetizing inductor current charges output capacitor C o through C 1, L 2, and D 1. D 2 and D 3 are off. o = in Lm C1 n Lm. C2 = in Lm. L2 = n Lm. Current in L 1 reflects the current in L 2. (b) Switch Q 1 turns on. D 2 is turned off. L m is charged. oltage across L 2 is L2 = n Lm = o C1. Since Lm = in, L2 = n in. With reverse biasing, current in D 1 starts reducing. (c) Current in D 1 drops to. For non-ideal diodes, there will be a reverse recovery period. Capacitor C 1 is charged by C 2, so C1 = C2. Device Q 1 is fully turned on, and L m current is increasing. (d) Switch turns off, diode D 2 is turned on, and C 2 gets charged with C2 = in Lm. D 3 is now reverse-biased, and its current starts reducing. There will be a reverse recovery period due to non-ideal D 3. After C 2 is fully charged, the mode returns to Mode (a). L k1 1:n L k2 D 1 L k1 1:n L k2 D 1 L k1 1:n L k2 D 1 L k1 1:n L k2 D 1 in Q 1 L m L 1 L 2 L m L 1 L 2 L m L 1 L 2 L m L 1 L 2 in in in C C 1 D o 3 o C C 1 D o 3 C C C 1 o o C 1 D o D o 3 3 Q D 1 Q 1 Q 1 2 D 2 D 2 C2 C 2 C 2 D 2 C 2 o (a) (b) (c) (d) JSL 54

28 oltage Conversion Ratio of Charge Pump Reboost Converter Assume capacitors are large enough that their voltage maintains constant during steady-state operation. Also assume the transformer windings are perfectly coupled. During off period (Mode-a and Mode-d), s of L 2 is D L2. With s balance, D L2 = n D in. Thus L2 = n D in /D, and Lm = D in /D C2 = in D in /D = (1D/D ) in = in /D. During on period (Mode-c), C1 = C2 = in /D. Under Mode-d condition, we have o C 2 C1 L2 in 1 D' 1 D' D n D' in 2 nd D' D' boost charge pump flyback o 2 nd The voltage conversion ratio becomes in 1 D Actual voltage conversion ratio will be slightly lower with non-perfectly coupled transformer. JSL 55 oltage Conversion Ratio and Duty Cycle Comparison oltage gain recharge boost with n =.58 reboost with n = Charge-pump re-boost 2 converter n = Duty cycle range Duty Reboost:.17 at 7 to.68 at 1 Recharge boost:.1 at 7 to.88 at 1 Charge pump reboost:.16 at 7 to.8 at 1 (most suitable range) JSL 56

29 Measured and Calculated oltage Conversion Ratio oltage Gain (o / in) Measured Gain Predicted Gain calculated measured Duty Cycle (%) Measured voltage conversion ratio matches calculated one very well. JSL 57 Measured Charge-Pump Reboost Converter Efficiency at Different oltages Efficiency % T test results with 1 FET, o = 2, 85kHz, n = % of rated load, 1% = 3W JSL 58

30 Recap of Part A A multiphase isolated DC-DC converter with peak efficiency of 98% and significant reduction on high-frequency ripples, thus allowing small-size, low-cost passive components to be used. Low-frequency ripple is a major issue in maximum energy harness. An active cancellation technique was presented. Super high efficiency (>99%) can be achieved with bidirectional dc-dc converter operating in synchronous conducting mode. Different high boost ratio dc-dc converter circuits were presented to show how to design low-cost and high-efficiency converters for renewable energy such as solar panel integration applications. JSL 59 Half-Time Break? JSL 6

31 Outline Part B Part A High Efficiency DC-DC Converters 1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter 3. High Boost Ratio DC-DC Converters Part B High Efficiency Inverters 1. Half-Cycle Asymmetrical Unipolar PWM 2. Single-Stage Power Conversion 3. Dual Buck Converters 4. H5 Inverter 5. Isolated Single-Stage Design 6. Soft-Switching Inverters Part C Energy Efficiency Standards JSL 61 Outline Part B-1 Part A High Efficiency DC-DC Converters 1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter 3. High Boost Ratio DC-DC Converters Part B High Efficiency Inverters 1. Half-Cycle Asymmetrical Unipolar PWM 2. Single-Stage Power Conversion 3. Dual Buck Converters 4. H5 Inverter 5. Isolated Single-Stage Design 6. Soft-Switching Inverters Part C Energy Efficiency Standards JSL 62

32 A Full-Bridge Inverter Circuit JSL 63 Bipolar Sinusoidal PWM Method c : carrier wave v ref : reference voltage, S 4 S 2, S 3 v ab v o time Algorithm: If v ref >v c, turn on upper device; otherwise, turn on lower device. If upper device is on then v a = v dc,; otherwise, v a =. v an = v a v dc /2; JSL 64

33 Unipolar (Dual) Sinusoidal PWM Method v c v ref-a v ref-b S 2 S 3 S 4 v ab time JSL 65 Detailed Waveforms of Unipolar PWM ref-a T s ref-b v a v b dc dc dc v ab Switching frequency effectively doubled JSL dc 66

34 PWM Methods in Multi-Stage and Single-Stage Power Conversions For dc voltage higher than the peak of ac output voltage, a simple dcac inverter can be used. However, for dc voltage lower than the peak of ac output voltage, multiple-stage (multiple high-frequency PWM stages) power conversion is needed to obtain the desired ac voltage. It is possible to convert low-voltage dc to high-voltage ac with a single PWM stage dc-dc converter to obtain high-voltage dc and a polarity selection stage to obtain high-voltage ac. dc ac in HF PWM DC/AC HF Xformer High-frequency transformer AC/DC HF SPWM DC/AC High-frequency switching DC/AC inverter (a) Multi-stage power conversion ac in HF PWM DC/AC Xformer AC/DC LF Distribution DC/AC (b) Single-stage power conversion JSL High-frequency Low-frequency 67 transformer polarity selection A Typical Multi-Stage Power Conversion Using oltage Source Push-Pull DC-DC Converter and oltage Source Full-Bridge DC-AC Inverter DC-DC converter dc/ac inverter P array filter ac output Use voltage source type push-pull dc/dc converter to boost voltage Entire module can operate independently with one P array input and one ac output Multiple ac module outputs can be parallel-connected to utility line JSL 68

35 A Typical Multi-Stage Power Conversion Using Current Source Push-Pull DC-DC Converter and oltage Source Full-Bridge DC-AC Inverter push-pull boost converter dc/ac inverter P array dc filter ac output Use current source type push-pull dc/dc converter to boost voltage Entire module can operate independently with one P array input and one ac output Multiple ac module outputs can be parallel-connected to utility line JSL 69 Single-Stage Inverter with Isolated Converter and a Matrix Converter for Low-oltage P Systems matrix converter filter ac in HF PWM DC/AC Xformer ac output High-frequency transformer Low-voltage converter implements PWM Transformer converts high-frequency low-voltage PWM to high voltage A matrix converter or cycloconverter converts high-frequency ac to low-frequency ac JSL 7

36 2. Basic Single-Stage Design Idea A DC-DC Buck Converter AC Selection Bridge ac dc Filter Buck stage LF distribution AC selection network Features: High input voltage level Buck converter produces rectified SPWM Low frequency selection network produces ac SPWM output Use power MOSFET as the buck switch to reduce switching loss Use IGBT or thyristor as the low-frequency ac selection switch to avoid reverse recovery loss JSL 71 Basic Operating Modes of Buck Switch S 5 S 3 S 3 S 5 S 5, S 4 S 2, S 3 S 2 S 4 S 2 S 4 v o (a) Positive cycle &S 4 on,s 5 on (b) Positive cycle &S 4 on,s 5 off, freewheeling S 3 S 3 S S 5 5 S 2 S 4 S 2 S 4 S 5 is half-wave symmetrical PWM operated Positive cycle, and S 4 are always on Negative cycle, S 2 and S 3 are always on (c) Negative cycle S 2 &S 3 on, M 1 on (d) Negative cycle S 2 &S 3 on, M 1 off, freewheeling JSL 72

37 3. Dual Buck Type Inverter i 1 i 2 v o i o Load SEL>> -2A 5ms Features: Use power MOSFET to reduce turn-off loss Use ultrafast reverse recovery diode to reduce turn-on loss No dead time and shoot-through concerns The only issue is power flow is unidirectional, and the output current must be in phase with the output voltage (reactive power output tends to have distorted current waveform) JSL A 1A A -1A -2A 2A 1A A (al) I(RL) i 2 v o i o i 1 6ms 8ms 1ms I(RLa) I(RLb) Time Dual Buck Inverter with Dual Outputs i 1 i a i 2 Load1 Load3 i 3 Load2 i 4 JSL 74

38 Dual Boost and Dual Buck-Boost Inverters L 1 C C dc1 i L dc1 L 1 i L R v o R v o dc2 L 2 C dc2 L 2 C (a) Double Boost Inverter (b) Double Buck-Boost Inverter Use power MOSFET to reduce turn-off loss Use ultrafast reverse recovery diode to reduce turn-on loss No dead time and shoot-through concerns JSL 75 Asymmetrical Half-Cycle Unipolar PWM S 3 S 3 S 4 S 3 S 2 S 2 S 4 S 2 S 4 (a) Positive cycle SPWM, S 4 is always on v o S 2 S 3 S 3 S 4 S 2 (b) Negative cycle S 3 SPWM, S 2 is always on JSL 76 S 4 Split previous buck switch S 5 into two PWM operated buck switches, and S 3 Positive cycle, S 4 is always on, runs in SPWM Negative cycle, S 2 is always on, S 3 runs in SPWM

39 4. Asymmetrical Half-Cycle Unipolar PWM Inverter with 5 Switches (H5 TM Inverter) SPWM Buck stage LF selection S 3 ac S 3 S 5 dc S 6 S 2 S 4 Filter Features: Buck switch S 5 produces rectified SPWM IGBT s and S 3 serve as low frequency selection network MOSFET S 2 operates in SPWM on negative cycle MOSFET S 4 operates in SPWM on positive cycle Use fast recovery diode for and S 3 to reduce reverse recovery loss S 5 and S 2 or S 4 share half the DC bus voltage, allowing low-voltage switches to be used in high voltage input JSL 77 Operating Modes of H5 TM Inverter S 5 S 5 S 2 S 2 S 5 S 4 S 3 S 4 S 3 S 4 S 3 (a) Positive cycle, S 4 &S 5 on (b) Positive cycle on,s 4 and S 5 off, freewheeling S 2 v o S 2 S 2 S S 5 5 S 3 S 4 S 3 S 4 (c) Negative cycle S 3, S 2 &S 5 on (d) Negative cycle S 2 on, S 3 and S 5 off, freewheeling JSL 78

40 Measured Gate Signals and Output oltage Waveforms S 3 AC voltage (1 /div) S 5 S 4 Experimental results verify the basic operation. JSL 79 Measured H5 Inverter Efficiency Efficiency Input: 42 Output: Power (kw) Use 2 CoolMOS parallel for S 5 and S 6. They are resistive element, so efficiency is high in low power region. Use slow IGBT but ultra fast diode, which can be replaced with SiC Schottky diode to further reduce the MOSFET turn-on loss. JSL 8

41 5. Isolated Single-Stage Design ac in HF PWM DC/AC Xformer AC/DC LF Distribution DC/AC High-frequency transformer Low-frequency switching inverter Low-voltage inverter implements symmetrical sinusoidal PWM Transformer converts high-frequency SPWM to high voltage Rectifier converts symmetrical SPWM to rectified SPWM Low-frequency inverter selects the positive and negative cycles, same as the non-isolated version JSL 81 Enphase Active-Clamp Flyback Inverter D 2 Q 1 Q 3 S x2 S 2 D 1 Q5 Q 2 Q 4 S x1 Interleaved flyback converters serve as single-stage power conversion. MOSFET and S 2 are the main switches. S x1 and S x2 are auxiliary switches for active clamp. Q 1, Q 2, Q 3, and Q 4 thyristors serve as polarity selection switches. Q 1 and Q 3 turn on during positive cycle. Q 2 and Q 4 turn on during negative cycle. Q 5 helps commutate thyristors under low dc bus voltage condition. JSL 82

42 Measured Efficiency of Enphase Inverter Efficiency Power (W) Use SiCSchottkydiode for D 1 and D 2 to reduce reverse recovery loss Use low voltage drop thyristors as the polarity selection switch and block reverse (high) voltage from utility Use low conduction voltage drop CoolMOS Q 5 to help turn off thyristors at low voltage or zero voltage crossing. JSL 83 Features of Single-Stage Power Conversion Reduced power conversion stages with only one PWM stage needed, potentially low cost High efficiency due to reduced PWM operation Low frequency ripple propagates back to source without any buffer A large capacitor bank is needed at the source to ensure maximum power tracking JSL 84

43 6. Soft-Switching Inverters Soft-Switching Basics Zero-oltage Switching Type Soft-Switching Inverters Resonant Snubber Inverter Coupled-Magnetic Type Zero-oltage Switching Inverter JSL 85 Issues with Device Switching Problems associated with conventional hard switching High switching losses Poor efficiency High dv/dt and di/dt Issues with Electromagnetic inference (EMI) Major switching losses Diode reverse recovery induced turnon loss IGBT turn-off tail current induced turnoff loss Soft switching methods Zero voltage switching (during turn-on) Zero current switching (during turn-off) device voltage device current device power loss turn-on conduction turn-off Waveforms Showing Device Switching Behaviors JSL 86

44 dc What s Relationship Between Snubber and Soft- L lk L s C s I o Switching? The traditional snubber uses L s to limit the turn-on current rise and C s to limit the turn-off voltage rise. Device losses were reduced, but the snubber losses were significant. Here are some formula for loss estimation. Snubber loss 2 o (2Ls Llk ) I Ps 2 2 s dc 3C f s C s L s Turn-on loss Turn-off loss 2 2 dc tr JSL 87 P P on off 24(2L L ) 2 o 2 f I t 24C Soft-switching is to do the same job that limits the current rise and voltage rise, but at the same time, to avoid the loss incurred in the snubbers. s s f s lk f s Categories of Zero-oltage Soft-Switching Inverters Resonant DC Link Ordinary Resonant Dc Link Active-Clamp Resonant dc Link Quasi-Resonant Dc Link DC Rail Zero-oltage Transition Resonant Pole Ordinary Resonant Pole Clamp Mode Resonant Pole (CMRP) Auxiliary Switched Resonant Snubber Auxiliary Resonant Commutated Pole (ARCP) Magnetic Coupled Zero- oltage Transition Y-Configured Resonant Snubber Inverter (Y-RSI) -Configured Resonant Snubber Inverter ( -RSI) Not easy to achieve 99% efficiency cost effectively JSL 88

45 Auxiliary Resonant Commutated Pole (ARCP) Inverter C sp Sa S1 C 1 S3 C 3 S5 L ra C 5 s Lrb Sb L rc ac motor C sn Sc S4 C 4 S6 C 6 S2 C 2 R. DeDoncker, 1991 Features: Standard PWM applicable Auxiliary switch sees half dc bus voltage Small size resonant components Disadvantages: Extra bulk energy storage capacitors Unbalanced capacitor voltages Need complicated control for zerovoltage switching JSL 89 Single-Phase Resonant Snubber Soft- Switching Inverter with One Inductor D 1 C 1 S 3 D 3 C 3 dc I S1 I S3 a L r R o I o L o I Lr1 D r1 S r1 D 2 D 4 b I S2 I S4 S 2 C S C I Lr2 S r2 D r2 JSL 9

46 Operation Modes of the Single-Phase Resonant Snubber Soft Switching Inverter L r1 D r1 S r1 S 3 I Lr2 I o dc R o I o L o I S3 I S1,4 S 2 S 4 L r2 S r2 D r2 I S2,3 dc Mode : t ~ t 1 L r1 D r1 S r1 R o I o L o S 3 I S3 I C1,4 I C2,3 I C2,3 S 2,3 I C1,4,4 S r2 t t 1 t 2 t 3 t 4 t 5 t 6 I Lr2 S 2 S 4 L r2 Sr2 D r2 Mode 1: t 1 ~ t 2 JSL 91 Operation Modes of the Single-Phase Resonant Snubber Soft Switching Inverter L r1 D r1 S r1 S 3 I Lr2 dc R o I o L o I S3 I o I Lr2 S 2 S 4 L r2 S r2 D r2 I S1,4 Mode 2: t 2 ~ t 3 I S2,3 dc L r1 R o D r1 I o S r1 L o S 3 I S3 I C1,4 I C2,3 I C2,3 S 2,3 I C1,4,4 S r2 I Lr2 t t 1 t 2 t 3 t 4 t 5 t 6 S 2 S 4 L r2 S r2 D r2 Mode 3: t 3 ~ t 4 JSL 92

47 Operation Modes of the Single-Phase Resonant Snubber Soft Switching Inverter L r1 D r1 S r1 S 3 I Lr2 dc R o I o L o I o I Lr2 I S4 S 2 S 4 L r2 S r2 Mode 4: t 4 ~ t 5 D r2 I S2,3 I S1,4 dc L r1 R o D r1 I o S r1 L o S 3 I C1,4 I C2,3 I C2,3 S 2,3 I C1,4,4 S r2 I S4 t t 1 t 2 t 3 t 4 t 5 t 6 S 2 S 4 L r2 S r2 D r2 Mode 5: t 5 ~ t 6 JSL 93 Power Circuit of 3-Phase Couple-Magnetic Soft-Switching Inverter S x1 S x3 S x5 S 3 S 5 C 1 L ra C 3 C 5 s C s L rb L rc ac motor S x4 S x6 S x2 S 4 S 6 S 2 C 4 C 6 C 2 Distinct design features: 1. Make turns ratio 1:n with n>1 to ensure zero-voltage switching for a wide range operation 2. Fix delay timing control to simplify controller design JSL 94

48 Single-Phase Test Circuit and Basic Operation S x1 D x1 n C1 CE1 S x1 S 2 S x2 t dt t dt dc 1 L r I Lr I o L o Load t dly i Lr i Load t dly S x2 D x2 S 2 t dt : dead time from DSP controller (e.g. 2µs) t dly : delay time (e.g. 1.5µs) t x = t dt t dly =.5µs I 1 dc JSL t 95 t 1 t 2 t 3 t 4 t 5 C 2 Load r1 t dc L I L 2 Load r 2 t i C2 i C1 i D1 v CE1 i S1 v CE2 Illustration of Soft-Switching Operation (a) S x1 D x1 C 1 (b) S x1 D x1 C 1 L r2 L r2 dc I Load dc I Load L r1 L r1 S x2 D x2 S 2 C 2 S x2 D x2 S 2 C 2 (c) S x1 D x1 C 1 (d) S x1 D x1 C 1 L r2 L r2 dc I Load dc I Load L r1 L r1 S x2 D x2 S 2 C 2 S x2 D x2 S 2 C 2 JSL 96

49 Soft-Switching Operation (cont d) (e) (f) S x1 D x1 C 1 S x1 D x1 C 1 L r2 L r2 dc I Load dc I Load L r1 L r1 S x2 D x2 S 2 C 2 S x2 D x2 S 2 C 2 JSL 97 Inverter Photo Showing DC Bus Capacitor and Coupled Magnetic Connections Resonant inductor Saturable inductor DC bus bar DSP interface JSL 98

50 Experimental erification in One Resonant Cycle 2A 175A 15A t(.5µs/div) i Lr v GE (2/div) 125A 1A 75A i Lr1 I Load I Load (1A/div) i Lr (1A/div) 5A 25A i Lr2 v CE (2/div) A -25A t (.5µs/div) JSL 99 Experimental Results of Inverter Operation at 3- Bus 69-A Load Current v GE (2/div) i Lr (1A/div) I Load (1A/div) t(5µs/div) v CE (2/div) JSL 1

51 Efficiency Test Results with 1-kW Compressor Efficiency 1% 99% 98% 97% 96% 95% 94% 93% 92% 91% 9% Inverter Input Power (kw) JSL 11 Efficiency Test Results with a 5-kW Adaptive Timing Zero-oltage Switching Inverter Efficiency (%) 99% 98% 97% 96% 95% 94% 93% 92% 91% Adaptive timing soft switching Hard switching Fixed timing soft switching Output Power (kw) DC bus capacitors Resonant capacitors DSP board Resonant inductors AC output DC input Fixed timing shows poor light load efficiency, worse than hard-switching case At 2% load (1-kW), the efficiency improvement with variable timing is >3%. High power output (>4.5 kw), the efficiency difference becomes less visible but both soft switching shows better efficiency than hard switching case JSL 12

52 Features of the Auxiliary Commutated Resonant Snubber Inverters Main switches turn on at zero voltage or under their anti-parallel diodes conducting condition; Main switches turn off at a slower dv/dt rate and lossless snubbing condition; Main switches do not have over-voltage or over-current stress; Auxiliary switches conduct only in a short period as compared to the PWM cycle; Auxiliary switches turn on and off under zero current condition; Auxiliary switches need to carry high peak current, typically higher than the rated load current; Free wheeling diodes across the main switches do not have reverse recovery problems because their currents are diverted by the auxiliary resonant circuitry; Auxiliary circuit diodes need to have very fast reverse recovery characteristic to prevent the resonant current from oscillation when it is swinging down across the zero point. JSL 13 Recap for Part B For energy applications, single-stage inverters have been actively studied and extended to different variations of highefficiency inverter. High efficiency commercial inverters (SMA and Enphase) are introduced. Dual buck, dual boost, and dual buck-boost inverters show potential for high efficiency operation. Soft-switching shows efficiency >99% for 3-phase high-power motor drives and >98% for 1-phase 5-kW grid-tie inverter. JSL 14

53 Outline Part C Part A High Efficiency DC-DC Converters 1. High-Efficiency Low-Ripple Isolated DC-DC Converter 2. Energy Management Using Bidirectional DC/DC Converter 3. High Boost Ratio DC-DC Converters Part B High Efficiency Inverters 1. Half-Cycle Asymmetrical Unipolar PWM 2. Single-Stage Power Conversion 3. Dual Buck Converters 4. H5 Inverter 5. Isolated Single-Stage Design 6. Soft-Switching Inverters Part C Energy Efficiency Standards JSL 15 Part C. Energy Efficiency Standards California Energy Commission (CEC) IEC 61683:1999, First Edition, , Photovoltaic systems Power conditioners Procedures for measuring efficiency. JSL 16

54 Efficiency of Alternative Energy Inverters California Energy Commission (CEC) All inverters must meet the requirements in EMERGING RENEWABLES EMERGING RENEWABLES PROGRAM, Final Guidebook, Eighth Edition, Section C Inverters. There are no set minimum requirements, but the conversion efficiency must be tested and reported to CEC - as defined here. JSL 17 IEC 61683:1999, Photovoltaic Systems Power Conditioners Procedure for Measuring Efficiency This standard describes guidelines for measuring the efficiency of power conditioners used in standalone and utility-interactive photovoltaic systems, where the output of the power conditioner is a stable systems, where the output of the power conditioner is a stable ac voltage of constant frequency or a stable dc voltage. The efficiency is calculated from a direct measurement of input and output power in the factory. An isolation transformer is included where it is applicable. China: GB/T is based on IEC 61683:1999 JSL 18

55 CEC and IEC Weighted Efficiency Measurement 5% 1% 2% 3% 5% 75% 1% CEC IEC JSL 19 Example Efficiency Measurement Results (A High-Boost Ratio DC-DC Converter Example) JSL 11

56 Measured and Weighted Efficiency Plots JSL 111 Summary of Power Electronics Design for Energy Efficiency at Different Levels System level Solar Magic TM, single-stage design Circuit topology soft switching converter/inverter, dual buck inverter, multilevel converter Modulation scheme phase-shift modulation, synchronous conduction mode Power device SiC diode, CoolMOS, hybrid switch Combination of above H5 inverters Control strategy maximum T/A and maximum efficiency for motor drives JSL 112

57 Recap High-efficiency and high-performance dc-dc converters were discussed in three categories: multiphase isolated dc-dc, bidirectional dc-dc, and high-boost ratio dc-dc converters. High-efficiency dc-ac inverters were introduced in three categories: Dual buck, dual boost, and dual buck-boost inverters, Single-stage inverter for potential high-efficiency and lowcost design Soft-switching inverters show promising efficiency for both motor drive and energy applications. Efficiency standards in US and Europe are introduced to show how to calculate weighted PCS efficiency. JSL 113? JSL 114