Soft-Switching in DC-DC Converters: Principles, Practical Topologies, Design Techniques, Latest Developments

Transcription

1 Soft-Switching in D-D onverters: Principles, Practical Topologies, Design Techniques, Latest Developments Raja Ayyanar Arizona State University Ned Mohan University of Minnesota Eric Persson International Rectifier Some of the slides in this presentation are used for the course EE5741 Advanced Power Electronics given by Prof Robbins and Prof Mohan at the University of Minnesota 22, N. Mohan, R. Ayyanar, E. Persson APE 22 1

2 Objectives What is soft-switching? Basic principles oncentration on a few popular topologies Design techniques omputer simulations New developments 2

3 What is Soft-Switching Switching transitions occur under favorable conditions device voltage or current is zero Reduced switching losses, switch stress, possibly low EMI, easier thermal management A must for very high frequency operation, (also medium frequency at high power levels) Usually involves compromises in conduction loss, switch rating, passive components etc. 4

4 Relationship Between Efficiency and Power Density 5 45 Power Rating Ploss = 2W Ploss = 1W Efficiency η = P out Pout P loss η Pout = P 1 η loss 5

5 Hard-Switching i i T L i L v T - V d - v diode i I L o v gate v T i diode i T v diode P loss P f t t sw s c( on) c( off ) 6

6 MOSFET haracteristics Output characteristics ross-sectional view of an n-channel MOSFET source gate n gs p p n gd Transfer characteristics ds n drain-body depletion layer n drain 7

7 MOSFET haracteristics D f I o V in gd i D = ( gs) f V R G V GG gs MOSFET model valid in active and cutoff regions Variation of capacitances with Vds 8

8 Simulation of Hard Switching onverters L2 4nH D2 1A I3 8 R3 1m 5V V1 R2 25. M1 IRF15 Ideal diode IRF15 2 v DS 1 v GS i D gate input -1 s.5us 1.us 1.5us 2.us 2.5us 3.us 3.5us 4.us V(M1:d)/4 ID(M1)*2 V(R2:2) V(V3:) Time 9

9 Simulation of Hard Switching onverters Diode reverse recovery 55 4 v ds PARAMETERS: R_LOAD = 1 fs = 1k MUR22R 5A D5 I1 2 v gs 1 V1 MUR22R I o i ds -1 3.us 3.4us 3.8us 31.2us 31.6us 32.us 32.4us 32.8us 33.2us 33.6us 34.us -I(R3) V(M1:1)/2 V(M1:2) I(I1) Time V1 = V2 = 15 TD = 1u TR = 1n TF = 1n PW = 2u PER = {1/fs} R2 1 V4 M1 MTB2N2E v ds v ds MTB2N2E 2. I o i ds v gs 2. v gs ids Io us 3.95us 31.us 31.5us 31.1us us -I(R3) V(M1:1)/3 V(M1:2) I(I1) Time 32.95us 33.us 33.5us 33.1us 33.15us 33.2us 33.25us 33.3us 33.34us -I(R3) V(M1:1)/3 V(M1:2) I(I1) Time 1

10 Problems of Hard-Switching Switching losses Device stress, thermal management EMI due to high di/dt and dv/dt Energy loss in stray L and Possible Solutions (combination) Snubbers to reduce di/dt and dv/dt usually no change in losses (unless loss recovery) ircuit layout to reduce stray inductances Gate drive circuit layout turn on / off speeds Soft switching to achieve ZVS and/or ZS 11

11 Snubbers Passive components (R, L, ) and a diode to shape switching trajectories Turn-on snubber (seldom used) V d L s i T v - T R s I o At turn-on Vd it ()= t L t s low di/dt lower turn-on losses in the device low reverse recovery current v T i T t t Price to be paid at turn-off 1/2 LI 2 energy dissipated during off interval off interval > 2 to 3 times L S /R S time constant switch voltage rating increases by R S I O 12

12 Turn-off Snubbers R S V d i T v T - D S i S S I o At turn-off while builds up i = I i T o S ( i flows through D ) S v T S switch turn-off loss decreases lower dv/dt i T I o S3 S = S1 S2 > > V d S S S v T Issues at turn-on 1/2 V 2 energy dissipated in R S and switch switch current rating increases by V d / R S ON interval > 2 to 3 times R S S time constant 13

13 Soft-Switching ZVS (Zero Voltage Switching) ZS (Zero urrent Switching) Advantages - Lower losses (may be!) - Low EMI (may be!) - Allows high frequency operation 14

14 ZVS (Zero Voltage Switching) Turn ON Turn OFF Switch voltage brought to zero before gate voltage is applied Ideal, zero-loss transition Low-loss transition Parallel capacitor as a loss-less snubber Preferred scheme for very high frequency applications using MOSFETs 15

15 ZS (Zero urrent Switching) Turn OFF Switch current brought to zero before gate voltage is removed Ideal, zero-loss transition Turn ON Low-loss transition Series inductor as a loss-less snubber Energy in junction capacitance is lost Best suited for converters with IGBTs due to tail current at turn-off 16

16 ZVS and Hard-Switched Waveforms Zero-voltage switched Hard-switched vdrainsource vgatesource 12V vdrainsource vgatesource V V 12V 12V 17

17 An Example: Zero Voltage Transition (ZVT) Synchronous Buck onverter v ( ) At t =,T v - is turned off ( ) = = V d T i i L v v = V - d V d T A D D - i - i L L V o 18

18 Zero Voltage Transition (ZVT) V d Since v v = V - d s dv dv - = s dt dt i i = T T A s D D - s - i i - i L L V o Also, i - i = i - L i = -i = v = v - = V - d il 2 V d At the end of this charge/discharge interval, positive i L is carried by D Subsequently, T is turned on; i L must reverse direction 19

19 Zero Voltage Transition ( t) va ( ) a T s i V d V o V d T A D D i - - s i L L V o t " t t t 1 t t i L t t t onducting Devices T None D T None D T None 2

20 Simulation of a ZVT Buck onverter PARAMETERS: R7 V7 25 M1 IRF15 L1 PulseWidth = 4.5us TDLY1 = 5.5us TDLY2 =.5us Period = 1us 21V V1 TD = {TDLY1} 2uH I = 2A R8 V8 25 M2 IRF15 1uF I = 1V 2 R6 1. TD = {TDLY2} ZVT_buck.opj 2 1 v DS gate input v GS i L i D us 1us 11us 12us 13us 14us 15us 16us 17us V(M2:d)/2 ID(M2)*2 V(M2:g) I(L1)*2 V(V8:) Time 21

21 lassification of Soft-Switching Schemes Load Resonant onverters onverters with Resonant Switches (Quasiresonant, Multi-resonant) Resonant Transition onverters ZVT and ZT 22

22 Phase Shift ontrolled Full-Bridge onverter (ZVT) Makes use of switch capacitances and transformer leakage inductance and magnetizing current T A T B Vd T A A T B B D a D a a D b b D b Io Poles A & B switched at nearly 5% duty-cycle Output voltage regulation is achieved by phase modulating the two pole outputs 47

23 Switching waveforms v A V d 2 ficticiousvin V d 2 T A T A A D A D A D B T B i AB v B T B AB D B L lt i L v B D a v AB D a i AB a D b b D b I o t In pole A T T A tot A A tot A v AB = v AB = V d -V d In pole B T tot v = V B B B B AB T tot v -V = AB d d 48

24 Transitions - Pole B T B to T B v AB T to T - B B V d T B T A i L T B D a A B a b I o D b i AB t v AB = V d AB v = -V d T to T - B B i L stays at I o L i stays at -I o 49

25 Transitions - Pole A V d T A T A A B T B i L D a a b D b I o v AB i AB T to T - A A t T tot v = A A AB -V d All four diodes conduct Leakage inductance resonates with switch capacitance Determination of T del critical for ZVS design Load dependent ZVS 5

26 Methods to increase ZVS range Use of external series inductor L o V in A i AB L B series v rect V o v AB i AB Disadvantages Loss of volt-sec higher turns-ratio v rect left-leg higher conduction loss increased VA ratings Load dependent ZVS 51

27 Use of magnetizing current V in A i load i mag i mag B Disadvantages higher conduction loss due to v AB i mag peak circulating current current through right-leg MOSFETs peak magnetizing current independent of V in 2 left leg 52

28 Factors Affecting ZVS ZVS Load Range apacitance across MOSFETs internal and external Leakage inductance Delay time Magnetizing current Design of other parameters like L o, o, transformer etc identical to hard switched PWM 53

29 Designing for ZVS MOSFET voltage during critical turn-on transition L vds = Vin Imag _ pk Irefl sin t 2 ( ) eq ( ω ) ds v ds ω = 1 2π Leq ds onditions for ZVS π 2 L Lk 2 ds t Leq 1. ( I I ) V 2 mag _ pk refl in,max ds π 2. T = L. 2 2 delay eq ds 54

30 A Possible Design Approach Using MathAD Sweep for all practical values of ds - based on limiting voltage rise during turn-off T - as a percentage of switching period delay Designing for ZVS alculate required I and L for each set mag,pk alculate switch peak current and RMS current lk Turn-off loss onduction loss alculate total losses. Iterate for different ZVS ranges 55

31 Designing for ZVS Total Losses (W) j i j ds i T del Total_loss 56