Slow controls of MROD. System overview ( CSM )

Transcription

1 Slow controls of MROD System overview MROD power-up sequence JTAG via SLINK return channel T. Wijnen MROD--DCS workshop - Amsterdam, 06 Dec System overview ( ) TDC #1 Serial to Parallel Conv. & Clock Domain Separator 18 x 18 x Separator 1 S 18 TDC #18 Serial to Parallel Conv. & Clock Domain Separator Clock/Trigger Data/Strobe 06 December 2000 T. Wijnen 2 Thei Wijnen 1

2 Tower of chambers System overview ( MROD ) MROD MRODOUT ROB 06 December 2000 T. Wijnen 3 System overview ( MROD crate ) DAQ / DCS Network ROB ROB VME-bus TTC-bus LDAQ MROD total... MROD 12 x TTC Interface ROD Busy 6 SLinks 6 SLinks From TTC system One MROD crate services 12 towers (e.g. 6 large + 6 small sectors on one Z-side) In total 16 crates are needed for all MDT chambers. Some MRODs have 7 or 8 SLink inputs via slave MROD cards. 06 December 2000 T. Wijnen 4 Thei Wijnen 2

3 VME64x MROD-1 3x (in total) Sharc Links (2x) TTC-Rx 06 December 2000 T. Wijnen 5 MROD Power-up sequence Re-configure s from EEPROM Stay inactive until VME Master has booted VME Master load Output- with program code and starts the s The 3 Input-s boot via a Link from the Output- (and the VME Master) The s wait for commands from the VME Master e.g. Initialize MROD (enable/disable SLinks, Zero-suppress, etc.) Start / Pause / Stop the run, etc. Initialise and Front End Boards via Slink Return Lines 06 December 2000 T. Wijnen 6 Thei Wijnen 3

4 FE parameter loading/initialization JTAG routing: via DAQ TTC routing: TTC MDT-DAQ TDCs & ASDs MROD ROB Mezzanine boards DCS JTAG routing: via DCS 06 December 2000 T. Wijnen 7 JTAG Usage Initialize/Set/Reset ASD/TDC/ parameters Reload parameters or Flash (if needed) Calibration sequence: 1: JTAG enables calibration pulses in the ASD 2: The TTC signals the to send a test pulse and the TTC system provides the calibration trigger Note: the JTAG clock (TCK) must be turned off during all data taking to avoid noise on the ASDs. 06 December 2000 T. Wijnen 8 Thei Wijnen 4

5 JTAG architecture more registers Internal Register #2 Internal Register #1 Bypass Register Test Data In TDI Instruction Register TDO Test Mode Select Test Clock TMS TCK TAP Controller Test Data Out Test Reset* (optional) 06 December 2000 T. Wijnen 9 JTAG timing TMS (TDI) TCK TCK: asymmetric, start/stop mode TMS/TDI must comply to setup/hold time Easy to generate by program in 06 December 2000 T. Wijnen 10 Thei Wijnen 5

6 SLINK interface with Return channel Physical Link ( for MDT ~ 100 m length) Link Source Interface Forward channel Return channel Link Destination Interface MROD program controls individual Return lines SLink protocol requires min. 32 clock cycles pulse width Maximum speed: ~ 200 kbit/s (over long fiber) 06 December 2000 T. Wijnen 11 JTAG via SLINK return channel Slink return lines bit 3 bit 2 bit 1 bit 0 Address/JTAG mode adr2 / TCK adr1 / TMS adr0 / TDO When bit3 = 1 : use bit 2,1,0 as an address for sub-device (ASD/TDC//TTCRx,...) When bit3 = 0: use bit 2,1,0 as the JTAG lines (TDO= data from MROD) The TDI line going back to the MROD is inserted in the Separator word (bit 18). this implies that the multiplexer must run after power-up (reset) ( should insert all-zero words in stead of TDC words until the first trigger arrives. ) 06 December 2000 T. Wijnen 12 Thei Wijnen 6

7 Conclusion JTAG via S-Link Return Lines is not very elegant but Run Control related parameter setting directly from (Local) DAQ Implementation in MROD without additional hardware cost Cheap when the Duplex S-Link interface becomes the standard 06 December 2000 T. Wijnen 13 Thei Wijnen 7