CCS Hardware Test and Commissioning Plan

Transcription

1 CCS Hardware Test and Commissioning Plan ECAL Off-Detector Electronics Workshop 7-8 April Kostas Kloukinas CERN

2 Overview CCS Development Status Production Plan CCS during Integration and Commissioning 7/4/2005 Kloukinas Kostas 2

3 The FEC-CCS System Design satisfy the requirements from: Tracker ECAL Preshower Pixel RPC Three components: mfec: small mezzanine card suitable for VME and PCI utilization. PCI-carrier: motherboard for one mfec FEC-CCS: VME motherboard for 8 mfecs. FEC tracker = CCS ecal * 7/4/2005 Kloukinas Kostas 3

4 mfec & PCI carrier mfec on a PCI carrier board to facilitate development work to be used in the lab and test beams. 7/4/2005 Kloukinas Kostas 4

5 FEC-CCS V2 (Prototype) VME Interface FPGA mfecs VME backplane ECAL backplane TTC input Trigger FPGA 7/4/2005 Kloukinas Kostas 5

6 FEC-CCS V3 (Final) V2 to V3 modifications: Splitting of 1-wire bus for temperature sensors and serial ID chip. Reassignment of JTAG backplane signals. QPLL & TTCrx control lines. Routing of spare FPGA lines at the P2 connector. One board assembled. Tested O.K. 7/4/2005 Kloukinas Kostas 6

7 Prototype Test Status VME to Local Bus interface is O.K.. All 8 mfecs can be and accessed from the VME bus. Conforms to the VME 64x plug & play standard. VME Interrupter is tested. Various Functions Electronic Serial Number tagging using a serial ID chip. Airflow temperature monitoring of the OPTOBAHNs on mfecs Fast Timing path is tested. TTCrx Trigger FPGA mfecs control rings. Send trigger commands to FE and DCC. Power consumption (measured) Card fully equipped with 8 mfecs 3.3V, 5.0V => ~30W dissipated Pending Issues: TTS signal functionality. DCC-CCS-TCCs integration tests. VME bus JTAG basckplane controller access. 7/4/2005 Kloukinas Kostas 7

8 Pre-Production Status FEC-CCS: Version 1: First prototype. 2 units have been fabricated. Were used in the TRACKER test beam and in the ECAL test-beam setups (summer 2004). Version 2: Second prototype. 8 units have been fabricated. All units are tested and fully equipped with mfecs. They are available for distribution. Version 3: Final version. Pre-production of 10 boards is in progress. 1 unit delivered (11/3) and currently being tested 9 more will be delivered around early April. 7/4/2005 Kloukinas Kostas 8

9 FEC-CCS Test Bench XDAQ (HAL) framework Full plug&play support Software development by: E. Vlassov F. Drouhin CERN scientific Linux >_ 7/4/2005 Kloukinas Kostas 9

10 Component Traceability Managing the distribution of FEC-CCS boards. FEC-CCS Project Website: proj-fec-ccs.web.cern.ch/proj-fec-ccs 7/4/2005 Kloukinas Kostas 10

11 Final Production Tracker: 352 control rings => 44 FEC-CCS boards ECAL: 368 control rings => 46 FEC-CCS boards Preshower: 48 control rings => 20 FEC-CCS boards Pixels: 120 control rings => 16 FEC-CCS boards RPCs: 25 control rings => 4 FEC-CCS boards FEC-CCS boards 116 FEC-CCS boards => 930 mfecs 50 PCI FEC boards => 50 mfecs mfecs Spares should be added. 7/4/2005 Kloukinas Kostas 11

12 Production Schedule Production of 900 mfecs is in progress. Production of 140 FEC-CCS boards to start soon. All components have been procured PCB manufacturing and assembly companies found. Production Testing Will be done at CERN Test bench and test procedures are currently under development. 7/4/2005 Kloukinas Kostas 12

13 Integration & Commissioning FEC-CCS board should facilitate: Front-End system testing & debugging. Possibility to run DCC-CCS-TCC(s) standalone. Enable data taking when LTC-TTCci system is unavailable. 7/4/2005 Kloukinas Kostas 13

14 Final System TTC/TTS signal paths Local Triggers TTCmi TTC Global Trigger Controller TTS Controller LTC TTC ci TTC ci TTC ci TTC ci TTC ex TTC ci TTC ci TTC ex TTC ci TTC ci TTC ex Controller FMM FMM CCS CCS CCS CCS TTS Controller DCC TCC DCC TCC DCC TCC DCC TCC TTC 7/4/2005 Kloukinas Kostas 14

15 FEC-CCS during Integration When final System is not yet available / operational Requirements: Enable Slow Control for the FE electronics. Generation of Local Trigger Commands and their distribution to the FE and to the OD electronics. Off-Detector electronics (DCC, TCCs) synchronization at the level of one supermodule. Implementation: Hardware Interface with external signals to synchronize internal operations. Firmware Trigger FPGA functionality to allow the generation and distribution of the Local Trigger Commands. Software To support these functionalities. 7/4/2005 Kloukinas Kostas 15

16 FEC-CCS Block Diagram Support for 1~8 control rings per board. VME 9U board. VME64x compatible. Control information passes through the VME bus. Fast Timing Signals passes through the TTC link. mfec mfec mfec mfec mfec mfec mfec Local Bus Fast Timing signals VME interface FPGA Trigger FPGA JTAG External I/O VME bus mfec TTCrx QPLL TTC link ECAL TTC/TTS bus 7/4/2005 Kloukinas Kostas 16

17 FEC-CCS Piggy Back Board Trigger FPGA logic. ECAL Test Beam Summer 2004 Prepared by Mark Dejardin 7/4/2005 Kloukinas Kostas 17

18 FEC-CCS Multi I/O board As a replacement of the Piggy Back I/O board. Propose to build a 3U Rear VME Backplane Transition Board Connects on spare Trigger FPGA lines. Only FEC-CCS V3 supports this card. VME RJ2 connector LVTTL to NIM NIM to LVTTL NIM I/O 4 IN 4 OUT 1 clock in 1 clock out (+ 4 IN/OUT spares) LVTTL I/O 7/4/2005 Kloukinas Kostas 18

19 Trigger FPGA firmware design IN OUT 4 4 CCS Clock Piggy Back Board NIM to TTL TTL to NIM translators Trigger FPGA Local Bus interface & Control Registers CCS Local Bus Clk40_L1 to mfecs L1ACCEPT BRCST<7:2> TTCRX_RDY Trigger Command Manager L Clk40_L1 Token Ring Clock Encoder TTCrx Clk40 Clk80 TTC in QPLL 40MHz 80MHz 160MHz L1 B<7:0> TTC Encoder Clk40 Clk40 Clk160 TTC signal to DCC/TCCs 7/4/2005 Kloukinas Kostas 19

20 Trigger Command Manager (1/4) FEC-CCS modes of operation REMOTE: Trigger Commands as received from the TTCrx chip are being distributed to Token Rings and the ECAL backplane. Used for Normal Data Taking operation. LOCAL: Allow the generation of Local Trigger commands. Used for system debugging. Mode Selection Auto Remote/Local selection is automating depending on the status of the TTCRX_RDY signal. Forced LOCAL User selection 7/4/2005 Kloukinas Kostas 20

21 Trigger Command Manager (2/4) Mapping of TTC B channel commands to Token Ring Trigger Commands B-Go command TRACKER ECAL Preshower PIXEL RPCs TTC Brcst<5:2> Function T Ring Function T Ring Function T Ring Function T Ring Function T Ring Function Not Used BC0 101 BC0 101 BC TestEnable TEST_ENABLE PrivateGap PrivateOrbit ReSync 101 RESYNC 110 ReSync 110 ReSync 101 ResetTBM HardReset RESET ResetEventCounter 111 ResetROC ResetOrbitCounter Send Start Stop Free1 110 APV_CALIBRATE 111 Monitoring 111 CalPulse 110 CalSync 12 Free2 13 Free3 14 Free4 15 Free5 16 Free6 TTCrx signal L1ACCEPT BcntRes EVcntRes 100 L1 100 L1 100 L1 100 L1 Trigger Command Assignments on the Token Rings are not common between subsystems. The FE ASICs decode these commands in a fixed manner. Mapping of TTC B channel commands to Token Ring Trigger Commands can be done by a LUT in the Trigger FPGA. 7/4/2005 Kloukinas Kostas 21

22 Trigger Command Manager (3/4) Generation of Local Trigger commands External signals Local L1 Trigger Command. Internal signals External signals LOC_L1 command channel 7/4/2005 Kloukinas Kostas 22

23 Trigger Command Manager (4/4) EXT_IN LOC_L1 LOC_B110B LOC_B101B LOC_B111B GEN1 TTC_X1 OUT1 OUT1 OUT1_delayed EXT_IN LOC_L1 LOC_B110B LOC_B101B LOC_B111B GEN2 TTC_X2 OUT2 OUT2 OUT2_delayed Frequency Generator 1 GEN1 Frequency Generator 2 GEN2 7/4/2005 Kloukinas Kostas 23

24 Wrap Up Flexible and configurable logic allows for: Single shot commands. Single shot Bursts of commands. Sequence of multiple commands. Periodic Sequence of multiple commands. Synchronization with external signals. Generic design The Integration Physicist/Engineers can modify the Trigger Generation logic as required for their setup. Other sub systems could possibly utilize these functionalities Easy firmware maintenance. Unique version for all subsystems. Comments & Discussion.. 7/4/2005 Kloukinas Kostas 24

25 Backup Slides 7/4/2005 Kloukinas Kostas 25

26 Piggy-Back PCB R. Benetta, M. Dejardin 7/4/2005 Kloukinas Kostas 26

27 FEC-CCS Piggy Back I/O board Prepared for the ECAL Test Beam in Summer by Mark Dejardin 7/4/2005 Kloukinas Kostas 27

28 Trigger FPGA Registers Available only for the ECAL Test Beam summer /4/2005 Kloukinas Kostas 28

29 Trigger FPGA design BOB EOB Laser In TDC Start TDC Stop Laser Out Loc L1 CCS Clock TTCrx Piggy Back Board NIM to TTL TTL to NIM translators QPLL 40MHz 160MHz ECAL Local Trigger Management Logic Clk40 Trigger Insertion Logic Clk40 Clk40 Clock Management Logic Trigger FPGA Local Bus interface & Control Registers Clk40_L1 Clk40_L1 CCS Local Bus Clk40_L1 to mfecs TTC signal to DCC 7/4/2005 Kloukinas Kostas 29

30 Overview of CCS Board 7/4/2005 Kloukinas Kostas 30

31 FEC-CCS Production Testing Production Testing will be done at CERN Separate Test Benches: For the mfecs will be PC based. Using PCI carrier boards. For the FEC-CCS boards will be VME based. Hardware needed: PCI bus, preferably allowing hot plug-in. TTC/TTS backplane driver board. TTCvi or TTCci. Software needed PC software for mfec testing Linux software for FEC-CCS testing. 7/4/2005 Kloukinas Kostas 31