March 12, 2013 Dr. Alexander Tetelbaum. Design Automation

Transcription

1 March 12, 2013 Dr. Alexander Tetelbaum Design Automation

2 Variations and Timing Signoff become even more important for 20nm node & below because more: Variation sources and their magnitude Complex designs & technologies Current (conventional/commercial) methods for timing derating (OCV, AOCV, LOCV, POCV, and SSTAs) represent an improvement vs. initial OCV method, but they have their limitations It is important to improve timing derating: To avoid missing violations and reduce pessimism And without introducing new STA tools and changing main steps of signoff flow Main goals of this presentation are: Show possible risk factors & inaccuracies in derating methods Investigate new Abelite technology to enhance timing analysis Develop ways to rapidly obtain timing estimates at additional PVT/RC/SPEF corners without re-running Extraction and STA tools Develop new Standard Timing Format for using new tools within current flow 2

3 All methods that will be presented: Are complementary to Cadence s Encounter Timing System (ETS) and Synopsys PrimeTime (PT) tools/flows and allow improving accuracy of timing & overcoming current limitations Use the original STA timing report as an input May find missed violations & improve design metrics (performance, timing yield, etc.) & reduce Turn-Around-Time Introduce proper not-pessimistic statistical derating that covers all sources of variations & EDA tool/libraries errors New Abelite timing technology: Uses path-driven signoff paradigm Is pseudo-statistical or statistical by nature Separates cell, wire and via variations Takes into account: The number of timing critical paths Correlations within and between variation sources Aging degradation, dynamic crosstalk effects, etc. 3

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5 Comparison of Time Derating Methods (cont.) Aspe ct Derate Method Conventional STA OCV One global margin AOCV LOCV Margins Table POCV One stage margin Pseudo-stat on all paths AT- AT-True Rite EAOCV Pseudo-stat on given paths Handling Correlations N N N Y- (simplified) Y- Y Y+ Aging Degradation N Y- N N Y- Y Y+ Handling Complex Cells N N N Y Y Y Y Statistical Crosstalk N N N N Y- Y Y+ DPT Variation N N N N N Y Y+ FinFET Variations N N N Y N Y Y+ Signoff Flow Management N N N N N Y Y AT- Stat Monte Carlo Tools/Libraries Inaccuracies N N N N Y- Y Y Variation Information Volume L M L H+ M M+ H- Flexible EP Margin N N N N Y Y Y Timing Yield Estimation N N N Y-(@corner) N N Y Stats & Report Summaries N N N Y- (limited) Y- Y Y+ SSTA Abelite Tools Reusing One SPEF Extraction N N N N N Y Y STF (Standard Timing Format) N N N N Y Y Y 5

6 STA derating methods do not differentiate between sources of variation SSTA tools mostly take into account local variations in transistor process at one global corner Correlations are practically ignored or very simplified methods are used Very limited support in determination of derates Conventional STA/SSTA Are unique & take into account all sources of global & local variations in: Transistor process including FinFET Voltage (supply, static, and dynamic) Temperature in cells (including T- inversion), wires & vias Geometry properties in wires & vias: Width, Height & Dielectric Thickness Double Pattern Technology (DPT) that varies wire spacing Inaccuracies in EDA tools (Extraction, 3D FinFET, Delay Calculation & Libraries vs. Silicon) Dynamic crosstalk delay variations Aging degradation, etc. Abelite Tools 6

7 Accuracy may be not high enough if paths structures/properties differ from the method s assumptions It may lead to: Optimism in timing (risk factor) & even to silicon failure Pessimism that worsens all design metrics Conventional STA/SSTA Tools Find all real timing violations & it s a must Decrease pessimism as a crucial task that improves: TAT Costs Design metrics Abelite Tools 7

8 Ignoring: Correlations between cells, wires & vias Number of timing critical paths Handling crosstalk & some other dynamic effects in a conservative static way Handling DPT in a conservative static way Simplified or not-justified methods of finding margins & there is no serious support from manufacture and EDA vendors Not properly separating delay variations in cells, wires & vias Using the same derating tables: For setup & hold checks to minimize runtime (no separate STA runs) For different PVT & RC/Via corners (usual case due to challenges in finding & supporting multiple derate tables) Not-uniformly distributed stage delays in paths Presence of complex or hierarchical cells with: Internal paths with depths more than one Internal built-in OCV margin 8

9 SSTAs Do Not Solve All Problems These tools take into account only some local variations around given global corner Mainly transistor process OCV Their other drawbacks include: High inaccuracy in modeling by using approximate pseudostatistical methods & simplifications Signoff at multiple PVT/RC global corners still required STA traditional signoff still required Ignoring real correlations Expensive libraries characterization, increased runtime and disc-space Ignoring many variation sources Results are not easy to interpret Ignoring the above issues may lead to problems including silicon failure 9

10 Limitations and drawbacks may lead to optimistic timing & silicon failure Derating Tables assume some bad rare scenarios in paths: They are still not the worst possible scenarios in order to avoid too much pessimism for the rest of paths Those few really worst paths are still at risk because they are optimistically estimated Ignoring number of critical paths Examples: (1) ~39% hold slacks were under-estimated by PT/AOCV in design #1: a relatively big risk factor (2) ~1% paths with hold violations were overlooked by PT/AOCV in this design Conventional STA/SSTA Tools Hold violations are the most important & must be never missed Setup violations must be not underestimated or missed: Less yield Failure to meet spec F Abelite Tools 10

11 Place and Route tools do not separately balance cell & net delays in clocks It may lead to problems. Example of a problem with bad path structure: Launch is fully net delay dominated & capture is fully cell delay dominated Signoff at many PVT/RC corners is needed to avoid silicon failure AOCV tables cannot take into account inter-clock correlation properly & it may lead to optimism Missed violation in the Example: - Traditional Setup check is at Slow Process corner including V min & different Temperatures & RC-models -If we add corners with untraditional V max, then capture will become faster (up to 20-30%) & it means that we have overlooked a serious violation. There are other dangerous situations for hold & setup: Conventional STA/SSTA Tools 11

12 Have very limited delay scaling capabilities Usually only for voltage & within ±10% of the corner Multiple detailed libraries must be characterized Conventional STA/SSTA Tools Have fast, accurate (Error<10%) & powerful scaling Scale cell, wire, via & xtalk delays from given PVT/RC corner to all other corners Do express delay analysis across all PVT/RC space One SPEF is scaled and reused for any corner temperature w/ Error<0.7% Monte Carlo timer (at_stat) uses fast scaling across the whole variation space Abelite Tools 12

13 Signoff is performed at multiple Global PVT/RC/Via corners It is important & not trivial to find minimum corner number Conventional tools do not support corner minimization Even considering only extreme points per a factor produces 64 corners The more factors are included into corner, the more pessimistic signoff is More corners needed for advanced technologies & new phenomena: Aging degradation Multi-voltage domains combinations Over- & under-drive voltages DPT & FinFET Do not need most of these corners Find each path-structure/-case: There are only limited number of them Each path-case can be analyzed by using corresponding {corners}, but not more than 3 for each timing check Companies use ever increasing corners number (from 8 to 128) Conventional STA/SSTA Tools Find needed additional corners for each critical path Abelite Tools 13

14 Illustration: One Path & Its Slack Variations Abelite technology finds all potential violators during one tool run: - Any degree of confidence can be achieved - Optional follow up STA or Abelite runs (for found violators) may refine results - Inaccuracy in scaling to extreme PVT/RC corner is not critical 14

15 Illustration, cont. Nominal Area of PVT/RC Space requires the highest timing accuracy Peripheral Area of Space does not require high timing accuracy because: ~ σ (1) Small probability of all dies in this extreme & rare area (2) Natural fussiness in this area 15

16 Variation Space Die In (at Global Corner Co ): - Co may be not Nominal - Analysis may be repeated for different corners in Die samples (local variations) around given corner Co = One die sample is a set of path samples in die generated by Monte Carlo & modeling local OCV 16

17 Die In (at Global Corner Co ) Global & Local Variations around Input corner Co Die sample at a New Global Corner C generated by Monte Carlo with Local variations around C 17

18 Die In (at Global Corner Co; there may be several corners in) Die Sample at New Global Corner C scaled from Input corner Co & generated by Monte Carlo. It includes Local variations (generated by Monte Carlo) around Global Corner C 18

19 Die In (at Nominal Global Corner Co) Die Sample at New Global Corner C scaled from Input corner Co It includes Local variations around Global Corner C 19

20 Voltage V V_max V_nom P Process sigma Animation timing is close to Real tool runtime for a design with ~30 timing critical paths V_min 20

21 Current methods: All timing violations must be fixed Yet, it does not prevent a silicon failure & design respin: It is true even with ever increasing derates Conventional STA/SSTA Tools Do not consider each path with a negative slack (at some corner) as a violator: It may not mean zero or unacceptable timing yield Not all violations must be fixed Path criticality and estimated timing yield Y for the design across all corners must be taken into account to make decision if the violation must be fixed or not It minimizes TTM and design costs Abelite Tools 21

22 Designs often have uncorrelated V-domains V-domains may have any combinations of min/max voltages & between Considering all V-combinations may be expensive & not supported automatically Using timing derates is risky & pessimistic Partially correlated V-domains are not supported Current methods are conservative for GA & based on WC-scenarios (even not-realistic) Conventional STA/SSTA Tools Have modes for: Fast finding worst slack V- combination w/o considering all combinations Scaling V-domains to any PVT/RC/Via corner Automatically exercising all V-combinations (for verification) Can handle partially correlated V-Domains Monte Carlo engine explores PVT/RC space with random combinations of voltages in V-domains Abelite Tools 22

23 STA runtime is significant but has recently improved Runtime & memory required are much more for SSTA tools Reason: A need to investigate all paths in design Conventional STA/SSTA Tools Memory requirement is one magnitude less Runtime is small: 500-2,500 paths per 1 minute (at_true): Reason: New methods used & analyzing only given set of timing critical paths after STA run at_stat runtime is more & proportional to global space size Runtime will be faster with multi-threading or parallel processing Abelite Tools 23

24 Pessimism comes from: Extreme-corner definition / characterization & Extremecase methodology: Corners & Derate Tables assume some bad but rare scenarios in paths and Typical paths will be pessimistically estimated & overdesigned Statically combining cell, wire and via corners Using unjustified conservative margins Adding static conservative xtalk & aging degradation Ignoring internal depth & build-in margin in complex cells Conventional STA/SSTA Tools Solve most problems using new paradigms in handling variations: Statistical methods Matching corner confidence to individual stage situation: Typical stage does not need 5-10 sigma confidence Handle cell, wires and vias separately Use new models and methods Abelite Tools 24

25 Pessimism: AT_True vs. PT/AOCV 3 Test-designs (#Critical paths): C1 (100), C2 (300), C3 (500) 25

26 STA: Cell, wire & via delay variations are just summed together into stage variation No clear separation between cells, wires & vias, which are not correlated for most factors No SSTA tool that considers wire & via variations Conventional STA/SSTA Tools Explicitly separate cells, wires & vias Consider global & local variations Use new models that describe wire/via variations as functions of geometry properties & temperature Consider correlations within & between variation factors Abelite Tools 26

27 Wire Process Factors Adjacent Layer Wires Adjacent Layer Wires Go-Wo Left Wire Go Wo Wire Lo Right Wire Ho Go-W+S Left Wire W Wire L Go-W-S Right Wire H Adjacent Layer Wires Adjacent Layer Wires Typical Wire Process Wire Process with variations Right Wire at layer i Wire at Layer i C2i Left Wire at layer i C1j Wire at layer j C2j Left Wire at layer j C3i Wire at layer i C1i Right Wire at layer j C3j Wire continues at Layer j 27

28 Via Process Factors Left Wire Left Wire Wire Go-Wo Wo Via Wire Go-Wo Go Wo Wire Go-Wo-dW Wo+dW Via Wire Go-Wo+dW+S Go+S Wo+dW Right Wire Right Wire Wo Wo Layer i Wire Ho Layer i Wire Ho Dielectric Via Do Lo Dielectric Via Do Lo Wire Layer i-1 Wire Layer i-1 Typical Via Process Process with variations 28

29 Current derating ignores Number of timing critical paths N CR, which actually may require an increased confidence level: Up to 4-5 sigma May lead to optimism Conventional STA Tools Achieve requested (by the user) confidence level (like 3 sigma) for the whole design: Not just for one path This confidence level is a function of N CR If design has more critical paths, the timing yield is decreasing & failure risk is increasing because a violation only in one path is enough for failure Abelite Tools 29

30 Assumption: Stage delays are about the same (uniform stage delay distribution): Then using LOCV/AOCV derate tables may be OK If the above is not true, total path derate becomes optimistic. Example: 1. Path with Depth =12 & Stage variation of 18% 2. aseline Path is uniformed 3. Real path has a not-uniform distribution: One stage S1 has more delay than average cell delay. Delay Ratio = Delay(S1) / Path delay Conventional STA Tools Possible Optimism for the Example Handle paths with any cell/wire/via delay distribution by using new enhanced derating Abelite Tools 30

31 Aging Degradation (AD) increases cell delays during microchip life time caused by NTI, HCI, TI & PTI phenomena Signoff without taking into account AD introduces risk of: Setup violations before design End-Of- Life (EOL) & Hold violations when slowdown in capture is more than in launch Conventional tools do not directly support AD: Additionally, e.g., at a slow corner it is not enough to derate up all delays or use EOL libraries. There may be such path structures where setup violations happen at eginning-of-life (OF) & derating delays up will mask violations. AD-solver automatically selects OL or EOF model for each path allowing different Effective Stress (ES) for data & clocks & timing checks: No other STA/SSTA tool has such a solver & users will need 2x more signoff corners or use even more conservative margins, or accept additional risk & less yield AD-solver does it for the input corner & any additional target corners Conventional STA/SSTA Tools Abelite Tools 31

32 Use extreme scenarios to create worst-cases for DP/CLK & timing checks: 100% correlation within path 0% correlation between paths Have no support on correlation between clocks in derate tables: Tables take into account clock distances only. If we assume: WC clocks location during AOCV table generation, it will lead to pessimism C clocks location, it will lead to optimism There is no way to describe distance between clocks & provide inter-clock derate tables Handle all correlations within each & between variation factors: Ignoring correlated variations leads to timing inaccuracy Have special characterization & modeling Estimate correlations as functions of distance & location Model cell, wire & via delay variations induced by the same correlated factor (like temperature T) Conventional STA/SSTA Tools Abelite Tools 32

33 Examples of Correlations... C C V_net V_cell ρ_net ρ_cell V_net V_cell C C Not All Correlations Are Shown e D Dk {v1_n, v2_n,, vm_n} ρm_net=f(d,dm_n)... ρ2_net =f(d,d2_n) ρ1_net =f(d,d1_n) {v1_n, v2_n,, vm_n} Each variation k has its own distance constant Dk {v1_c, v2_c,,vn_c} ρn_cell =f(d,dn_c)... {v1_c, v2_c,,vn_c} ρ2_cell =f(d,d2_c) ρ1_cell =f(d,d1_c) 33

34 Complex cells have internal I/O paths with depth N > 1: Different internal paths usually have different depths Ignoring N leads to extra derating Manual specification of all depths is tedious & not supported Complex cells often have a built-in margin: E.g., memories usually have internal margin that takes into account some (not all) variations STAs are usually not aware of it It will lead to double margining The issues are not completely supported Calculate internal depth N automatically for each path in complex cells Statistically calculate derates taking into account N Automatically take into account internal build-in margin Proper handling of complex cells: Minimizes pessimism Improves accuracy Simplifies settings for STA Conventional STA/SSTA Tools Abelite Tools 34

35 Assume WC signal alignment for all victims & aggressors in all stages Are pessimistic for many paths, because such WC scenario may occur very rarely (once in 1, 2... or more years of chip life time) Ignore Factors such as the time to failure (TTF), design frequency F, the number of paths with crosstalk & realistic probabilities of crosstalk impact Are pessimistic in several paths as a result Take into account all mentioned Factors & consider crosstalk as a dynamic effect Use new statistical & less conservative methods: Fast methods Deliver requested confidence Conventional STA/SSTA Tools Abelite Tools 35

36 Use increased number of RCcorners or Use the same 5 RC-corners but with statically increased OCV values Conventional STA/SSTA Tools Allow using new DPT RC-corners, but introduce proper library credits to take into account rareness of these extreme situations Allow use non-dpt RCcorners with proper statistical increase in local wire space variations Abelite Tools 36

37 The same scripts for multiple corners for all paths Minimal support on: Checking settings History of signoff Design summaries No support on: Finding additional corners to run Conventional STA/SSTA Tools Use path-driven signoff: Minimal initial number of corners & finding new additional corners for each risky path Do checking of settings Report settings changes between runs Generate important path/design summaries Support regressions Abelite Tools 37

38 Tools, data, methodology & design flows are not perfect Signoff tools (Extraction, Spice, STA, SSTA, etc.) & Libraries are not 100% accurate These inaccuracies are significant No direct support on their characterization & taking into account Ignoring these inaccuracies is a significant risk factor Conventional STA/SSTA Tools Incorporate tools/libraries/flow inaccuracies (errors) into derates to prevent optimism in timing: Errors may be pure random, correlated, notcentered & have not normal distribution Consider errors as a type of variations and handle them properly Abelite Tools 38

39 STA: Relatively small amount of variations characterization to build derate tables, but with minimal support SSTA: 10-20x more volume of libraries and characterization Conventional STA/SSTA Tools Use new statistical methods allowing to significantly minimize characterization volume w/o adding too much error to slack: Rare corners do not need high characterization accuracy & many points 25% accuracy in characterization causes in average 0.8% error in slack Abelite Tools 39

40 Use constant End Point (EP) margin for all paths May be different for: Setup Hold Individual path margin may be provided by user, but it is a tedious process & values are usually unknown Allow setup EP margin to be different for different clock domains Determine margins automatically New slack margin can be useful to find all risky paths during initial screening: Applied at one (usually nominal) PVT/RC corner Finds potential violators across all PVT/RC space Much faster than running corners Conventional STA/SSTA Tools Abelite Tools 40

41 Timing reports are not standardized, difficult to read & analyze Reports do not have all important information It complicates using such reports by other timing signoff tools in order to improve, correct or statistically process reported data Conventional STA/SSTA Tools Use a new Standard Timing Format (STF) for reporting & exchanging timing info between tools. STF: Is additional to current timing reports Includes all important information Is structured Has minimum size May become an industry standard Prototype of STF is available Abelite Tools 41

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43 Use Corner-Driven Paradigm Have drawbacks that increase a risk of silicon failure & diminish design metrics Are time-consuming due to ever increasing corner numbers & rare occurrence of most corners: Considering all conceivable corners & spending most time on analyzing very unlikely corners at the expense of accurate analysis of realistic & important corners All paths are treated in the same manner & most time is wasted on analyzing paths at corners where they never fail A few really vulnerable paths may be not analyzed at needed & relevant corners Confidence level of timing is not consistent in different stages and may too conservative (up to 10 sigma for typical stages: P ~ ) Use simplified timing derating methods (OCV, AOCV, LOCV, POCV, etc.) in commercial tools 43

44 Statistical STA tools use Fixed-Global-Corner Paradigm SSTA tools address some issues, but are not panacea: Not truly statistical (approximate, not Monte Carlo methods) Perform only local variation analysis at a given global corner Take into account mainly transistor process variations, even though there are multiple other factors Handle interconnect statically even though interconnect delay may be greater than cell delay Handle correlations simplistically Conclusion on Current STA/SSTA Tools: May cause failure in few paths & a lot of pessimism in the rest of paths Require significant time for libraries characterization, running & fixing issues (including false) at multiple corners 44

45 1 st Paradigm: Path-driven signoff: Corners are auto-selected for each timing critical path High accuracy of all timing estimations by using advanced statistical methods for each critical path 2 nd Paradigm: Stage-based signoff: Equalizing risk at individual stages: Corner (library) confidence level C is estimated for each stage & derating is adjusted to have the same required confidence level K in all stages 45

46 Design resources & time are limited & must be spent on critical paths: If designers are fixing false violations, it makes more difficult to fix real problems or improve design metrics Performing timing signoff at whole variation space rather than at multiple rare corners Using powerful delay scaling in variation space Taking into account all variations & errors including: EDA tools/libraries inaccuracies Global & local variations Wire geometry & temperature Via geometry & temperature Dynamic crosstalk, etc. Handling complex correlations Using new pseudo-statistical & pure statistical Monte Carlo methods Handling timing yield & confidence level requirements 46

47 Timing signoff experts know statistics on: Number of designs that were not closed at a spec frequency in spite of all the design efforts & time Number of re-spins for designs due to insufficient timing yield or silicon failure These statistics are not published & the reasons are understandable. This is happening in spite of all the advancements in technology, EDA tools & methodology developed at Semiconductors, EDA & Electronics industries New advanced tools are emerging because: No room for silicon failure More accurate timing is needed to avoid pessimism These tools improve accuracy, provide risk management, minimize pessimism & signoff corners number, etc. Abelite technology is based on new paradigms to advance timing analysis & solve the contemporary challenges 47