Addressing the DDR3 design challenges using Cadence DDR3 Design-In Kit
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1 Addressing the DDR3 design challenges using Cadence DDR3 Design-In Kit Martin Biehl Ecole d'électronique numérique Fréjus 27.Nov.2012
2 Agenda 1. Key Design Challenges 2. DDR3 Design-In IP 3. DDR3 Design-In Flow & Methodology Cadence Design Systems, Inc. All rights reserved.
3 Key Design Challenges for DDR3 Timing Budget Signal Quality DDR3 Board and IC Package design Large solution space To be explored Component parameters and selection Stack-up and Layout Cadence Design Systems, Inc. All rights reserved.
4 Key Design Challenges - Timing Budget Set-up / Hold Times Data write w.r.t strobe Data read w.r.t strobe Addressing w.r.t clock Strobe w.r.t clock Data w.r.t Address Account for Clock/Strobe Jitters and Interconnect Jitters Slew-rates and hence derating of setup/hold Cadence Design Systems, Inc. All rights reserved.
5 Key Design Challenges - Signal Quality Thresholds DC and AC Noise-Margins Overshoots/Undershoots Magnitude Area tvac Minimum time for signal to stay above threshold Eye Data-Valid Window after accounting Jitter Slews that in-turn affect timing Rise/Fall times Cadence Design Systems, Inc. All rights reserved.
6 Key Design Challenges - Component Selection Memory-Buffers Trade-off between read-write cycles Controller Driver strength Trade-off between read-write cycles Connector Insertion loss Strobe/Clock differential buffers Should satisfy tdvac and overshoot/undershoot area requirements Cadence Design Systems, Inc. All rights reserved.
7 Key Design Challenges - Layout Constraints Trace-lengths Relational Propagation-delays Data-Strobe for balanced setup/hold Relational Propagation-delays Address-Clock for balance setup/hold Relational Propagation-delays Strobe-Clock for successful write-leveling Topology schedules Point to Point for Data FlyBy for Address Trace Impedance Example: Lead-in section (45 ohm) to Load-in section (60 ohm) through neck-down (~5 to 10 mm) for clock Percentage variation that can be tolerated Differential matching (CLK, STROBE) Maximum unparallel length Cadence Design Systems, Inc. All rights reserved.
8 DDR3 Design-In Kit Content: Design-In IP! Controller IO+ IC Package Model Timing/Deration Model Connector Model Memory Model Scripts, Utilities & Documents Electrical Constraints DIMM topology Cadence Design Systems, Inc. All rights reserved.
9 DDR3 Design-In IP Frequency: 800/1066/1333/1600 DIMM-Type: A to F Configuration: 1-slot/2-slot/on-board Addressing: IT/2T AC-Threshold levels:150/175 Slew-rate based derating Cadence Design Systems, Inc. All rights reserved.
10 DDR-3 Design-In Flow & Methodology Building Project Timing Verification Timing Estimation ECset generation IO-model selection Bus-Analysis SI solution space Allegro PCB SI 16.5 EMA TimingDesigner 9.2.5
11 Building Project Frequency of operation and AC threshold levels Configures TD models Configures custom measurements Address (1T / 2T) Configures TD models New DIMMs (Or On-board) vs Existing DIMMs Pre-created Topologies vs Extracted DIMM topologies DIMM Card Type Configures topologies and ECSets Cadence Design Systems, Inc. All rights reserved.
12 Timing estimation Estimate Etchdelays of datastrobe-clockaddress such that all timing constraints are met Balance setup/hold is achieved interconnect jitter is tolerated Constraint TDQSS TDSH TDSS TDS TDH TDIPW TDQSH TDQSL TCH TCL Description Strobe rising time relative to rising clock edge. Strobe falling edge setup time to rising clock edge. Strobe falling edge hold time to rising clock edge. Data setup time Data hold time Data pulse width Strobe output high pulse width time. Strobe output low pulse width time. Clock high pulse width time. Clock low pulse width time Cadence Design Systems, Inc. All rights reserved.
13 IO-model selection/exploration - Card A with Card B Cadence Design Systems, Inc. All rights reserved.
14 Relational topologies - Refine etch-delays for strobe centering Cadence Design Systems, Inc. All rights reserved.
15 Timing Verification after SI-annotation Re-verify timing after import of SI propagation-delays Cadence Design Systems, Inc. All rights reserved.
16 Setting up ECSets Propagation Delays Impedance RPD Max Parallel Cadence Design Systems, Inc. All rights reserved.
17 Bus Analysis Use Signal Jitter & Offset from TimingDesigner diagrams Use DDR3 derate-file for setup/hold margins Cadence Design Systems, Inc. All rights reserved.
18 DDR3 Design-In IP The Cadence way to explore and implement the protocol Etch-delay estimation for timing Pre-layout Signal- Integrity to Timingclosure Signal-Integrity checks using estimated etch- delays Generation of layout constraints for board routing based on SI topologies Etch-length and Buffer strength (ODT) refinement for better eye Post-layout Bus simulations and verification Cadence Design Systems, Inc. All rights reserved.
19 DDR-3 design-in kit - Reverse-engineer a board Pick DDR3 board Designed at 800Mbps Timing Closure against 1333 Mbps data-rate Timing model Extract topology ECset generation SI verification and exploration For 1333 Mbps Bus-Analysis on Updated board Cadence Design Systems, Inc. All rights reserved.
20 DDR-3 design-in kit - Decide IO-buffer timing parameters DDR3 reference board SI extraction of nets -Propagation delays -Estimated Xtalk -Stack-up variation Timing Exploration for Buffer -TCO delays -Write-leveling delays -PLL jitter / DCD SI verification using SPICE IO-buffer models Cadence Design Systems, Inc. All rights reserved.
21 DDR3-design in kit Full version (IP560): Can be customized and applied to designs DDR3 custom-measurements and Eye-masks Generic IBIS IO buffers for DDR3 controller and Memory Basic Timing-models for different speed-bins: 800, 1333, 1600Mhz Simulation patterns and setup/hold derate-file Post-route flow with Reference Mother-board and DIMM Pre-route flow using pre-created topologies corresponding to different DIMM cards ECSet templates for guiding routing of boards Enhanced Timing-models Write-leveling Support for separate package, board, dimm delays Auto-configuration based on DIMM types Hierarchical IC / PCB timing-libraries Over-clock speed-bins: 1866, 2133Mhz TSMC 28n 2400Mhz IBIS buffers corresponding to Cadence DDR3/4 PHY Reference Package Cadence Design Systems, Inc. All rights reserved.
22 DDR3-design in kit Full version (Educational version): Cannot be modified for use in designs DDR3 custom-measurements and Eye-masks Generic IBIS IO buffers for DDR3 controller and Memory Basic Timing-models for different speed-bins: 800, 1333, 1600Mhz Simulation patterns and setup/hold derate-file Post-route flow with Reference Mother-board and DIMM Pre-route flow using pre-created topologies corresponding to different DIMM cards ECSet templates for guiding routing of boards Enhanced Timing-models Write-leveling Support for separate package, board, dimm delays Auto-configuration based on DIMM types Hierarchical IC / PCB timing-libraries Over-clock speed-bins: 1866, 2133Mhz TSMC 28n 2400Mhz IBIS buffers corresponding to Cadence DDR3/4 PHY Reference Package Cadence Design Systems, Inc. All rights reserved.
23 DDR3-design in kit Lite version (Web download): Abridged version available as demo-vehicle DDR3 custom-measurements and Eye-masks Generic IBIS IO buffers for DDR3 controller and Memory Basic Timing-models for different speed-bins: 800, 1333, 1600Mhz Simulation patterns and setup/hold derate-file Post-route flow with Reference Mother-board and DIMM Pre-route flow using pre-created topologies corresponding to different DIMM cards ECSet templates for guiding routing of boards Enhanced Timing-models Write-leveling Support for separate package, board, dimm delays Auto-configuration based on DIMM types Hierarchical IC / PCB timing-libraries Over-clock speed-bins: 1866, 2133Mhz TSMC 28n 2400Mhz IBIS buffers corresponding to Cadence DDR3/4 PHY Reference Package Cadence Design Systems, Inc. All rights reserved.
24 Cadence Design Systems, Inc. All rights reserved.
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