ISSN Vol.05,Issue.41 November-2016, Pages:

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1 ISSN Vol.05,Issue.41 November-2016, Pages: A Novel Design of Binary Multiplier using Partial Product Generator (PPG) MOHAMMED ABDUL KAREEM 1, MOHAMMED MUNEER KHAN 2, IMTHIAZUNNISA BEGUM 3 1 PG Scholar, Dept of EEE, VIF College of Engineering And Technology, Moinabad, Rangareddy(Dt), TS, India, makareem755@gmail.com. 2 Assistant Professor, Dept of EEE, VIF College of Engineering And Technology, Moinabad, Rangareddy(Dt), TS, India, ecehodvifcet@gmail.com. 3 HOD, Dept of EEE, VIF College of Engineering And Technology, Moinabad, Rangareddy(Dt), TS, India, ecehodvifcet@gmail.com. Abstract: Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage. Therefore, the proposed RBMPPG generates fewer partial product rows than a conventional RB MBE multiplier. Simulation results show that the proposed RBMPPG based designs significantly improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits; these reductions over previous NB multiplier designs incur in a modest delay increase (approximately 5%). The power-delay product can be reduced by up to 59% using the proposed RB multipliers when compared with existing RB multipliers. Keywords: Redundant Binary, Modified Booth Encoding, RB Partial Product Generator, RB Multiplier. I. INTRODUCTION Multiplier plays an important part in digital signal processing (DSP) system. It is used in implementation of recursive, transverse filters and discrete Fourier transforms. The performance of DSP systems is inherently affected by decision on their design regarding the allocation and the architecture of arithmetic units. Using of the large computation leads to increases in power and area of the system. In [1], a two-stage recorder which converts a number in carry save form to its MB representation. The first stage transforms the carry-save form of the input number into signed-digit form which is then recoded in the second stage and it matches the form that the MB digits request. Recently, this technique had been used for the design of high performance flexible coprocessor architecture targeting the computationally intensive DSP applications. In [2], the recoding of a redundant input form its carry-save form to the corresponding borrow-save form keeping the critical path of the multiplication operation fixed. The multiplication operation product is obtained by adding partial products presented in [3], thus the final speed of the multiplier circuits depends on the speed of the adder circuits and the number of partial products generated. Radix-8 booth encoded technique used then there are only 3 partial products and only one CSA and CLA is required to produce the final product. Through this algorithm it increases in power of the system. Based on the observation that an addition can often be subsequent to a multiplication (e.g., in symmetric FIR filters), the Multiply-Accumulator (MAC) and Multiply- Add (MAD) units were introduced [4] leading to more efficient implementations of DSP algorithms compared to the conventional ones, which use only primitive resources [5]. Several architectures have been proposed to optimize the performance of the MAC operation in terms of area occupation, critical path delay or power consumption [6], [7]. In [8], MAC components increase the flexibility of DSP data path synthesis as a large set of arithmetic operations can be efficiently mapped on the system. The fused operations are a two-term dot product and add-subtract unit. The FFT processors [9] use butterfly operations that consist of multiplications, additions, and subtractions of complex valued data. Both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating-point operations. Although the direct recording of the multiplier in its MB form leads to a more efficient implementation of the fused add-multiply (FAM) unit with RB encoding compared to the conventional one. The existing recoding schemes are based on complex manipulations in bit-level, which are implemented by dedicated circuits in gate-level. This paper focuses on the efficient design of FAM unit with RB encoding and targeting the optimization of the recoding scheme for direct shaping of the MB form of multipliers IJSETR. All rights reserved.

2 MOHAMMED ABDUL KAREEM, MOHAMMED MUNEER KHAN, IMTHIAZUNNISA BEGUM The adoption of the proposed recoding technique delivers optimized solutions for the FAM design using RB encoding enabling the targeted operator to be timing functional (no timing violations) for a larger range of frequencies. Also, under the same timing constraints, the proposed designs deliver improvements in both area and power consumption, thus outperforming the existing Modified Booth Scheme recoding solutions. Main Objective: We proposed a new RB modified partial product generator based on MBE (RBMPPG-2) is presented in this section; in this design, ECW is eliminated by incorporating it into both the two MSBs of the first partial product row and the two LSBs of the last partial product row. RB modified partial product generator. The proposed RBMPPG-2 scheme for an 8x8-bit multiplier. It is different from the scheme in where all the errorcorrecting terms are in the last row. A. RB Partial Product Generator As two bits are used to represent one RB digit, then a RBPP is generated from two NB partial products. The addition of two N-bit NB partial products X and Y using two s complement representation can be expressed as follows [6]: where is the inverse of, and the same convention is used in the rest of the paper. The composite number can be interpreted as a RB number. The RBPP is generated by inverting one of the two NB partial products and adding -1 to the LSB. Each RB digit belongs to the set - 1, 0, 1; this is coded by two bits as the pair. Note that 1 = 1. RB numbers can be coded in several ways. Table II shows one specific RB encoding, where the RB digit is obtained by performing TABLE I: MBE Scheme II. EXISTING SYSTEM Booth encoding has been proposed to facilitate the multiplication of two's complement binary numbers. It was revised as modified Booth encoding (MBE) or radix- 4 Booth encoding [18]. The MBE scheme is summarized in Table I, where stands for the multiplicand, and stands for the multiplier. The multiplier bits are grouped in sets of three adjacent bits. The two side bits are overlapped with neighboring groups except the first multiplier bits group in which it is {b1, b0, 0}. Each group is decoded by selecting the partial product shown in Table I, where 2A indicates twice the multiplicand, which can be obtained by left shifting. Negation operation is achieved by inverting each bit of A and adding 1 (defined as correction bit) to the LSB [10-13]. Methods have been proposed to solve the problem of correction bits for NB radix-4 Booth encoding (NBBE-2) multipliers. However, this problem has not been solved for RB MBE multipliers. Fig. 1. Conventional RBPP architecture for an 8-bit MBE multiplier. TABLE II: RB Encoding used in this work Both MBE and RB coding schemes introduce errors and two correction terms are required: 1) when the NB number is converted to a RB format, -1 must be added to the LSB of the RB number; 2) when the multiplicand is multiplied by -1 or -2 during the Booth encoding, the number is inverted and +1 must be added to the LSB of the partial product. A single ECW can compensate errors from both the RB encoding and the radix-4 Booth recoding. The conventional partial product architecture of an 8-bit MBE multiplier [5-6] is shown in Fig. 1, where b_ pre presents the bit position, and is generated by using an encoder and decoder (Fig. 2) [10]. An N-bit CRBBE-2 multiplier includes N/4 RBPP rows and one ECW; the ECW takes the form as follows: where i represent the ith row of the RBPPs. In a correction term is always required by RB coding. If also corrects the errors from the MBE recoding, then the correction term cancels out to 0. That is to say that if the multiplicand digit is inverted and added to 1, then is 0, otherwise is -1. The error-correcting digit is determined only by the Booth encoding, no negative encoding1, negative encoding. III. PROPOSED RBMPPG-2 The circuit diagrams of the modified partial product variables and are shown in Fig. 4. It is clear that has the longest delay path. It is well known that the inverter, the 2- input NAND gate and the transmission gate (TG) are faster than other gates. So, it is desirable to use TGs when designing the multiplexer [5-6]. As shown in Fig. 4 (a), the Fig. 2. An encoder and decoder of the MBE scheme. critical path delay (the dash line) consists of a 1-stage AND-

3 A Novel Design of Binary Multiplier using Partial Product Generator (PPG) OR-Inverter gate, a 1-stage inverter, and 2-stage TGs. Therefore, RBMPPG-2 just increases the TG delay by 1- stage compared with the MBE partial product of Fig. 3. The above discussion is only an example; the above technique can be applied to design any 2_-bit RB multipliers. It eliminates the extra ECWN/4 and saves one RBPP accumulation stage, i.e., three XOR gate delays, while only slightly increasing the delay of the partial product generation stage. In general, an N-bit RB multiplier has /4_ RBPP rows using the proposed RBMPPG-2. The partial product variable. The radix-4 Booth decoding of a PPR needs additional 3-input OR gates (Fig. 3). Therefore, the extra ECWN/4 is removed by the transformation of 4 partial product variables and one partial product row is saved in RB multipliers with any power-of-two word-length. A. Radix-4 Booth Encoding Booth encoding has been proposed to facilitate the multiplication of two's complement binary numbers. It was revised as modified Booth encoding (MBE) or radix- 4 Booth encoding. The multiplier bits are grouped in sets of three adjacent bits. The two side bits are overlapped with neighboring groups except the first multiplier bits group in which it is {b1, b0, 0}. Each group is decoded by selecting the partial product shown in Table I, where 2A indicates twice the multiplicand, which can be obtained by left shifting. Negation operation is achieved by inverting each bit of A and adding 1 (defined as correction bit) to the LSB [10-13]. Methods have been proposed to solve the problem of correction bits for NB radix-4 Booth encoding (NBBE-2) multipliers. However, this problem has not been solved for RB MBE multipliers. Fig. 3. The modified radix-4 Booth encoding and decoding scheme for PP. TABLE III: Truth Table of TABLE IV: Truth Table of B. RB Partial Product Generator As two bits are used to represent one RB digit, then a RBPP is generated from two NB partial products [1-6]. The addition of two N-bit NB partial products X and Yusing two s complement representation can be expressed as follows Both MBE and RB coding schemes introduce errors and two correction terms are required: 1) when the NB number is converted to a RB format, -1 must be added to the LSB of the RB number; 2) when the multiplicand is multiplied by -1 or -2 during the Booth encoding, the number is inverted and +1 must be added to the LSB of the partial product. A single ECW can compensate errors from both the RB encoding and the radix-4 Booth recoding. The conventional partial product architecture. C. Proposed RB Partial Product Generator The circuit diagrams of the modified partial product variables and are shown in Fig. 4. It is clear that has the longest delay path. It is well known that the inverter, the 2- input NAND gate and the transmission gate (TG) are faster than other gates. So, it is desirable to use TGs when designing the multiplexer [5-6]. As shown in Fig. 4 (a), the critical path delay (the dash line) consists of a 1-stage AND- OR-Inverter gate, a 1-stage inverter, and 2-stage TGs. Therefore, RBMPPG-2 just increases the TG delay by 1- stage compared with the MBE partial product of Fig. 4. The above discussion is only an example; the above technique can be applied to design any 2_-bit RB multipliers. It eliminates the extra ECWN/4 and saves one RBPP accumulation stage, i.e., three XOR gate delays, while only slightly increasing the delay of the partial product generation stage. In general, an N-bit RB multiplier has /4_ RBPP rows using the proposed RBMPPG-2. The partial product variables. The radix-4 Booth decoding of a PPR (PP_/ needs additional 3-input OR gates (Fig. 5). Therefore, the extra ECWN/4 is removed by the transformation of 4 partial product variables and one partial product row is saved in RB multipliers with any power-of-two word-length. D.Design of Rbmppg-2-Based High-Speed Rb Multipliers The proposed RBMPPG-2 can be applied to any 2- bit RB multipliers with a reduction of a RBPP accumulation

4 MOHAMMED ABDUL KAREEM, MOHAMMED MUNEER KHAN, IMTHIAZUNNISA BEGUM stage compared with conventional designs. Although the delay of RMPPG-2 increases by 1-stage of TG delay, the delay of one RBPP accumulation stage is significantly larger than a 1-stage TG delay. Therefore, the delay of the entire multiplier is reduced. The improved complexity, delay and power consumption are very attractive for the proposed design. A 32-bit RB MBE multiplier using the proposed RBPP generator is shown in Fig. 6. The multiplier consists of the proposed RBMPPG-2, three RBPP accumulation stages, and one RB-NB converter. Eight RBBE-2 blocks generate the RBPP; they are summed up by the RBPP reduction tree that has three RBPP accumulation stages. Each RBPP accumulation block contains RB full adders (RBFAs There are 4 stages in a conventional 32-bit RB MBE multiplier architecture; however, by using the proposed RBMPPG-2, the number of RBPP accumulation stages is reduced from 4 to 3 (i.e., a 25% reduction). These are significant savings in delay, area as well as power consumption. The improvements in delay, area and power consumption are further demonstrated in the next section by simulation. Fig.6. Block diagram of 32-bit RB multiplier using RBMPPG-2. IV. SIMULATION RESULTS Simulation results of this paper is as shown in bellow Figs.6 and 7. Fig.6. RTL Diagram Of The System. Fig.4.The circuit diagram of the modified partial product variables. Fig. 5. The modified radix-4 Booth encoding and decoding scheme for PP. Fig.7. System Response.

5 A Novel Design of Binary Multiplier using Partial Product Generator (PPG) TABLE V: Synthesis Report Advantages: High-Throughput. Less area & delay. Reduces the system complexity. Applications: High speed arithmetic computations. Fast adder. V. CONCLUSION A new modified RBPP generator has been proposed in this paper; this design eliminates the additional ECW that is introduced by previous designs. Therefore, a RBPP accumulation stage is saved due to the elimination of ECW. The new RB partial product generation technique can be applied to any 2_-bit RB multipliers to reduce the number of RBPP rows from /4 + 1_ to /4_. Simulation results have shown that the performance of RB MBE multipliers using the proposed RBMPPG-2 is improved significantly in terms of delay and area. The proposed designs achieve significant reductions in area and power consumption when the word length is at least 32 bits. The PDP can be reduced by up to 59% using the proposed RB multipliers when compared with existing RB multipliers. Hence, the proposed RBPP generation method is a very useful technique when designing area and PDP efficient power-of-two RB MBE multipliers. Future Enhancement: In this paper we modify the multiplier by increasing the number of input to the multiplier. In this multiplier design we need A and B inputs and the output is Y. In our modification these inputs are in 64 bits and the output in 128 bits. VI. REFERENCES [1] A. Avizienis, Signed-digit number representations for fast parallel arithmetic, IRE Trans. Electron. Computers, vol. EC-10, pp , [2] N. Takagi, H. Yasuura, and S. Yajima, High-speed VLSI multiplication algorithm with a redundant binary addition tree, IEEE Trans. Computers, vol. C-34, pp , [3] Y. Harata, Y. Nakamura, H. Nagase, M. Takigawa, and N. Takagi, A high speed multiplier using a redundant binary adder tree, IEEE J. Solid-State Circuits, vol. SC-22, pp , [4] H. Edamatsu, T. Taniguchi, T. Nishiyama, and S. Kuninobu, A 33 MFLOPS floating point processor using redundant binary representation, in Proc. IEEE Int. Solid- State Circuits Conf. (ISSCC), pp , [5] H. Makino, Y. Nakase, and H. Shinohara, A 8.8-ns 54x54-bit multiplier using new redundant binary architecture, in Proc. Int. Conf. Comput. Design (ICCD), pp , [6] H. Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, and K. Makino, An 8.8-ns bit multiplier with high speed redundant binary architecture, IEEE J. Solid-State Circuits, vol. 31, pp , [7] Y. Kim, B. Song, J. Grosspietsch, and S. Gillig, A carryfree 54b 54b multiplier using equivalent bit conversion algorithm, IEEE J. Solid-State Circuits, vol. 36, pp , [8] Y. He and C. Chang, A power-delay efficient hybrid carrylookahead carry-select based redundant binary to two s complement converter, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, pp , [9] G. Wang and M. Tull, A new redundant binary number to 2'scomplement number converter, in Proc. Region 5 Conference: Annual Technical and Leadership Workshop, pp , Author s Profile: Mohammed Abdul Kareem received the B.Tech degree in Electronics and Communication Engineering from Shadan College of Engineering and Technology, Peerancheru, Rangareddy (DT), T.S, India, in Currently he is pursuing M.Tech in VLSI Design from VIF college of engineering and technology, moinabad, Rangareddy (DT), T.S, India. His research interests include VLSI systems design. Mohammed Muneer Khan Received the B.Tech degree in Electronics and Communications from Jawaharlal Nehru Tecnological University, Hyderabad, T.S, India. He has Completed M.Tech in VLSI systems design from Jawaharlal Nehru Tecnological University, Hyderabad, T.S,, Telangana, India. Currently he is working as Assistant professor in VIF College of Engineering and Technology, Moinabad, Rangareddy (DT), T.S, India.

6 MOHAMMED ABDUL KAREEM, MOHAMMED MUNEER KHAN, IMTHIAZUNNISA BEGUM Imthiazunnisa Begum Received the B.Tech degree in Electronics and Communications from Jawaharlal Nehru Tecnological University, Hyderabad, T.S, India. She has Completed M.Tech in VLSI System Design from Jawaharlal Nehru Technological University, Hyderabad, T.S, India. Currently she is working as Head of the department in VIF college of engineering and Technology, Moinabad, Rangareddy (DT), T.S, India.