TYPICAL APPLICATION. LTC Bit Rail-to-Rail Micropower DAC with Clear Input DESCRIPTION FEATURES APPLICATIONS

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1 12-Bit Rail-to-Rail Micropower with Clear Input FEATRES SO-8 Package 12-Bit Resolution Buffered True Rail-to-Rail Voltage Output Asynchronous Clear Input Built-In Reference Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface Power-On Reset Clears to V 3-Wire Cascadable Serial Interface Maximum DNL Error:.5LSB Low Cost APPLICATIONS Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones DESCRIPTION The LTC 1456 is a complete single supply, rail-to-rail voltage output, 12-bit digital-to-analog converter () in an SO-8 package. It includes a rail-to-rail output buffer amplifier and an easy-to-use 3-wire cascadable serial interface. The LTC1456 includes a CLR pin that asynchronously clears the to zero scale. The LTC1456 has an internal 2.48V reference and a fullscale output of 4.95V. It operates on a 4.5V to 5.5V supply, dissipating 2.2mW. The low power supply current and the space saving SO-8 package make the LTC1456 ideal for battery-powered applications., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION Functional Block Diagram: 12-Bit Rail-to-Rail with Clear Input 8 2 D IN 4.5V TO 5.5V 2.48V.5 Differential Nonlinearity vs Input Code µp BIT SHIFT REG AND LATCH 12-BIT + V OT 7 RAIL-TO-RAIL VOLTAGE OTPT DNL ERROR (LSB) 4 D OT TO OTHER S 6 CLR POWER-ON RESET GND TA CODE 1456 TA2 1

2 ABSOLTE MAXIMM RATINGS W W W to GND....5V to 7.5V Logic Inputs to GND....5V to 7.5V V OT....5V to +.5V Maximum Junction Temperature C to 125 C Operating Temperature Range LTC1456C... C to 7 C LTC1456I... 4 C to 85 C Storage Temperature Range C to 15 C Lead Temperature (Soldering, 1 sec)... 3 C PACKAGE/ORDER I FOR D IN D OT N8 PACKAGE 8-LEAD PDIP TOP VIEW V OT CLR GND S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 125 C, θ JA = 1 C/W (N8) T JMAX = 125 C, θ JA = 15 C/W (S8) Consult factory for Military grade parts. W ATIO ORDER PART NMBER LTC1456CN8 LTC1456IN8 LTC1456CS8 LTC1456IS8 S8 PART MARKING I ELECTRICAL CHARACTERISTICS = 4.5V to 5.5V, V OT unloaded, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Resolution 12 Bits DNL Differential Nonlinearity Guaranteed Monotonic (Note 1) ±.5 LSB INL Integral Nonlinearity T A = 25 C ±3.5 LSB (Note 1) ±4 LSB V OS Offset Error T A = 25 C ±12 mv ±18 mv V OS TC Offset Error Temperature ±15 µv/ C Coefficient V FS Full-Scale Voltage T A = 25 C V V V FS TC Full-Scale Voltage ± 24 ppm/ C Temperature Coefficient Power Supply Positive Supply Voltage For Specified Performance V I CC Supply Current (Note 4) µa Op Amp DC Performance AC Performance Short-Circuit Current Low V OT Shorted to GND 12 ma Short-Circuit Current High V OT Shorted to 12 ma Output Impedance to GND Input Code = 4 12 Ω Voltage Output Slew Rate (Note 2).4 1. V/µs Voltage Output Settling Time (Notes 2, 3) to ±.5LSB 14 µs Digital Feedthrough.3 nv s 2

3 ELECTRICAL CHARACTERISTICS = 4.5V to 5.5V, V OT unloaded, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Digital I/O V IH Digital Input High Voltage 2.4 V V IL Digital Input Low Voltage.8 V V OH Digital Output High Voltage I OT = 1mA, D OT Only 1. V V OL Digital Output Low Voltage I OT = 1mA, D OT Only.4 V I LEAK Digital Input Leakage = 5V, V IN = GND to ±1 µa C IN Digital Input Capacitance Guaranteed by Design. Not Subject to Test. 1 pf Switching t 1 D IN Valid to Setup 4 ns t 2 D IN Valid to Hold ns t 3 High Time 4 ns t 4 Low Time 4 ns t 5 Pulse Width 5 ns t 6 LSB to 4 ns t 7 Low to 2 ns t 8 D OT Output Delay C LOAD = 15pF, = 5V 15 ns t 9 Low to Low 2 ns t 1 CLR Pulse Width 65 ns The denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 495 (full scale). Note 2: Load is 5kΩ in parallel with 1pF. Note 3: switched between all 1s and the code corresponding to V OS for the part. Note 4: Digital inputs at V or. 3

4 TYPICAL PERFORMANCE CHARACTERISTICS W Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Minimum Supply Headroom for Full Output Swing vs Load Current V OT < 1LSB CODE: ALL 1s V OT = 4.95V DNL (LSB) INL ERROR (LSB) V OT (V) CODE CODE LOAD CRRENT (ma) 1456 G G G3 OTPT PLL-DOWN VOLTAGE (mv) Minimum Output Voltage vs Output Sink Current 125 C 25 C 55 C SPPLY CRRENT (ma) Supply Current vs Logic Input Voltage ALL DIGITAL INPTS TIED TOGETHER OTPT SWING (V) Output Swing vs Load Resistance CODE: ALL s R L OTPT SINK CRRENT (ma) LOGIC INPT VOLTAGE (V) 1 1 1k 1k LOAD RESISTANCE (Ω) 1456 G G G6 OTPT SWING (V) Output Swing vs Load Resistance 4.5 CODE: ALL 1s R L.5 OFFSET VOLTAGE (mv) Offset Voltage vs Temperature SPPLY CRRENT (µa) Supply Current vs Temperature = 5.5V = 5V 47 = 4.5V k 1k LOAD RESISTANCE (Ω) TEMPERATRE ( C) TEMPERATRE ( C) 1456 G G G9 4

5 PIN FNCTIONS (Pin 1): The Serial Interface Clock. Internal Schmitt trigger on this input allows direct optocoupler interface. D IN (Pin 2): The Serial Interface Data. Data on the D IN pin is latched into the shift register on the rising edge of the serial clock. (Pin 3): The Serial Interface Enable and Load Control. When is low the signal is enabled, so the data can be clocked in. When is pulled high, data is loaded from the shift register into the register, updating the output. When is high the is disabled internally. D OT (Pin 4): The Output of the Shift Register Which Becomes Valid on the Rising Edge of the Serial Clock. GND (Pin 5): Ground. CLR (Pin 6): The Clear Input. When pulled low, this pin asynchronously clears the internal shift and registers to zero scale. Should be tied high for normal operation. V OT (Pin 7): The Buffered Output. (Pin 8): The Positive Supply Input. 4.5V 5.5V. Requires a bypass capacitor to ground. BLOCK DAGRA I W V 8 D IN 2 LD 12-BIT SHIFT REGISTER REGISTER 12-BIT + 7 V OT 3 POWER-ON RESET 6 CLR D OT 4 5 GND 1146 BD W W TI I G DIAGRA t 1 t 2 t 6 t 7 t 4 t 3 t 9 D IN B PREVIOS WORD B11 MSB B1 B1 B LSB t 8 t 5 D OT B11 PREVIOS WORD B1 B1 B B11 CRRENT WORD 1456 TD 5

6 DEFI ITIO S Resolution (n): Resolution is defined as the number of digital input bits, n. It defines the number of output states (2 n ) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (V FS ): This is the output of the when all bits are set to 1. Voltage Offset Error (V OS ): The theoretical voltage at the output when the is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below zero. If the offset is negative, the output will remain near V resulting in the transfer curve shown in Figure 1. The offset of the part is measured at the code that corresponds to the maximum offset specification: V OS = V OT [(Code V FS )/(2 n 1)] Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes. LSB = (V FS V OS )/(2 n 1) = (V FS V OS )/495 LSB = 4.95/495 = 1mV Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end-points of the transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between full scale and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated as follows: INL = [V OT V OS (V FS V OS )(code/495)]/lsb V OT = The output voltage of the measured at the given input code Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = ( V OT LSB)/LSB V OT = The measured voltage difference between two adjacent codes Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nv)(sec). OTPT VOLTAGE NEGATIVE OFFSET V CODE 1456 F1 Figure 1. Effect of Negative Offset 6

7 OPERATIO LTC1456 Serial Interface The data on the D IN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The register loads the data from the shift register when is pulled high. The is disabled internally when is high. Note: must be low before is pulled low to avoid an extra internal clock pulse. When CLR is pulled low it asynchronously resets the shift and registers to all zeros. The buffered output of the 12-bit shift register is available on the D OT pin which swings from GND to. Multiple LTC1456s may be daisy-chained together by connecting the D OT pin to the D IN pin of the next chip, while the and signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the signal is pulled high to update all of them simultaneously. Voltage Output The LTC1456's rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range while pulling to within 3mV of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 4Ω when driving a load to the rails. The output can drive 1pF without going into oscillation. TYPICAL APPLICATION The circuit below shows a digitally programmable current source from an external voltage source using an external op amp, an LT 177 and an NPN transistor (2N344). Any digital word from to 495 is loaded into the LTC1456 and its output correspondingly swings from V to 4.95V. In the configuration shown, this voltage will be forced across the resistor R A. If R A is chosen to be 41Ω the output current will range from ma at zero scale to 1mA at full scale. The minimum voltage for V S is determined by the load resistor R L and Q1 s V CESAT voltage. With a load resistor of 5Ω, the voltage source can be as low as 5V. µp 12-Bit 5V Single Supply Voltage Output TO NEXT FOR DAISY-CHAINING D IN 4.5V TO 5.5V LTC1456 D OT CLR GND V OT.1µF OTPT V TO 4.95V 1456 TA3 Digitally Programmable Current Source 5V.1µF V S + 5V TO 1V FOR R L 5Ω µp CLR D IN LTC1456 GND V OT + LT177 D R L I OT = IN 4.95 ma TO 1mA 496 R A Q1 2N344 R A 41Ω 1456 TA4 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7

8 PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted ( ) N8 Package 8-Lead PDIP (Narrow.3) (LTC DWG # ) ( ).13 ±.5 (3.32 ±.127).4* (1.16) MAX ( ) ( ).65 (1.651) TYP.5 (.127) MIN.1 ±.1 (2.54 ±.254) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.1 INCH (.254mm).125 (3.175) MIN.18 ±.3 (.457 ±.76).15 (.38) MIN.255 ±.15* (6.477 ±.381) N ( ).1.2 ( ) 45 8 TYP S8 Package 8-Lead Plastic Small Outline (Narrow.15) (LTC DWG # ) ( ).4.1 ( ) * ( ) ( ) * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.152mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.1" (.254mm) PER SIDE.5 (1.27) BSC ( ) ** ( ) SO8 695 RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC1257 Single 12-Bit V OT, Full Scale: 2.48V, : 4.75V to 15.75V, 5V to 15V Single Supply, Complete V OT in Reference Can Be Overdriven p to 12V, i.e., FS MAX = 12V SO-8 Package LTC1446/LTC1446L Dual 12-Bit V OT s in SO-8 Package LTC1446: = 4.5V to 5.5V, V OT = V to 4.95V LTC1446L: = 2.7V to 5.5V, V OT = V to 2.5V LTC145/LTC145L Single 12-Bit V OT s with Parallel Interface LTC145: = 4.5V to 5.5V, V OT = V to 4.95V LTC145L: = 2.7V to 5.5V, V OT = V to 2.5V LTC1451 Single Rail-to-Rail 12-Bit, Full Scale: 4.95V, : 4.5V to 5.5V, Same as LTC1456 Except REF Out Pin Replaces Internal 2.48V Reference Brought Out to Pin CLR Pin LTC1452 Single Rail-to-Rail 12-Bit V OT Multiplying, : 2.7V to 5.5V Low Power, Multiplying V OT with Rail-to-Rail Buffer Amplifier in SO-8 Package LTC1453 Single Rail-to-Rail 12-Bit V OT, Full Scale: 2.5V, : 2.7V to 5.5V 3V, Low Power, Complete V OT in SO-8 Package LTC1454/LTC1454L Dual 12-Bit V OT s in SO-16 Package with Added Functionality LTC1454: = 4.5V to 5.5V, V OT = V to 4.95V LTC1454L: = 2.7V to 5.5V, V OT = V to 2.5V LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output s with Added Functionality LTC1458: = 4.5V to 5.5V, V OT = V to 4.95V LTC1458L: = 2.7V to 5.5V, V OT = V to 2.5V 8 Linear Technology Corporation 163 McCarthy Blvd., Milpitas, CA (48) FAX: (48) TELEX: fs, sn1456 LT/TP 697 7K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 1996