CS Computer Architecture Spring Week 10 & 11: 5.4

Transcription

1 CS 35 Computer Architecture Spring 28 Week & : 5.4 Materials adapted from Kevin Schaffer and Mary Jane Irwin ( [adapted from D. Patterson slides] CS 35 Ch5.36 Steinfadt, SP8 KSU

2 Head s Up This week s material and next week s More on single cycle datapath design and exam review - ing assignment PH: , Multicycle MIPS datapath implementation - ing assignment PH: , multicycle MIPS datapath and control path implementation Reminders Project 2 is posted and due on 4/22 Exam #2 is Tuesday, April 5 CS 35 Ch5.37 Steinfadt, SP8 KSU

3 Review: Creating a Datapath from the Parts Assemble the datapath elements, add control lines as needed, and design the control path Fetch, decode and execute each instructions in one clock cycle single cycle design no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., one reason why we have a separate Instruction and Data ) to share datapath elements between two different instruction classes need multiplexors at the input of the shared elements with control lines to do the selection Cycle time is determined by length of the longest (slowest) path CS 35 Ch5.38 Steinfadt, SP8 KSU

4 Putting it All Together: A Simple MIPS Datapath Design 4 Shift left 2 PCSrc PC ress Instruction Instruction RegWrite r Register r 2 File Write r Data Data 2 Src control ovf zero ress MemWrite Data Data MemtoReg Sign 6 Extend 32 Mem CS 35 Ch5.39 Steinfadt, SP8 KSU

5 ing the Control Selecting the operations to perform (, Register File and read/write) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction Observations op field always in bits 3-26 addr of two registers to be R-type: op rs rt rd shamt funct I-Type: op rs rt address offset read are always specified by the rs and rt fields (bits 25-2 and 2-6) base register for lw and sw always in rs (bits 25-2) addr. of register to be written is in one of two places in rt (bits 2-6) for lw; in rd (bits 5-) for R-type instructions offset for beq, lw, and sw always in bits 5- CS 35 Ch5.4 Steinfadt, SP8 KSU

6 Control In order to simplify design of the main control unit we give the its own control logic The control block takes a 2-bit control signal (Op) and the instruction's funct field Generates a 4-bit operation code for CS 35 Ch5.4 Steinfadt, SP8 KSU

7 (Almost) Complete Single Cycle Datapath 4 Shift left 2 PCSrc RegDst RegWrite Src MemWrite MemtoReg PC ress Instruction Instr[3-] Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 File Write r Data Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Mem Instr[5-] Op CS 35 Ch5.42 Steinfadt, SP8 KSU

8 Control 's operation based on instruction type and function code Control Inputs Function AND OR Subtract Set on less than NOR CS 35 Ch5.43 Steinfadt, SP8 KSU

9 Control Signals, Con t Controlling the uses of multiple decoding levels main control unit generates the Op bits control unit generates control bits Instr op lw sw beq R-type R-type R-type R-type R-type R-type funct xxxxxx xxxxxx xxxxxx Op add add subtract add subtract AND OR NOR slt action control CS 35 Ch5.45 Steinfadt, SP8 KSU

10 CS 35 Ch5.46 Steinfadt, SP8 KSU Control Truth Table control 3 F F F2 F3 F4 F5 Op Op control control control 2

11 Control Unit Control unit takes an instruction as input and produces control signals as output Types of control signals Multiplexor selector signals Write enables for state elements Control signals for other blocks (, etc.) In a single-cycle datapath the control unit is simple, just look up instruction in a table CS 35 Ch5.47 Steinfadt, SP8 KSU

12 Control Signals RegDst: Selects either rd or rt as the destination register RegWrite: The value on the write data port will be written into the register specified by the write register input when asserted Op: Selects operation Src: Selects the second input to be either the second register output or the signextended immediate value CS 35 Ch5.48 Steinfadt, SP8 KSU

13 Control Signals PCSrc: Selects new PC as either PC + 4 or the output of the branch target adder Logical AND of Branch control signal and Zero output Mem/MemWrite: Causes data memory to perform a read/write operation when asserted MemtoReg: Selects either the output or the data memory output as the data input into the register file CS 35 Ch5.49 Steinfadt, SP8 KSU

14 Control Signals (Rformat) lw sw beq Op Src Branch Mem MemWrite MemtoReg x x RegDst x x RegWrite CS 35 Ch5.5 Steinfadt, SP8 KSU

15 (Almost) Complete Datapath with Control Unit 4 Op Instr[3-26] Control Unit Branch Src Shift left 2 PCSrc Mem MemtoReg MemWrite PC ress Instruction Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 File Write r RegWrite Data Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CS 35 Ch5.5 Steinfadt, SP8 KSU

16 Main Control Unit Instr RegDst Src MemReg RegWr MemRd MemWr Branch Op R- type lw sw beq Completely determined by the instruction opcode field Note that a multiplexor whose control input is has a definite action, even if it is not used in performing the operation CS 35 Ch5.52 Steinfadt, SP8 KSU

17 R-type Instruction Data/Control Flow 4 Op Instr[3-26] Control Unit Branch Src Shift left 2 PCSrc Mem MemtoReg MemWrite PC ress Instruction Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 File Write r RegWrite Data Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CS 35 Ch5.53 Steinfadt, SP8 KSU

18 Store Word Instruction Data/Control Flow 4 Op Instr[3-26] Control Unit Branch Src Shift left 2 PCSrc Mem MemtoReg MemWrite PC ress Instruction Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 File Write r RegWrite Data Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CS 35 Ch5.55 Steinfadt, SP8 KSU

19 Load Word Instruction Data/Control Flow 4 Op Instr[3-26] Control Unit Branch Src Shift left 2 PCSrc Mem MemtoReg MemWrite PC ress Instruction Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 File Write r RegWrite Data Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CS 35 Ch5.57 Steinfadt, SP8 KSU

20 Load Word Instruction Data/Control Flow 4 Op Instr[3-26] Control Unit Branch Src Shift left 2 PCSrc Mem MemtoReg MemWrite PC ress Instruction Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 File Write r RegWrite Data Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CS 35 Ch5.58 Steinfadt, SP8 KSU

21 Branch Instruction Data/Control Flow 4 Op Instr[3-26] Control Unit Branch Src Shift left 2 PCSrc Mem MemtoReg MemWrite PC ress Instruction Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 File Write r RegWrite Data Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CS 35 Ch5.59 Steinfadt, SP8 KSU

22 Main Control Unit Instr R-type lw sw beq RegDst Src MemReg RegWr MemRd MemWr Branch Op Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design (could have to be or could be a (don t care)) CS 35 Ch5.6 Steinfadt, SP8 KSU

23 Control Logic CS 35 Ch5.62 Steinfadt, SP8 KSU

24 Review: Handling Jump Operations Jump operation have to replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits 3 J-Type: op jump target address 4 4 PC ress Instruction Instruction 26 Shift left 2 28 Jump address CS 35 Ch5.63 Steinfadt, SP8 KSU

25 ing the Jump Operation 4 Instr[25-] 26 Op Instr[3-26] Shift left 2 Control Unit 28 Branch 32 PC+4[3-28] Jump Src Shift left 2 PCSrc Mem MemtoReg MemWrite PC ress Instruction Instr[3-] RegDst Instr[25-2] Instr[2-6] Instr[5 -] r Register r 2 File Write r RegWrite Data Data 2 ovf zero ress Data Data Instr[5-] Sign 6 Extend 32 control Instr[5-] CS 35 Ch5.64 Steinfadt, SP8 KSU

26 Main Control Unit Instr RegDst Src MemReg RegWr MemRd MemWr Branch Op Jump R-type lw sw beq j Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design CS 35 Ch5.66 Steinfadt, SP8 KSU

27 Functional Unit Use Instruction class Functional units used by instruction class Instr Mem Reg File Reg File Load Instr Mem Reg File Data Mem Reg File Store Instr Mem Reg File Data Mem Branch Instr Mem Reg File Jump Instr Mem Units: 2 ps and adders: ps Register File (R or W): 5 ps CS 35 Ch5.68 Instruction Mix: 25% loads % stores 5% branches 5% jumps 45% instructions Steinfadt, SP8 KSU

28 Instruction Critical Paths Instructio n class Time / Functional units used by instruction class Instr Mem Reg File Reg File Total Load Instr Mem Reg File Data Mem Reg File Store Instr Mem Reg File Data Mem Branch Instr Mem Reg File Jump Instr Mem Assume negligible delays for muxes, control unit, sign extend, PC access, shift left 2, wires Instruction Mix: Units: 2 ps 25% loads % stores and adders: ps 5% branches 5% jumps Register File (R or W): 5 ps 45% instructions CS 35 Ch5.69 Steinfadt, SP8 KSU

29 Performance comparison Compare CPI vs. variable clock cycle performance CPU Execution Time = IC x CPI x Clock cycle time Simplify: CPU execution time = IC x Clock cycle time CPU clock cycle for variable length clock = IC x CPU clock cycle single clock = CPU clock cycle single clock = IC x CPU clock cycle variable clock CPU clock cycle variable clock CS 35 Ch5.7 Steinfadt, SP8 KSU

30 Single Cycle Implementation Cycle Time Unfortunately, though simple, the single cycle approach is not used because it is very slow Clock cycle must have the same length for every instruction What is the longest (slowest) path (slowest instruction)? CS 35 Ch5.73 Steinfadt, SP8 KSU

31 Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be timed to accommodate the slowest instr especially problematic for more complex instructions like floating point multiply Clk Cycle Cycle 2 lw sw Waste May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but It is simple and easy to understand CS 35 Ch5.74 Steinfadt, SP8 KSU