design a 1-bit ALU using and gate, or gate, a full adder, and a mux

Transcription

1 1 ISA 2 design a fast ALU for the MIPS ISA requirements? support the arithmetic/logic operations: add, addi addiu, sub, subu, and or, andi, ori, xor, xori, slt, slti, sltu, sltiu design a multiplier design a divider design a 1-bit ALU using and gate, or gate, a full adder, and a mux ISA 3 4 design a 32-bit ALU by cascading 32 1-bit ALUs a 1-bit ALU performing AND, OR, addition and subtraction

2 5 6 include a less input for set-on-less-than (slt) design the most significant bit ALU most significant bit need to do more work (detect overflow and MSB can be used for slt ) how to detect an overflow overflow = carryin{msb} xor carryout{msb] overflow = 1 ; means overflow overflow = 0 ; means no overflow set-on-less-than slt $1, $2, $3; if $2 < $3 then $1 = 1, else $1 = 0 ; if MSB of $2 - $3 is 1, then $1 = 1 ; 2 s comp. MSB of a negative no. is a 1-bit ALU for the MSB A 32-bit ALU constructed from 32 1-bit ALUs

3 A 32-bit ALU with a zero detector 9 10 ALU control lines i.e., selection signals for the mux ALU control lines function 000 and 001 or 110 sub 111 set-on-less-than Critical path of 32-bit ripple carry adder is 32 x carry propagation delay How to solve this problem design trick : use more hardware design trick : look ahead, peek carry look adder (CLA) CLA a b cout nothing happen 0 1 cin propagate cin 1 0 cin propagate cin generate propagate = a + b; generate = ab 11 ALU Symbol for MIPS 12 CLA using 4-bit as an example two 4-bit numbers: a3a2a1a0, b3b2b1b0 p0 = a0 + b0; g0 = a0b0 c1 = g0 + p0c0 c2 = g1 + p1c1 c3 = g2 + p2c2 c4 = g3 + p3c3 larger CLA adders can be constructed by cascading 4- bit CLA adders other adders: carry select adder, carry skip adder a b ALU operation ALU ALU Control Lines Function 000 And 001 Or 010 Add 110 Subtract 111 Set-on-less-than (control lines) zero result overflow carryout

4 Design Process 13 Multiplier 14 Divide and Conquer using simple components glue simple components together work on the things you know how to do. The unknown will become obvious as you make progress Successive Refinement multiplier design divider design paper and pencil method multiplicand multiplier product n bits x m bits = m+n bits binary : 0 place 0 1 place a copy of multiplicand Multiply Hardware Version 1 15 Multiply Algorithm Version bits x 32 bits; using 64-bit multiplicand reg. 64 bit ALU, 64 bit product reg. 32 bit multiplier multiplicand shift left 64 bits shift right 64-bit ALU multiplier 1. test multiplier0 1.a if multiplier0 = 1, add multiplicand to product and place result in product register 2. shift the multiplicand left 1 bit 3. shift the multiplier right 1 bit 4. 32nd repetition? if yes done if no go to 1. product write 64 bits control

5 Multiply Algorithm Version 1 Example 17 Multiplier Algorithm Version 1 18 iter. step multiplier multiplicand product observations from version 1 1/2 bits in multiplicand always 0 use 64-bit adder is wasted 0 s inserted into multiplicand as shifted left, least significant bits of the product doesnot change once formed 3 steps per bit shift product to right instead of shifting multiplicand to left? Multiply Hardware Version 2 19 Multiply Algorithm Version bit multiplicand reg. 32-bit ALU, 64-bit product reg. 32- bit multiplier reg multiplicand 32-bit ALU product shift right write multiplier shift right control 1. test multiplier0 1a. if multiplier0 = 1 add multiplicand to the left half of product and place the result in the left half of product register; 2. shift product reg. right 1 bit 3. shift multiplier reg. right 1 bit 4. 32nd repetition? if yes done if no, go to 1.

6 Multiply Algorithm Version 2 Example 21 Multiply Version 2 22 iter. step multiplier multiplicand product Observations product reg. wastes space that exactly matches the size of multiplier 3 steps per bit combine multiplier register and product register Multiply Hardware Version 3 23 Multiply Algorithm Version bit multiplicand register, 32-bit ALU, 64-bit product register, multiplier reg is part of product register 32 bit ALU multiplicand product (multiplier) shift right control 1. test product0 1a. if product0 = 1 add multiplicand to the left half of product and place the result in the left half of product register 2. shift product register right 1 bit 3. 32nd repetition? if yes, done if no, go to 1.

7 Multiply Algorithm Version 3 Example 25 Multiply Algorithm Version 3 26 iter. step multiplicand product Observations 2 steps per bit because of multiplier and product in one register, shift right 1 bit once (rather than twice in version 1 and version 2) MIPS registers Hi and Li correspond to left and right half of product MIPS has instruction multu How about signed numbers in multiplication? method 1: keep the sign of both numbers and use the magnitude for multiplication, after 32 repetitions, then change the product to appropriate sign. method 2: Booth s algorithm Booth s algorithm is more elegant in signed number multiplications Booth s algorithm uses the same hardware as version 3 Booth s Algorithm 27 Booth s Algorithm 28 Motivation for Booth s Algorithm is speed example 2 x 6 = 0010 x 0110 normal approach Booth s approach Booth s approach : replace a string of 1s in multiplier by two actions action 1: beginning of a string of 1s, subtract multiplicand action 2: end of a string of 1s, add multiplicand end of run middle of run beginning of run current bit bit to the right explanation action (previous bit) 1 0 beginning of a run of 1s sub. mult d from left half of product 1 1 middle of a run no arithmetic oper. 0 1 end of a run add mul d to left half of product 0 0 middle of a run of 0s no arith. operation.

8 Booth s Algorithm Example 29 Divide Algorithm 30 iteration step multiplicand product Paper and pencil quotient divisor dividend remainder (modulo ) Divide Hardware Version 1 31 Divide Algorithm Version bit divisor reg., 64-bit ALU, 32-bit quotient reg. 64-bit remainder register 64-bit ALU remainder dividor write shift right control quotient shift left start: place dividend in remainder 1. sub. divisor from the remainder and place the result in remainder 2. test remainder 2a. if remainder >= 0, shift quotient to left setting the new rightmost bit to 1 2b. if remainder <0, restore the original value by adding divisor to remainder, and place the sum in remainder. shift quotient to left and setting new least significant bit 0 3. shift divisor right 1 bit 4. n+1 repetitions? if yes, done, if no, goto 1.

9 Divide Algorithm Version 1 example 33 Divide Algorithm Version 1 34 iter. step quotient divisor remainder Observations 1/2 bits in divisor always 0 1/2 of divisor is wasted 1/2 of 64-bit ALU is wasted Possible improvement instead of shifting divisor to right, shifting remainder to left? first step can not produce a 1 in quotient, so switch order to shift first and then subtract. This can save one iteration Divide Hardware Version 2 35 Divide Algorithm Version bit divisor reg. 32-bit ALU, 32-bit quotient reg., 64-bit remainder reg. divisor 32-bit ALU shift left remainder quotient shift left control start: place dividend in remainder 1. shift remainder left 1 bit 2. sub. divisor from the remainder and place the result in remainder 3. test remainder 3a. if remainder >= 0, shift quotient to left setting the new rightmost bit to 1 3b. if remainder <0, restore the original value by adding divisor to the left half of remainder, and place the sum in the left of the remainder. also shift quotient to left and setting new least significant bit 0 4. n repetitions? if yes, done, if no, goto 1.

10 Divide Algorithm Version 2 Example 37 Divide Algorithm Version 2 38 iter. step quotient divisor remainder Observations 3 steps (shift remainder left, subtract, shift quoient left) Further improvement (version 3) eliminating quotient register by combining with remainder register as shifted left therefore loop contains only two steps, because the shift of remainder is shifting the remainder in the left half and the quotient in the right half at the same time consequence of combining the two registers together is the remainder shifted one time unnecessary at the last iteration final correction step: shift back the remainder in the left half of the remainder register (i.e., shift right 1 bit of remainder only) Divide Hardware Version 3 39 Divide Algorithm Version bit divisor register, 32-bit ALU, 64-bit remainder register, 0-bit quotient register (quotient bit shifts into remainder register, as remainder register shifts left) 32-bit ALU divisor 32bits remainder, quotient 64-bit control start: place dividend in remainder 1. shift remainder left 1 bit 2. sub. divisor from the remainder and place the result in remainder 3. test remainder 3a. if remainder >= 0, shift remainder to left setting the new rightmost bit to 1 3b. if remainder <0, restore the original value by adding divisor to the left half of remainder, and place the sum in the left of the remainder. also shift remainder to left and setting new least significant bit 0 4. n repetitions? if yes, done, if no, goto 1.

11 Divide Algorithm Version 3 Example 41 Divide Algorithm Version 3 42 iter. step divisor remainder Observations same hardware as multiply, need a 32-bit ALU to add and subtract and a 64-bit register to shift left and right divide algorithm version 3 is called restoring division algorithm for unsigned numbers Signed numbers divide simplest method» remember signs of dividend and divisor, make postive, and finally complement quotient and remainder as necessary» dividend and remainder must have the same sign» quotient is negative if dividend sign and divisor sign disagree SRT (named after three persons) method» an efficient algorithm Floating Point Numbers 43 Floating Point Numbers 44 What can be represented in N bits? unsigned 2 s compl. 1 s comp. BCD How about very small numbers, very large numbers rationals, irrationals transcendentals Mantissa (aka Significand), Exponent (using radix of 10) 6.12 x S E M IEEE standard F.P. ±1.M x 2 E-127 single precision S(1bit), E(8 bits), M(23 bits) mantissa = sign + magnitude; magnitude is normalized with hidden integer bit: 1.M exponent = E -127 (excess 127), 0 < E < 255 a FP number N = (-1) S 2 (E-127) (1.M) 0 = =

12 Floating Point Numbers 45 Floating Point Numbers 46 Single Precision FP numbers = = 7 = Single precision FP number What is the smallest number in magnitude? (1.0) What is the largest number in magnitude? ( ) binary = ( ) Floating Point Numbers 47 Floating Point Numbers 48 single precision FP numbers Exponent Significand Object represented nonzero denormalized numbers 1 to 254 anything floating point numbers infinite 255 nonzero NaN (Not A Number) Double precision 64 bits total» 52-bit significand» 11-bit exponent (excess 1023 bias) Number is: (-1) s (1.M) x 2 E-1023 other topics in FP numbers 1. extra bits for rounding 2. guard bit, sticky bit 3. algorithms for FP numbers

13 Basic Addition Algorithm 49 Addition Example 50 Steps for Y + X, assuming Y >= X 1. Align binary points (denormalize smaller number) a. compute Diff = Exp(Y) - Exp(X); Exp = Exp(Y) b. Sig(X) = Sig(X) >> Diff 2. Add the aligned components Sig = Sig(X) + Sig(Y) 3. Normalize the sum 1. shift Sig right/left until leading bit is 1; decrementing or incrementing Exp. 2. Check for overflow in Exp 3. Round 4. repeat step 3 it not still normalized 4-bit significand x x 2 2 align binary points (denormalize smaller number) x x 2 3 Add the aligned components x 2 3 Normalize the sum x 2 4 No overflow, no rounding Another Addition Example 51 Accuracy and Rounding x x 1 4-bit significand; extra bit needed for accuracy 1. Align binary point: x x Subtract the aligned components x Normalize x 2 2 = 4.75 Without extra bit, the result would be x 2 3 = = 4.5, which is off by This is too much! Want arithmetic to be fully precise IEEE 754 keeps two extra digits on the right during intermediate calculations (guard digit, round digit) Alignment step can cause data to be discarded (shifted out on right) 2.56 x x x x x 10 2 Round Answer = 2.37 x 10 2 Guard Without using Guard and Round digits, Answer would be 2.36 x 10 2

14 Pentium Bug Pentium FP divide uses SRT algotithm for divide implementation using PLA, five divisors omitted from PLA (1.0001, , , , ) pentium table uses 7 bits of remainder and 4 bits of divisor = 2048 entries FP divisors neas intergers 3, 9,15, 21, 27 are dangerous Scientists suspect errors and report on Internet Sep Intel discoveries bug in Pentium in June 1994, takes months to fix (4 to 5 million Pentiums with bug) Intel press release Nov 1994, Most engineers and financial analysts need only 4 or 5 digits. Error occurs at the 9th digit. Only mathematicans should be concerned Intel claims error happens once in years IBM claims error happens once in 24 days, Ban Pentium Sales Intel says It is just a FLAW, Dammit, not a BUG Well it takes nearly 300 correct codes to fix a FLAW. Jan. 1995: Intel writes down $500M to cover replacement costs 53