5-V Low Drop Fixed Voltage Regulator TLE 4270

Transcription

1 5-V Low Drop Fixed Voltage Regulator TLE 427 Features Output voltage tolerance ±2% 65 ma output current capability Low-drop voltage Reset functionality Adjustable reset time Suitable for use in automotive electronics Integrated overtemperature protection Reverse polarity protection Input voltage up to 42 V Overvoltage protection up to 65 V ( 4 ms) Short-circuit proof Wide temperature range ESD protection > 4 V P-TO P-TO Functional Description This device is a 5-V low drop fixed-voltage regulator. The maximum input voltage is 42 V (65 V, 4 ms). Up to an input voltage of 26 V and for an output current up to 65 ma it regulates the output voltage within a 2% accuracy. The short circuit protection limits the output current of more than 65 ma. The device incorporates overvoltage protection and a temperature protection which turns off the device at high temperatures. P-TO P-TO P-TO Type Ordering Code Package TLE 427 Q67-A929 P-TO TLE 427 S Q67-A9243 P-TO TLE 427 G Q676-A921 P-TO TLE 427 D Q676-A936 P-TO , P-TO Data Sheet 1 Rev. 1.6,

2 P-TO (P-TO22-5-8) P-TO (P-TO22-5-1) P-TO (P-TO22-5-2) 1 5 Ι RO D GND Q AEP P-TO252-5 (D-PAK) GND Ι RO D GND Q AEP1923 Ι GND Q RO D AEP Ι RO D Q AEP258 Figure 1 Pin Configuration (top view) Table 1 Pin Symbol Function Pin Definitions and Functions 1 I Input; block to ground directly at the IC with a ceramic capacitor. 2 RO Reset Output; the open collector output is connected to the 5-V output via an integrated resistor of 3 kω. 3 GND Ground; internally connected to heatsink. 4 D Reset Delay; connect a capacitor to ground for delay time adjustment. 5 Q 5-V Output; block to ground with 22 µf capacitor, ESR < 3 Ω. Data Sheet 2 Rev. 1.6,

3 Circuit Description The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of a series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. The IC also incorporates a number of internal circuits for protection against: Overload Overvoltage Overtemperature Reverse polarity Application Description The IC regulates an input voltage in the range of 5.5 V < V I < 36 V to V Q,nom = 5. V. Up to 26 V it produces a regulated output current of more than 65 ma. Above 26 V the save-operating-area protection allows operation up to 36 V with a regulated output current of more than 3 ma. Overvoltage protection limits operation at 42 V. The overvoltage protection hysteresis restores operation if the input voltage has dropped below 36 V. A reset signal is generated for an output voltage of V Q < 4.5 V. The delay for power-on reset can be set externally with a capacitor. Data Sheet 3 Rev. 1.6,

4 Temperature Sensor Saturation Control and Protection Circuit I 1 5 Q Bandgap Reference Control Amplifier Buffer Reset Generator 2 RO 4 D Adjustment 3 GND AEB1924 Figure 2 Block Diagram Data Sheet 4 Rev. 1.6,

5 Table 2 T j = -4 to 15 C Absolute Maximum Ratings Parameter Symbol Limit Values Unit Notes Input I Voltage Voltage Current Reset Output RO Voltage Current Reset Delay D Voltage Current Output Q Voltage Current Ground GND V I V I I I Min. -42 V RO -.3 I RO V D -.3 I D V Q -1. I Q Max. Current I GND -.5 A Temperatures Junction temperature Storage temperature T j T stg V V V V V C C t 4 ms internally limited Internally limited Internally limited Internally limited Table 3 Operating Range Parameter Symbol Limit Values Unit Notes Min. Max. Input voltage V I 6 42 V Junction temperature T j C Thermal Resistance Junction ambient R thj-a K/W K/W TO263, TO252 1) Junction case R thj-c 3 K/W TO-22/263 Packages 1) Mounted on PCB, mm 3 ; 35µ Cu; 5µ Sn; Footprint only; zero airflow. Data Sheet 5 Rev. 1.6,

6 Table 4 Characteristics V I = 13.5 V; -4 C T j 125 C (unless otherwise specified) Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. Output voltage V Q V 5 ma I Q 55 ma; 6 V V I 26 V Output voltage V Q V 26 V V I 36 V; I Q 3 ma Output current limiting Current consumption I q = I I - I Q Current consumption I q = I I - I Q Current consumption I q = I I - I Q I Qmax ma V Q = V I q ma I Q = 5 ma I q ma I Q = 55 ma I q 7 9 ma I Q = 55 ma; V I = 5 V Drop voltage V DR 35 7 mv I Q = 55 ma 1) Load regulation V Q,Lo 25 5 mv I Q = 5 to 55 ma; V I = 6 V Line regulation V Q,Li mv V I = 6 to 26 V I Q = 5 ma Power supply Ripple rejection PSRR 54 db f r = 1 Hz; V r =.5 Vpp Reset Generator Switching threshold V RT V Reset High voltage V ROH 4.5 V Reset low voltage V ROL 6 mv R int = 3 kω 2) ; 1. V V Q 4.5 V Reset low voltage V ROL 2 4 mv I R = 3 ma, V Q = 4.4 V Reset pull-up R int kω internally connected to Q Charge current I D,c µa V D = 1. V Data Sheet 6 Rev. 1.6,

7 Table 4 Characteristics (cont d) V I = 13.5 V; -4 C T j 125 C (unless otherwise specified) Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. Upper reset timing V DU V threshold Lower reset timing V DL V V Q < V RT threshold Delay time t rd 13 ms C D = 1 nf Reset reaction time t rr 3 µs C D = 1 nf Overvoltage Protection Turn-Off voltage V I, ov V 1) Drop voltage = V I - V Q (measured when the output voltage has dropped 1 mv from the nominal value obtained at 13.5 V input) 2) Reset peak is always lower than 1. V. Data Sheet 7 Rev. 1.6,

8 I I 1 µf 47 nf I 1 5 Q I Q 22 µf TLE 427G V I 4 D 2 3 GND RO I R V Q I D V R V D C D I GND AES1925 Figure 3 Test Circuit Input I 1 5 Q 5 V - Output 47 nf TLE 427 Reset to µc RO 2 3 GND 4 D 1 nf 22 µf AES1926 Figure 4 Application Circuit Data Sheet 8 Rev. 1.6,

9 Design Notes for External Components An input capacitor C I is necessary for compensation of line influences. The resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approx. 1 Ω in series with C I. An output capacitor C Q is necessary for the stability of the regulating circuit. Stability is guaranteed at values of C Q 22 µf and an ESR of < 3 Ω. Reset Circuitry If the output voltage decreases below 4.5 V, an external capacitor C D on pin 4 (D) will be discharged by the reset generator. If the voltage on this capacitor drops below V DL, a reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage rises above the reset threshold, C D will be charged with constant current. After the power-on-reset time the voltage on the capacitor reaches V DU and the reset output will be set high again. The value of the power-on-reset time can be set within a wide range depending of the capacitance of C D. Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor C D which can be calculated as follows: C D = ( t I D,c )/ V (1) Definitions: C D = delay capacitors t = reset delay time t rd I D,c = charge current, typical 14 µa V = V DU, typical 1.8 V V DU = upper reset timing threshold at C D for reset delay time t rd = V C D /I D,c (2) The reset reaction time t rr is the time it takes the voltage regulator to set the reset out LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs for delay capacitor of 47 nf. For other values for C D the reaction time can be estimated using the following equation: t rr 2 s/f C D (3) Data Sheet 9 Rev. 1.6,

10 V I < t rr V Q V D VRT VDU V DL dv d t = I D, c C D t rd t rr V RO Power-ON Reset Thermal Shutdown Voltage Drop at Input Undervoltage Secondary Spike Load Bounce AES1927 Figure 5 Reset Time Response Data Sheet 1 Rev. 1.6,

11 Output Voltage V Q versus Temperature T j Output Voltage V Q versus Input Voltage V I V Q 5.2 V 5.1 V I = 13.5 V AED1928 V Q 12 V 1 AED R L = 25 Ω C 16 T j V Ι V 1 Output Current I Q versus Temperature T j Output Current I Q versus Input Voltage V I 12 ma I Q max AED193 I Q 1.2 A AED T j = 125 C 25 C C 16 T j V 5 V I Data Sheet 11 Rev. 1.6,

12 Current Consumption I q versus Output Current I Q Ι q 3 ma AED392 Current Consumption I q versus Output Current I Q Ι q 8 ma 7 AED V Ι = 13.5 V 3 2 V Ι = 13.5 V ma 12 Ι Q ma 6 Ι Q Current Consumption I q versus Input Voltage V I Drop Voltage V DR versus Output Current I Q I q 12 ma 1 AED1934 V DR 8 mv 7 AED R L = 1 Ω 5 4 T j = 125 C 25 C R L = 2 Ω 5 Ω V 5 V I ma 1 I Q Data Sheet 12 Rev. 1.6,

13 Charge Current I D,c versus Temperature T j I 2 µa AED347 Upper Reset Timing Threshold V DU versus Temperature T j 4. ma V DU AED I D, c V I = 13.5 V V D = 1 V V Ι = 13.5 V V DU C C 16 T j T j Data Sheet 13 Rev. 1.6,

14 Package Outlines 1 ± ± ) A ±.1 17± ±.3 1) 13.4 ± ±.2 C ± ±.3.8 ±.1 3.7± ± M A C 8.4 ± ±.4 1) Typical All metal surfaces tin plated, except area of cut. GPT964 Figure 6 P-TO (Plastic Transistor Single Outline) You can find all of our packages, sorts of packing and others in our Infineon Internet Page Products : SMD = Surface Mounted Device Dimensions in mm Data Sheet 14 Rev. 1.6,

15 1 ± ± ) A B ±.1 17± ±.3 1) 13.4 ± ±.2 C 11±.5 13 ± x.8 ± ± M A B C Typical 1) All metal surfaces tin plated, except area of cut. GPT965 Figure 7 P-TO (Plastic Transistor Single Outline) You can find all of our packages, sorts of packing and others in our Infineon Internet Page Products : SMD = Surface Mounted Device Dimensions in mm Data Sheet 15 Rev. 1.6,

16 (15) ±.2 1 ±.3 1 ± ) 1) 7.55 A 1.27 ± ± ±.3 B x.8 ±.1 4 x ±.1.25 M A B 8 MAX..1 B 1) Typical Metal surface min. X = 7.25, Y = 6.9 All metal surfaces tin plated, except area of cut. GPT9113 GPT9113 Figure 8 P-TO (Plastic Transistor Single Outline) You can find all of our packages, sorts of packing and others in our Infineon Internet Page Products : SMD = Surface Mounted Device Dimensions in mm Data Sheet 16 Rev. 1.6,

17 1± ±.1 A B ± (4.17).8 ±.15 1± max per side x ±.1.25 M A B.51 min GPT9161 All metal surfaces tin plated, except area of cut. Figure 9 P-TO (Plastic Transistor Single Outline) You can find all of our packages, sorts of packing and others in our Infineon Internet Page Products : SMD = Surface Mounted Device Dimensions in mm Data Sheet 17 Rev. 1.6,

18 ± MAX. ±.1 (4.24) 1 1).15 MAX. per side (5).8 ± A 5 x.6 ±.1.25 M A B B MIN B 1) Includes mold flashes on each side. All metal surfaces tin plated, except area of cut. GPT9527 Figure 1 P-TO (Plastic Transistor Single Outline) You can find all of our packages, sorts of packing and others in our Infineon Internet Page Products : SMD = Surface Mounted Device Dimensions in mm Data Sheet 18 Rev. 1.6,

19 Remarks Data Sheet 19 Rev. 1.6,

20 Edition Published by Infineon Technologies AG, St.-Martin-Strasse 53, München, Germany Infineon Technologies AG 24. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office ( Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.