Section 2. 1) Dynamic op amp limitations. 2) Static op amp limitations

Transcription

1 Section 2 1) Dynamic op amp limitations 2) Static op amp limitations

2 1 ) Open-loop response Dynamic op amp limitations Dominant pole response: Low frequencies: Higher frequencies: Low pass filter action Expression for open-loop response: The open-loop response has higher order poles and zeroes, but the dominant pole frequency is chosen deliberately low to ensure that gain has dropped well below unity and the effect of higher order roots can be ignored

3 Dynamic op amp limitations Dominant pole response: For general purpose type op amps: 500 khz < GBP <20 MHz a 0 and f b are ill-defined because of R eq and a 2 due to manufacturing process variations. f t is more practical parameter. Stable, predictable values of I A and C C Graphical visualization of loop-gain:

4 2 ) Closed-loop response Non- inverting Amplifier: Dynamic op amp limitations a) T >>1, A ~ A ideal b) T = 1, phase (T) = - 90 o, A =A ideal / (1 + j) c) T << 1, A ~ A ideal. T = a Negative feedback reduces gain form a 0 to A 0 (A 0 << a 0 ), but widens the bandwidth from f b to f B (f b >> f B ). Gain Bandwidth trade off: GBP = A 0. f B = f t

5 Dynamic op amp limitations Inverting Amplifier: Gain Bandwidth trade off: GBP = A 0. f B = ( R 2 / R 1 ). f t. ( R 1 / (R 1 +R 2 ) ) = (1- β). ft Non-inverting unity gain amplifier : GBP = f t Inverting unity gain amplifier : GBP = 0.5 f t 3) Output and input impedances z d, z o are capacitive or inductive z c, common mode input impednace Data sheets provide r d, r o, r c Some times C d, C c information is provided Z ~ z ( 1 + T ) (series) or Z ~ z ( 1 + T ) -1 (shunt) By decreasing T at higher frequencies the series impedance is more capacitive and the shunt Impedance is more inductive

6 Input series impedance: Dynamic op amp limitations Output series impedance: Equivalent Circuit Input Output

7 Input shunt impedance: Dynamic op amp limitations Output shunt impedance: Equivalent Circuit Output

8 Dynamic op amp limitations 4 ) Transient response Examining the transient response to a step signal Rise Time (t R ) t R : time for V o to swing from 10% to 90% of V m : Slew Rate limiting Above a certain step amplitude the output slope saturates at a constant value named slew-rate and the output waveform is a ramp Slew rate limiting is a nonlinear effect that stems from the limited ability by the internal circuitry to charge or discharge the frequency compensation capacitor C c

9 Dynamic op amp limitations Generalization for β < 1: f t β. f t Full - Power Bandwidth : The maximum frequency at which the op amp will yield an undistorted AC output With the largest possible amplitude. Settling time (t s ) The time it takes for the response to a large input signal to settle and remain within Specified error band (0.1% and 0.01%nof a 10 V input step). Test Circuit for t s Fast t s is desirable in high speed, high accuracy D-A converters, S & H circuits and multiplexed amplifiers

10 Dynamic op amp limitations Slew rate limiting causes and cures V m small; input stage in linear region: By overdriving input stage i o1 saturates at I A and C c is current starved. During slew-rate limiting, v N may depart form v P (input stage saturation). Three different ways of improving S.R. : (1) Increasing ft (reducing Cc) (2) Reducing gm (3) Increasing IA

11 Section 2 1) Dynamic op amp limitations 2) Static op amp limitations

12 Static op amp limitations 1 ) Input bias and offset currents Practical op amps draw small currents at their input (I P and I N : Base or Gate currents) Mismatch between input transistors: I B = (I P +I N )/2 and I OS =I P I N (I OS << I B ) The polarity of I OS depends on the direction of mismatch Errors caused by I B and I OS : E o = (1+(R 2 / R 1 ))[(R 1 R 2 )I N R P I P ] E o : Output DC noise E o = (1+(R 2 / R 1 )). {[(R 1 R 2 ) R P ](I B ) [(R1 R2) + R](I os /2)] R p = R 1 R 2 : Dummy Resistor then I B = 0

13 Static op amp limitations Low input bias current op amps 1. Super-beta input op amps: β F ~ 1000!, LM308 (I B = 1nA) 2. Input bias current cancellation: Using internal circuitry, OP 07 (I B = 1 na, I OS =0.4 na) 3. JFET input op amps: I G in the order of tens of Pico amps. LF 356 BiFET (I B = 30 pa, I OS =3 pa), AD549, OPA129: Special JFET +Isolation techniques (I B < 100 fa) 4. MOSFET input op amps: Input leakage current is around pa. TLC 279 CMOS (I B = 0.7 pa, I OS =0.1 pa), Input bias current drift For Bipolar op amps increasing the temperature decreases I B For p-n junction (Diode or JFET ): I B (T) ~I B (T0). 2 T0 : Ambient temperature ( o C) (T T0)/10 At high temperatures, there is no advantage in using FET op amps

14 Static op amp limitations 2 ) Input offset voltage Vo = a. (v P v N ); By shorting v P and v N : v o = 0, Due to inherent mismatches v o is not zero To force v o to zero, a suitable correction voltage must be applied between the input ports. vo = a. (v P + V os v N ) = 0; v N = v P + V os Errors caused by V os : E o = (1+(R 2 / R 1 )). V os R 2 >> R 1 : good for measuring V os

15 Static op amp limitations Thermal Drift Temperature coefficient: T c (V os ) = d V os / dt (mv/ o C) V os (T) ~V os (25 o C) +Tc (V os ). (T -25 o C) Common Mode Rejection Ratio We model this phenomena with a change in the input offset voltage due to v CM variation 1 / CMRR = d V os / d v CM (μv/v), In practice v CM ~v P Power Supply Rejection Ration We model this phenomena with a change in the input offset voltage due to supply variation : 1 / PSRR = d V os / d V S (μv/v) Changes of V os with output swing Δ Vos = Δ vo / a

16 Static op amp limitations Summary of effects which generate V os : V os = V os0 + Tc (V os ). ΔΤ + (Δ V p / CMRR) + (Δ V s / PSRR) + (Δv o / a) 3 ) Input offset error compensation Internal offset nulling: E o =(1 + (R 2 / R 1 )). [ V os -(R 1 R 2 )I os ] E I = V os -(R 1 R 2 )I os E I can be nulled by using a suitable trimmer, a smart designer tries to minimize E I by a combination of circuit tricks (scaling, op amp selection, etc). The last choice would be trimming.

17 Static op amp limitations External offset nulling: Does not introduce any additional imbalance to the input stage, no degradation drift CMRR, PSRR Input Error: E I + V x R B >> R C (Excessive loading of the wiper) R A << R P (Avoid perturbing)