EE247 Lecture Comparator architecture examples Flash ADC sources of error Sparkle code Meta-stability

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1 EE247 Lecture 2 ADC Converters - Comparator architecture examples Flash ADC sources of error Sparkle code Meta-stability Techniques to reduce flash ADC complexity Interpolating Folding EECS 247 Lecture 2: Data Converters 24 H.K. Page Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input & single-ended large swing output Output swing compatible with driving digital logic circuits Open-loop amplification no frequency compensation required Precise gain not required Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe Two options for implementation : High-gain amplifier + simple digital latch Low-gain amplifier + a high-sensitivity latch Sample-data comparators S/H input Offset cancellation Pipelined stages EECS 247 Lecture 2: Data Converters 24 H.K. Page 2

2 Latched Comparator f s V i+ A v Latch D o+ V i- D o- Preamp Clock rate f s Resolution Overload recovery Input capacitance (and linearity!) Power dissipation Input common-mode range Kickback noise EECS 247 Lecture 2: Data Converters 24 H.K. Page 3 Comparators Overdrive Recovery Linear model for a single-pole amplifier: U amplification after time t a During reset amplifier settles exponentially to its zero input condition with τ =RC Assume Vm maximum input normalized to /2lsb (=) Example: Worst case input/output waveforms Limit output voltage swing by. Passive clamp 2. Active restore 3. Low gain/stage EECS 247 Lecture 2: Data Converters 24 H.K. Page 4

3 Comparators Overdrive Recovery Limiting Output Clamp Adds parasitic capacitance Active Restore After outputs are latched Activate φ R & equalize output nodes EECS 247 Lecture 2: Data Converters 24 H.K. Page 5 CMOS Comparator Example Flash ADC: 8bits, +-/2LSB fs=5mhz (Vref=3.8V) No offset cancellation A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, JSSC June 985, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 6

4 Comparator with Auto-Zero I. Mehr and L. Singer, A 5-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 999, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 7 Auto-Zero Implementation Ref:I. Mehr and L. Singer, A 55-mW, -bit, 4-Msample/s Nyquist-Rate CMOS ADC, JSSC March 2, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 8

5 Comparator Example Variation on Yukawa latch used w/o preamp No dc power when φ high Good for low resolution ADCs M & M2 added to vary comparator threshold To st order, for W=W2 & W=W2 V th latch = W/W x V R where V R =V R+ - V R- Ref: T. B. Cho and P. R. Gray, "A b, 2 Msample/s, 35 mw pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 3, pp , March 995. EECS 247 Lecture 2: Data Converters 24 H.K. Page 9 Comparator Example Used in a pipelined ADC with digital correction no offset cancellation Input buffers suppress kick-back Note differential reference M7, M8 operate in triode region Preamp gain ~ Current in MB2 switches by LATCH signal to flow either in the preamp or the latch. Ref: S. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC,NO. 6, Dec. 987 EECS 247 Lecture 2: Data Converters 24 H.K. Page

6 Bipolar Comparator Example Used in 8bit 4Ms/s & 6bit 2Gb/s flash ADC Signal amplification during φ high, latch operates when φ low Input buffers suppress kickback & input current Separate ground and supply buses for front-end preamp kick-back noise reduction Ref: Y. Akazawa, et al., "A 4MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXX, pp , February 987. Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits Conference, vol. XXXI, pp , February 988. EECS 247 Lecture 2: Data Converters 24 H.K. Page Flash Converter Sources of Error R/2 R R R V ref V in Encoder Digital Output Comparator input: Offset Nonlinear input capacitance Kickback noise (disturbs reference) Signal dependent sampling time R R/2 Comparator output: Sparkle codes ( ) Metastability EECS 247 Lecture 2: Data Converters 24 H.K. Page 2

7 Typical Flash Output Encoder Binary Output (negative) V DD b3 b2 b b Thermometer to Binary decoder ROM Thermometer code -of-n decoding Final encoding NOR ROM EECS 247 Lecture 2: Data Converters 24 H.K. Page 3 Typical Flash Output Decoder Binary Output (negative) V DD b3 b2 b b b3 b2 b b Output Thermometer to Binary decoder ROM EECS 247 Lecture 2: Data Converters 24 H.K. Page 4

8 Sparkle Codes V DD Erroneous (comparator offset?) b3 b2 b b Correct Output: Erroneous Output: EECS 247 Lecture 2: Data Converters 24 H.K. Page 5 Sparkle Tolerant Encoder Protects against a single sparkle. Ref: C. Mangelsdorf et al, A 4-MHz Flash Converter with Error Correction, JSSC February 99, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 6

9 Meta-Stability X Different gates interpret metastable output X differently Correct output: or Erroneous output: Solutions: Latches (high power) Gray encoding Ref: C. Portmann and T. Meng, Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters, JSSC August 996, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 7 Gray Encoding Thermometer Code Gray Binary T T 2 T 3 T 4 T 5 T 6 T 7 G 3 G 2 G B 3 B 2 B G = T T + T T G G = T T = T Each T i affects only one G i Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder EECS 247 Lecture 2: Data Converters 24 H.K. Page 8

10 Reducing Flash ADC Complexity E.g. -bit straight flash Input range: V LSB = : ~ mv Comparators: 23 with offset << LSB Input capacitance: 23 * ff = 2pF Power: 23 * 3mW = 3W Techniques: Interpolation Folding Folding & Interpolation Two-step, pipelining EECS 247 Lecture 2: Data Converters 24 H.K. Page 9 Interpolation Idea Interpolation between preamp outputs Reduces number of preamps Reduced input capacitance Reduced area, power dissipation Same number of latches Important side-benefit Decreased sensitivity to preamp offset improved DNL EECS 247 Lecture 2: Data Converters 24 H.K. Page 2

11 Simulink Model Vi Vin Vin A2 2*Delta Vref2 Preamp2 2 Y A *Delta Preamp Vref EECS 247 Lecture 2: Data Converters 24 H.K. Page 2 Preamp Output Vin A Preamp Output Vin / A A 2 Zero crossings (to be detected by latches) at V in = V ref = V ref2 = 2 A 2 EECS 247 Lecture 2: Data Converters 24 H.K. Page 22

12 Differential Preamp Output Preamp Output A +A A -A A 2 -A A +A Vin / Zero crossings at V in = V ref = V ref2 =.5*(+2) = 2 V ref2 EECS 247 Lecture 2: Data Converters 24 H.K. Page 23 Interpolation in Flash ADC Vin A A 2 Half as many reference voltages and preamps Interpolation factor:x2 Possible to accomplish higher interpolation factor Resistive interpolation EECS 247 Lecture 2: Data Converters 24 H.K. Page 24

13 Resistive Interpolation Resistors produce additional levels With 4 resistors, the interpolation factor M=8 (ratio of latches/preamps) Ref: H. Kimura et al, A -b 3-MHz Interpolated- Parallel A/D Converter, JSSC April 993, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 25 DNL Improvement Preamp offset distributed over M resistively interpolated voltages: impact on DNL divided by M Latch offset divided by gain of preamp use large preamp gain Ref: H. Kimura et al, A -b 3-MHz Interpolated- Parallel A/D Converter, JSSC April 993, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 26

14 Preamp Input Range Preamp Output A +A Vin / A -A A 2 -A 2 A +A 2 Linear preamp input ranges must overlap i.e. range > Sets upper bound on gain << V DD / EECS 247 Lecture 2: Data Converters 24 H.K. Page 27 Interpolated-Parallel ADC Ref: H. Kimura et al, A -b 3-MHz Interpolated-Parallel A/D Converter, JSSC April 993, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 28

15 Measured Performance (7+3) Ref: H. Kimura et al, A -b 3-MHz Interpolated-Parallel A/D Converter, JSSC April 993, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 29 Folding Converter V IN MSB ADC LSB ADC Digital Output Folding Circuit Significantly fewer comparators than flash ~2 B/2+ Fast Nonidealities in folder limit resolution to ~ EECS 247 Lecture 2: Data Converters 24 H.K. Page 3

16 Folding Folder maps input to smaller range MSB ADC determines which fold input is in LSB ADC determines position within fold Logic circuit combines LSB and MSB results Folder Output Analog Input MSB ADC LSB ADC EECS 247 Lecture 2: Data Converters 24 H.K. Page 3 Generating Folds A-A2 A A Vin / A-A2 A3 A-A2+A Vin / EECS 247 Lecture 2: Data Converters 24 H.K. Page 32

17 Folding Circuit 3 V 3 V R kohm R2 kohm Vo Vo2 M / M2 / Vref M3 / M4 / Vref2 M5 / M6 / Vref3 M7 / M8 / Vref4 I I2 I3 I4 Vin EECS 247 Lecture 2: Data Converters 24 H.K. Page 33 CMOS Folder Output.5 Folder Output Ideal Folder CMOS Folder Accurate only at zero-crossings Error Vin / Lowdown Most folding ADCs do not actually use the folds, but only the zero-crossings! EECS 247 Lecture 2: Data Converters 24 H.K. Page 34

18 Parallel Folders Folder 4 Fine Flash ADC 4 V ref + 3/4 * Folder 3 Fine Flash ADC 3 V ref + 2/4 * Logic Folder 2 Fine Flash ADC 2 V ref + /4 * Folder Fine Flash ADC V ref + /4 * EECS 247 Lecture 2: Data Converters 24 H.K. Page 35 Parallel Folder Outputs Folder Output F F2 F3 F4 4 Folders 6 Zero crossings only 4 LSB bits Better resolution More folders Large complexity Interpolation Vin / EECS 247 Lecture 2: Data Converters 24 H.K. Page 36

19 Folding & Interpolation Folder 4 V ref + 3/4 * Folder 3 V ref + 2/4 * Folder 2 Fine Flash ADC Encoder V ref + /4 * Folder V ref + /4 * EECS 247 Lecture 2: Data Converters 24 H.K. Page 37 Folder / Interpolator Output Folder / Interpolator Output F F2 I I2 I3 Folder / Interpolator Output.5 F F2 I.4 I2 I Vin / Vin / EECS 247 Lecture 2: Data Converters 24 H.K. Page 38

20 Folder / Interpolator Output Folder / Interpolator Output F F2 I I2 I Vin / Folder / Interpolator Output Vin / Interpolate only between closely spaced folds to avoid nonlinear distortion F F2 I I2 I3 EECS 247 Lecture 2: Data Converters 24 H.K. Page 39 A 7-MS/s -mw 8-b CMOS Folding and Interpolating A/D Converter Ref: B. Nauta and G. Venes, JSSC Dec 985, pp EECS 247 Lecture 2: Data Converters 24 H.K. Page 4

21 A 7-MS/s -mw 8-b CMOS Folding and Interpolating A/D Converter EECS 247 Lecture 2: Data Converters 24 H.K. Page 4 A 7-MS/s -mw 8-b CMOS Folding and Interpolating A/D Converter EECS 247 Lecture 2: Data Converters 24 H.K. Page 42

22 Pipelined ADCs EECS 247 Lecture 2: Data Converters 24 H.K. Page 43 Pipelined A/D Converters Ideal Operation Errors and Correction Redundancy Digital Calibration Implementation Practical Circuits Stage Scaling EECS 247 Lecture 2: Data Converters 24 H.K. Page 44

23 Block Diagram V in Stage B V res Stage 2 B 2 V res2 Stage k B k MSB......LSB Align and Combine Data Digital output (B + B B k ) Idea: Cascade several low resolution stages to obtain high overall resolution Each stage performs coarse A/D conversion and computes its quantization error, or "residue" EECS 247 Lecture 2: Data Converters 24 H.K. Page 45 Characteristics Number of components (stages) grows linearly with resolution Pipelining Trading latency for conversion speed Latency may be an issue in e.g. control systems Throughput limited by speed of one stage fi Fast Versatile: 8...6bits,...2MS/s Many analog circuit non-idealities can be corrected digitally EECS 247 Lecture 2: Data Converters 24 H.K. Page 46

24 Concurrent Stage Operation φ φ 2 acquire convert convert acquire V in Stage B Stage 2 B 2 Stage k B k CLK φ φ 2 φ... Align and Combine Data Digital output (B + B B k ) Stages operate on the input signal like a shift register New output data every clock cycle, but each stage introduces ½ clock cycle latency EECS 247 Lecture 2: Data Converters 24 H.K. Page 47 Data Alignment φ φ 2 acquire convert convert acquire V in Stage B Stage 2 B 2 Stage k B k CLK φ φ 2 φ D out CLK CLK CLK Digital shift register aligns sub-conversion results in time EECS 247 Lecture 2: Data Converters 24 H.K. Page 48

25 Latency [Analog Devices, AD 9226 Data Sheet] EECS 247 Lecture 2: Data Converters 24 H.K. Page 49 Pipelined ADC Analysis Ignore timing and use simple static model V in Stage B V res Stage 2 B 2 V res2 Stage k B k + + D out Let's first look at "two-stage pipeline" E.g.: Two cascaded 2-bit ADCs to get 4 bits of total resolution EECS 247 Lecture 2: Data Converters 24 H.K. Page 5

26 Two Stage Example V in 2-bit ADC 2-bit ADC??? + D out = V in + ε q Using only one ADC: Output contains large quantization error "Missing voltage" or "residue" (-ε q ) Idea: Use second ADC to quantize and add -ε q EECS 247 Lecture 2: Data Converters 24 H.K. Page 5 Two Stage Example 2-bit ADC 2-bit DAC 2-bit ADC V in Coarse + - -ε q Fine + ε q +ε q2 D out = V in + ε q ε q + ε q2 Use DAC to compute missing voltage Add quantized representation of missing voltage Why does this help? How about ε q2? EECS 247 Lecture 2: Data Converters 24 H.K. Page 52

27 Two Stage Example ε q V ref /2 2 V ref V in V ref2 Second ADC Fine First ADC Coarse Fine ADC is re-used 2 2 times Fine ADC's full scale range needs to span only LSB of coarse quantizer Vref 2 Vref ε q2 = = EECS 247 Lecture 2: Data Converters 24 H.K. Page 53 Two Stage Transfer Function D out Coarse (MSB) Fine (LSB) V ref V in EECS 247 Lecture 2: Data Converters 24 H.K. Page 54