NTE943, NTE943M, & NTE943SM Integrated Circuit Low Power, Low Offset, Dual Voltage Comparator

Transcription

1 NTE9, NTE9M, & NTE9SM Integrated Circuit Low Power, Low Offset, Dual Voltage Comparator Description: The NTE9, NTE9M, and NTE9SM consist of two independent precision voltage comparators with an offset voltage speciication as low as.0mv max for two comparators which were designed specifically to operate from a single power supply over a wid range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. These comparators alos have a unique characteristic in that the input common mode voltage range includesground, even though operated from a single powe supply voltage. Application areas include limit comparators, simple analog to digital converters; pulse, squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. These devices are designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies they will directly interface with MOS logic where their low power drain is a distinct advantage over standard comparators. Features: Wide Single Supply Volatge Range:.0V to V Dual Supplies: ±.0V to ±V Low Supply Current Drain (0.mA) Independent of Supply Voltage (.0mW/Comparator at V) Low Input Biasing Current: na Low Input Offset Current: ±na Maximum Offset Voltage: ±mv Input Common Mode Voltage Range Includes Ground Differential Input Voltage Range Equal to the Power Supply Voltage Low Output Saturation Voltage: ma Output Voltge Compatible with TTL, DTL, ECL, MOS, and CMOS Logic Sytems Available in Different Case Styles: Lead Metal Can: NTE9 Lead Mini DIP: NTE9M Lead SOIC (Surface Mount): NTE9SM

2 Absolute Maximum Ratings: Supply Voltage, V V or ±V Differential Input Voltage (Note ) V Input Voltage V to +V Power Dissipation (Note ) NTE mW NTE9M mW NTE9SM mW Output Short Circuit to GND (Note ) Continuous Input Current (V IN < 0.V), Note ) mA Operating Temperature Range to +0 C Storage Temperature Range to +0 C Lead Temperature (During Soldering, 0 sec) C Note. Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common mode range, the comparator will provide a proper output state. The low input voltage state must not be less than 0.V (or 0.V below the the magnitude of the negative power supply, if used). Note. For operating at elevated temperature, these devices must be derated based on a C maximum junction temperature and a thermal resistance of C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The low bias dissipation and the ON OFF haracteristic of the output keeps the chip dissipation very small (P D 00mW), provided the output transistors are allowed to saturate. Note. Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to GND, the maximum output current is approximately 0mA independent of the magnitude of V+. Note. This input current will only exist when the voltage at any of th input leads is driven negative. It is due to the collector base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to GND for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re establish when the input voltage, which was negative, again returns to a value greater than 0.V. Electrical Characteristics: (0 T A +0 C, V+ = V unless otherwise specified) Parameter Test Conditions Min Typ Max Unit Input Offset Voltage Note ±9.0 mv T A = + C, Note ±.0 ±.0 mv Input Offset Current I IN (+) I IN ( ) V CM = 0V ±0 na I IN (+) I IN ( ) V CM = 0V, T A = + C ±.0 ±0 na Input Bias Current I IN (+) or I IN ( ) with Output in Linear Range, V CM = 0V, Note I IN (+) or I IN ( ) with Output in Linear Range, V CM = 0V, T A = + C, Note 0 na 0 na Note. At output switch point, V O.V, R S = 0Ω, with V+ from V to 0V and over he full input common mode range (0V to V+.V), at C. Note. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output so no loading change exists on the reference or input lines.

3 Electrical Characteristics (Cont d): (0 T A +0 C, V+ = V unless otherwise specified) Parameter Test Conditions Min Typ Max Unit Input Common Mode V+ = 0V, Note 0 V+.0 V Voltage Range V+ = 0V, T A = + C, Note 0 V+. V Supply Current R L = on all Components, T A = + C 0..0 ma R L = on all Amps, V+ = V, T A = + C ma Voltage Gain R L kω, V+ = V, V O = V to V, T A = + C 0 00 V/mV Large Signal Response Time V IN = TTL Logic Swing, V REF =.V, V RL = V, R L =.kω, T A = + C 00 ns Response Time V RL = V, R L =.kω, T A = + C, Note. µs Output Sink Current V IN ( ) = V, V IN (+) = 0, V O.V, T A = + C ma Saturation Voltage V IN ( ) = V, V IN (+) = 0, I SINK ma 00 mv V IN ( ) = V, V IN (+) = 0, I SINK ma, T A = + C 0 00 mv Output Leakage Current V IN ( ) = 0, V IN (+) = V, V O = 0V.0 µa V IN ( ) = 0, V IN (+) = V, V O = V, T A = + C 0. na Differential Input Voltage Keep All V IN s 0V (or V, if Used), Note V Note. Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common mode range, the comparator will provide a proper output state. The low input voltage state must not be less than 0.V (or 0.V below the the magnitude of the negative power supply, if used). Note. The response time specified is for a 00mV input step with mv overdrive. For larger overdrive signals 00ns can be obtained.

4 Pin Connection Diagram NTE9 (Top View) NTE9M NTE9SM Non Invert Input B Invert Input B GND Output A V (+) Output B Non Invert Input A Invert Input A Non Invert Input A Output B Invert Input B V (+) Invert Input A GND Non Invert Input B Output A NTE9.0 (9.9) Dia Max. (.) Dia Max. (.) Max.9 (.) Min.0 (0.) Dia Typ.00 (.0) Dia.0 (0.)

5 NTE9M. (.) Max.9 (0.0) Max.00 (.).0 (.).00 (.).00 (.) Min.00 (.) NTE9SM.9 (.9). (.99). (.9).00 (.) 0 (.0).9 (.0) 0 (.).00 (.) NOTE: Pin on Beveled Edge