FPGA SYNTHESIS AND CONSTRAIN SETTING. -- Liang Tang

Transcription

1 FPGA SYNTHESIS AND CONSTRAIN SETTING -- Liang Tang 1

2 Outline FPGA Design Procedure Key FPGA Constraint Commands How to set constraint? 2

3 FPGA Design Procedure RTL (Register Transfer Level) Design Synthesis Implementation 3

4 FPGA Design Procedure RTL (Register Transfer Level) Design The FPGA design entry is Register Transfer Level which represents a digital circuit as a set of connected components. Design Specification Behavioral Description RTL Design RTL verification 4

5 FPGA Design Procedure Synthesis This stage converts RTL code into a optimized gate-level netlist represented in the terms of certain component library. RTL => Logic cell Logic cell Optimization Logic to Technology Timing/Area Optimization 5

6 FPGA Design Procedure Implementation Implementation procedure will translate netlist into the placed and routed FPGA design. Translate Map Place & Route 6

7 Outline FPGA Design Procedure Key FPGA Constraint Commands How to set constraint? 7

8 Key FPGA Constraint Commands Good constraint improves design performance: Tools try to meet your performance expectations; Compile time may be increased; Example of timing constraint effect: Without Timing constraint With Timing constraint 8

9 Key FPGA Constraint Commands I/O pad assignment Clock creation I/O delay definition False path 9

10 Key FPGA Constraint Commands I/O pad assignment Assign the signals in the FPGA design to I/O pad to communicate with external device. Example: NET "i2c_sclk" LOC = "C5" ; 10

11 Key FPGA Constraint Commands Clock creation Constrain register to register path inside FPGA design. Example: NET MCLK" TNM_NET = "mclk_net"; TIMESPEC "TS_MCLK" = PERIOD "mclk_net" 10 ns HIGH 50 %; This example defines a minimum period of 10ns for MCLK clock net. D Q D Q 11 0ns 5ns 10ns MCLK

12 Key FPGA Constraint Commands I/O delay definition OFFSET constraint is used to specify external setup time for input pads or necessary hold time for output pads. For input pads, OFFSET specifies a time before the (external) clock edge when the related data signals are set. Syntax for input delay: OFFSET = IN offset_time [units] [VALID <datavalid_time> [UNITS]] {BEFORE AFTER} clk_name [{RISING FALLING}]; Parameter offset_time datavalid_time BEFORE AFTER clk_name RISING FALLING Comment The difference in time between the capturing clock edge and the start of the data to be captured. The valid duration of the data to be captured. It is optional parameter. It defines the timing relationship of the start of data to the clock edge. BEFORE is usually used. 12 The name of input trigger clock pad net. The capturing clock edge. It is optional parameter.

13 Key FPGA Constraint Commands Example for input delay: NET data_i" OFFSET = IN 4 ns BEFORE MCLK"; My Design D Q data_i D Q 4ns MCLK 13

14 Key FPGA Constraint Commands For output pads, OFFSET specifies a minimum time after the clock edge when the related data signals can be deasserted. Syntax for output delay: OFFSET = OUT offset_time [units] {BEFORE AFTER} clk_name [REFERENCE_PIN ref_pin ] [{RISING FALLING}]; Parameter offset_time BEFORE AFTER clk_name Comment It defines the time from the clock edge at the input pin of the FPGA until data first becomes valid at the data output pin of the FPGA. It defines the timing relationship from the clock edge to the start of data. The name of input trigger clock pad net. REFERENCE_PIN ref_pin RISING FALLING is an optional keyword that is most commonly used in source synchronous output interfaces. It is optional parameter. The transmitting clock edge. It is optional parameter. 14

15 Key FPGA Constraint Commands Example for output delay: NET data_o" OFFSET = OUT 5.5 ns AFTER MCLK"; My Design D Q data_o D Q 5.5ns MCLK 15

16 Key FPGA Constraint Commands Timing Ignore (TIG) TIG causes paths that fan forward from the point of application to be treated as if they do not exist during implementation. TIG is applicable to: Nets, Pins, Instances. Example TIMESPEC "TSid" = FROM "from_grp" TO "to_grp" TIG; 16

17 Outline FPGA Design Procedure Key FPGA Constraint Commands How to set constraint? 17

18 How to set constraint? User Constrain File (.ucf) UCF file is ASCII file specifying constraints on the logical design, such as timing and location. UCF can be edited by: ISE Constraints Editor; Any text editor; 18

19 ISE Constraints Editor After creation of ISE project, click: Project New Source Implementation Constraints File to generate constraints file. 19

20 ISE Constraints Editor In the ISE project Design tab, select your top module, then double click Create Timing Constraints under User Constraints. 20

21 ISE Constraints Editor Then the Constraints Editor will appear. 21

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23 ISE Constraints Editor: Clock Setting Double click the Clock Domains in Timing Constraints tab to activate clock setting. Set your clock based on specification. 23

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25 ISE Constraints Editor: Input Signal Setting Double click the Inputs in Timing Constraints tab to activate input signal setting. Select Interface type, Data rate and Clock edge at first. Notes on Interface type: System Synchronous Timing: one clock source controls the data transmission and reception of all devices. Source Synchronous Timing: one clock source controls the data transmission of devices. The derived clocks control data reception. 25

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27 ISE Constraints Editor: Input Signal Setting Then define the detail parameters: Parameter Input clock pad net Input pad timgroup/net External setup time (offset in) Data valid duration Comment The clock is used to capture the input signal. Equals to OFFSET IN clk_name parameter. Select the input signal to be defined. The time before the rising clock edge when the rising data becomes valid. Equals to OFFSET IN offset_time parameter. The duration of the data valid window for the rising data. Equals to OFFSET IN datavalid_time parameter. 27

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29 ISE Constraints Editor: Output Signal Setting Double click the Outputs in Timing Constraints tab to activate output signal setting. Then define the detail parameters: Parameter SDR/DDR selection Output clock pad net Output pad timegroup/net External clock to pad (offset out) Comment Select Single Data Rate or Dual Data Rate for output signal. The clock net used to trigger the outgoing data. Equals to OFFSET OUT clk_name parameter. Select the output signal to be defined. The time from the rising clock edge at the input pin of the FPGA until data becomes valid at the output pin of the FPGA. Equals to OFFSET OUT offset_time parameter. 29

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31 Using text editor After generation of constraint file by double click Create Timing Constraints, an UCF file should be generated in the project directory. It can be edited by any text editor. The full description of constraints syntax can be found in Xilinx Constraints Guide Example of UCF file content: NET "mclk" TNM_NET = mclk; TIMESPEC TS_MCLK = PERIOD "mclk" 9 ns HIGH 50%; NET "pal_hs" OFFSET = IN 5 ns VALID 7 ns BEFORE "mclk" RISING; NET "mem_adv" OFFSET = OUT 5 ns AFTER "mclk"; 31

32 Question Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz? Assume no clock skew between devices 32

33 Answer Answer: PERIOD = 10 ns, OFFSET IN = 7 ns and OFFSET OUT = 8 ns 33