Altera Error Message Register Unloader IP Core User Guide

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1 Altera Error Message Register Unloader IP Core User Guide UG Subscribe The Error Message Register (EMR) Unloader IP core (altera unloader) reads and stores data from the hardened error detection circuitry in Altera devices. Features Retrieves and stores an Altera device error register message contents Permits injection of an EMR register content value without changing CRAM bits Avalon Streaming (Avalon-ST) compliant interface Easy instantiation using the parameter editor Generates VHDL or Verilog HDL synthesis files Supports Verilog HDL RTL simulation Device Support The Error Message Register (EMR) Unloader IP core supports the following devices: Stratix V and Stratix IV Arria 10, Arria V, Arria II GX, and Arria II GZ Cyclone V Resource Utilization and Performance The Quartus II software generates the following resource estimate for the Cyclone V (5CGXFC7C7F23C8) FPGA device. Results for other devices are similar. Table 1: EMR Unloader IP Core FPGA Performance and Resource Utilization Resource utilization is not affected by the CRC Error Check Clock Divisor parameter. Device 5CGXFC7 C7F23C8 CRC Error Check Clock Divisor Parameters Enable Virtual CRC JTAG Injection ALMs Logic Registers Primary Secondary 4 Off M20K All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered Innovation Drive, San Jose, CA 95134

2 2 Installing and Licensing IP Cores UG Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore IP functions require that you purchase a separate license for production use. However, the OpenCore feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software. After you are satisfied with functionality and perfformance, visit the Self Service Licensing Center to obtain a license number for any Altera product. Figure 1: IP Core Installation Path acds quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores altera - Contains the Altera IP Library source code <IP core name> - Contains the IP core source files Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is <home directory>/altera/ <version number>. Related Information Altera Licensing Site Altera Software Installation and Licensing Manual Customizing and Generating IP Cores You can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog and parameter editor allow you to quickly select and configure IP core ports, features, and output files. IP Catalog and Parameter Editor The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation. Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard Plug-In Manager for IP selection and parameterization, beginning in Quartus II software version Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores. The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. You can also parameterize an IP variation without an open project.

3 UG IP Catalog and Parameter Editor 3 Use the following features to help you quickly locate and select an IP core: Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog. Type in the Search field to locate any full or partial IP core name in IP Catalog. Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation. Click Search for Partner IP, to access partner IP information on the Altera website. Figure 2: Quartus II IP Catalog Search for installed IP cores Show IP only for target device Double-click to customize, right-click for detailed information Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer to Creating a System with Qsys in the Quartus II Handbook.

4 4 Using the Parameter Editor Using the Parameter Editor The parameter editor helps you to configure IP core ports, parameters, and output file generation options. Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values for specific applications. View port and parameter descriptions, and links to documentation. Generate testbench systems or example designs (where provided). Figure 3: IP Parameter Editors UG View IP port and parameter details Legacy parameter editors Specify your IP variation name and target device Apply preset parameters for specific applications Specifying IP Core Parameters and Options Follow these steps to specify IP core parameters and options. 1. In the Qsys IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears. 2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Altera device family and output file HDL preference. Click OK. 3. Specify parameters and options for your IP variation: Optionally select preset parameter values. Presets specify all initial parameter values for specific applications (where provided). Specify parameters defining the IP core functionality, port configurations, and device-specific features. Specify options for generation of a timing netlist, simulation model, testbench, or example design (where applicable). Specify options for processing the IP core files in other EDA tools. 4. Click Finish to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level.qsys IP variation file and HDL files for synthesis and

5 UG Files Generated for Altera IP Cores 5 simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing. 5. To generate a simulation testbench, click Generate > Generate Testbench System. Generate Testbench System is not available for some IP cores that do not provide a simulation testbench. 6. To generate a top-level HDL example for hardware verification, click Generate > HDL Example. Generate > HDL Example is not available for some IP cores. The top-level IP variation is added to the current Quartus II project. Click Project > Add/Remove Files in Project to manually add a.qsys file to a project. Make appropriate pin assignments to connect ports. Files Generated for Altera IP Cores The Quartus II software generates the following IP core output file structure: Figure 4: IP Core Generated Files <project directory> <your_ip>.qsys - System or IP integration file <your_ip>.sopcinfo - Software tool-chain integration file <your_ip> <your_ip> n IP variation files IP variation files <your_ip>.cmp - VHDL component declaration file <your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or.vhd - Sample instantiation template <your_ip>.ppf - XML I/O pin information file <your_ip>.qip - Lists IP synthesis files <your_ip>.sip - Contains assingments for IP simulation files <your_ip>_generation.rpt - IP generation report <your_ip>.debuginfo - Contains post-generation information <your_ip>.html - Connection and memory map data <your_ip>.bsf - Block symbol schematic <your_ip>.spd - Combines simulation scripts for multiple cores <testbench>_tb testbench system <testbench>_tb testbench files sim simulation files <EDA tool setup scripts> <your_ip>_tb.qsys Testbench system file <your_testbench>_tb.csv <your_testbench>_tb.spd sim Simulation files synth IP synthesis files <ip subcores> n Subcore libraries <EDA tool name> Simulator scripts <your_ip>.v or.vhd Top-level simulation file <simulator_setup_scripts> <your_ip>.v or.vhd Top-level IP synthesis file synth Subcore synthesis files <HDL files> sim Subcore Simulation files <HDL files>

6 6 Files Generated for Altera IP Cores Table 2: IP Core Generated Files UG File Name <my_ip>.qsys <system>.sopcinfo <my_ip>.cmp <my_ip>.html <my_ip>_generation.rpt <my_ip>.debuginfo <my_ip>.qip <my_ip>.csv <my_ip>.bsf <my_ip>.spd <my_ip>.ppf <my_ip>_bb.v <my_ip>.sip Description The Qsys system or top-level IP variation file. <my_ip> is the name that you give your IP variation. Describes the connections and IP component parameterizations in your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components. Downstream tools such as the Nios II tool chain use this file. The.sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component. The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files. A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments. IP or Qsys generation log file. A summary of the messages during IP generation. Contains post-generation information. Used to pass System Console and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect. Contains all the required information about the IP component to integrate and compile the IP component in the Quartus II software. Contains information about the upgrade status of the IP component. A Block Symbol File (.bsf) representation of the IP variation for use in Quartus II Block Diagram Files (.bdf). Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The.spd file contains a list of files generated for simulation, along with information about memories that you can initialize. The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner. You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box. Contains information required for NativeLink simulation of IP components. You must add the.sip file to your Quartus project.

7 UG Files Generated for Altera IP Cores 7 File Name <my_ip>_inst.v or _inst.vhd <my_ip>.regmap <my_ip>.svd <my_ip>.v or Description HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation. If the IP contains register information, the.regmap file generates. The.regmap file describes the register map information of master and slave interfaces. This file complements the.sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in System Console. Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system. During synthesis, the.svd files for slave interfaces visible to System Console masters are stored in the.sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name. HDL files that instantiate each submodule or child IP core for synthesis or simulation. <my_ip>.vhd mentor/ aldec/ /synopsys/vcs /synopsys/vcsmx /cadence Contains a ModelSim script msim_setup.tcl to set up and run a simulation. Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation. Contains a shell script vcs_setup.sh to set up and run a VCS simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX simulation. Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation. /submodules Contains HDL files for the IP core submodule. <child IP cores>/ For each generated child IP core directory, Qsys generates /synth and / sim sub-directories.

8 8 Parameter Settings UG Parameter Settings Table 3: EMR Unloader Parameters Parameter Value Default Description CRC error check clock divisor Enable Virtual JTAG CRC error injection 1, 2, 4, 8, 16, 32, 64, 128, Indicates the error detection clock divisor value to apply to the internal oscillator. The divided clock drives the internal CRC function. This setting must match the ERROR_CHECK_FREQUENCY_DIVISOR Quartus II Settings File (.qsf) setting, otherwise the software issues a warning. Stratix IV, Arria II GZ, and Arria II GZ devices do not support a value of 1. On, off Off Enables in-system sources and probes (ISSP) functionality to inject the EMR register content via the JTAG interface without changing the CRAM value. Use this interface to troubleshoot user logic that is connected to the core. Input clock frequency Any 50 MHz Specifies the frequency of the EMR Unloader IP core input clock. This option is applicable when the Input clock is driven from Internal Oscillator parameter is off. Input clock is driven from Internal Oscillator On, off Off Indicates that the internal oscillator provides the core input clock. Enable this parameter if an internal oscialltor drives the user design's core input clock. Note: The frequency of the internal oscillator is not affected by the CRC error check clock divisor. CRC Error Verify input clock frequency Completion of full chip Error Detection cycle MHz 50 MHz Specifies CRC Error Verify IP core (ALTERA_CRCERROR_VERIFY) input clock frequency. Stratix IV, Arria II GZ, and Arria II GX devices only. On, off Off Optional. Turn on to assert this signal at the end of each full chip error detection cycle. Stratix V, Arria 10, Arria V, and Cyclone V devices only.

9 UG Functional Description 9 Functional Description Some Altera devices include an error message register that indicates the occurance of a CRC error in the configuration RAM (CRAM). CRAM errors may occur because of a single event upset (SEU). You use the EMR Unloader IP core's Avalon-ST logic interface to access the device's EMR. For example, you can use the EMR Unloader IP core with the Fault Injection Debugger and Advanced SEU Detection IP cores to access device EMR information. Note: For more information on SEU support for your FPGA device, refer to the device handbook s SEU mitigation chapter. The EMR Unloader IP core monitors the device's EMR. When hardware updates the EMR content, the IP core reads (or unloads) and de-serializes the EMR content, and allows other logic (such as the Advanced SEU Detection IP core, Fault Injection IP core, and user logic) to access the EMR content simultaneously. As shown in the following figure, the EMR Unloader IP core instantiates the CRC Error Verify IP core. Figure 5: EMR Unloader Block Diagram EMR Unloader IP Core EMR Unloader Hard CRC Block shiftnld regout CRC Error Verify IP Core (1) Hard CRC Block EMR (Avalon-ST Source) CRC Error EMR Read End of Full-Chip Error Detection Cycle (Optional) Note: 1. The CRC Error Verify IP core is used in Stratix IV and Arria II devices only. Note: Refer to the CRC Error Verify IP core documentation for more information. Error Message Register Altera devices contain built-in error detection circuitry to detect a flip in any of the device's CRAM bits due to a soft error. Signals The bit assignments for the device EMR vary by device family. For details on the EMR bits for your FPGA device family, refer to the device handbook s SEU mitigation chapter. Table 4: EMR Unloader Signals Signal Width Direction Description clock 1 Input Input clock signal.

10 10 Signals UG Signal Width Direction Description reset 1 Input Active-high logic reset signal. 1 Input Optional. This active-high signal initiates rereading the current EMR content. The EMR content is updated when the device detects a new error. The EMR contains the error until a new error is detected, even if internal or external scrubbing corrects the error. 1 Output Indicates that a CRC error is detected. This signal is synchronized to the EMR Unloader IP core clock port. _pin 1 Output Connect this signal to the CRC_Error pin. This signal is synchronous to the device's internal oscillator. _clk 1 Input CRC Error Verify IP core input clock signal. _reset 1 Input CRC Error Verify IP core active-high logic reset signal. [N:0] 46, 67, or 119 Output This data port contains the device's error message register contents, as defined in the device handbook SEU mitigation chapter. Arria 10 devices have 119-bit EMRs Stratix V, Arria V, and Cyclone V devices have 67-bit EMRs Older devices have 46-bit EMRs The EMR output signals comply with the Avalon-ST interface definition. N is 46, 67, or Output Active high when the signal contents are valid. This signal complies with the Avalon-ST interface definition. 1 Output This signal is active high when the current EMR output transfer has an error and should be ignored. Typically, this signal indicates that the EMR input clock is too slow. This signal complies with the Avalon-ST interface definition. endoffullchip 1 Output Optional output signal that indicates the end of each full-chip error detection cycle for the entire device. Stratix V, Arria 10, Arria V, and Cyclone V devices only. Note: Refer to the CRC Error Verify IP core documentation for more information.

11 UG Timing 11 Timing The EMR Unloader IP core requires two clock cycles for the device error message circuitry, plus the following additional EMR Unloader input clock cycles to unload EMR content: N + 3 where N is the signal width. 122 clock cycles for Arria clock cycles for Stratix V, Arria V, and Cyclone V 49 clock cycles for Stratix IV, Arria II GX, and Arria II GZ Arria 10 Timing The following waveforms show the EMR Unloader IP core timing behavior for Arria 10 devices. Figure 6: Signal for Correctable Errors (0 < V-Type < 3'b111) Timing Diagram Column Error Detection Pulse 3 b0 < EMR V-Type < 3 b111 Frame Error Detection and Correction Pulse xxxxxxxxxxxxxxxxxx Figure 7: Signal for Correctable Errors after Power Up Only (V-Type == 3'b0) Column Error Detection Pulse Only EMV V-Type == 3 b xxxxxxxxxxxxxxxx... Figure 8: Signal for Uncorrectable Errors Column Error Detection Pulse Only EMV V-Type == 3 b xxxxxxxxxxxxxxxx...

12 12 All Other Device Timing Figure 9: Timing Diagram UG Column Error Detection Pulse Frame Error Detection Pulse Next Error Column Error Detection Pulse In the case of 2 consecutive SEU errors, the IP core asserts for the lost EMR content. The IP core asserts if the falling edge of the pulse for the next error is detected before the core loads the previous content of the EMR user update register into the user shift register. The rising edge of deasserts. is a critical system state and can indicate that the EMR Unloader input clock is too slow. All Other Device Timing The following waveforms show the EMR Unloader IP core timing behavior for Stratix V, Stratix IV, Arria V, Arria II GZ, Arria II GX, and Cyclone V devices. Figure 10: Timing Diagram Figure 11: Timing Diagram

13 UG Document Revision History (EMR Unloader UG) 13 Figure 12: Example EMR Errors Timing Diagram Can Be Asserted for Three Consecutive Frames clock No Is Asserted for Two Consecutive Frames Document Revision History (EMR Unloader UG) Table 5: Document Revision History Date Version Changes June Updated Arria 10 support details. December Initial release.

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