Advanced Computer Architecture Pipelining
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1 Advanced Computer Architecture Pipelining Dr. Shadrokh Samavi 1
2 Dr. Shadrokh Samavi 2
3 Some slides are from the instructors resources which accompany the 5 th and previous editions. Some slides are from David Patterson, David Culler and Krste Asanovic of UC Berkeley; Israel Koren of UM Amherst, and Milos Prvulovic of Georgia Tech. Sources of some slides are mentioned at the bottom of the page. Please inform me if I am missing a name in the above list. Dr. Shadrokh Samavi 3 3
4 C.1. What Is Pipelining? Dr. Shadrokh Samavi 4
5 An implementation technique whereby multiple instructions are overlapped in execution. pipe stage throughput machine cycle Dr. Shadrokh Samavi 5
6 IF ID EXE MEM WB Dr. Shadrokh Samavi 6
7 IF Dr. Shadrokh Samavi 7
8 ID Dr. Shadrokh Samavi 8
9 EXE Dr. Shadrokh Samavi 9
10 MEM Dr. Shadrokh Samavi 10
11 WB Dr. Shadrokh Samavi 11
12 Pipelined Dr. Shadrokh Samavi 12
13 Simple RISC Pipeline Clock number Instruction number Instruction i IF ID EX MEM WB Instruction i + 1 IF ID EX MEM WB Instruction i + 2 IF ID EX MEM WB Instruction i + 3 IF ID EX MEM WB Instruction i + 4 IF ID EX MEM WB Dr. Shadrokh Samavi 13
14 Review: Visualizing Pipelining Time (clock cycles) I n s t r. Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Ifetch DMem DMem O r d e r Ifetch Ifetch DMem DMem Adapted from Patterson, Katz and Kubiatowicz UCB Dr. Shadrokh Samavi 14
15 Dr. Shadrokh Samavi 15
16 C.2. Pipeline Hazards Dr. Shadrokh Samavi 16
17 Hazards: circumstances that would cause incorrect execution if next instruction were launched Structural hazards: Attempting to use the same hardware to do two different things at the same time Data hazards: Instruction depends on result of prior instruction still in the pipeline Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps). Dr. Shadrokh Samavi 17
18 Average instruction time unpipelined Speedup from pipelining = Average instruction time pipelined Assuming same Clock cycle for pipelined & unpipelined = = CPI unpipelined Clock cycle unpipelined CPI pipelined Clock cycle pipelined - CPI unpipelined Clock cycle unpipelined CPI pipelined Clock cycle pipelined CPI pipelined = Ideal CPI + Pipeline stall clock cycles per instruction = 1 + Pipeline stall clock cycles per instruction Speedup= Speedup = Speedup from pipelining = CPI unpipelined Pipeline stall cycles per instruction Pipeline depth Pipeline stall cycles per instruction CPI unpipelined CPI pipelined Clock cycle unpipelined Clock cycle pipelined = Pipeline stall cycles per instruction Clock cycle unpipelined Clock cycle pipelined Dr. Shadrokh Samavi 18
19 Example: Structural Hazard Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t r. O r d e r Load Ifetch Instr 1 Instr 2 Instr 3 Instr 4 Ifetch Ifetch DMem Ifetch DMem DMem DMem Structural Hazard Dr. Shadrokh Samavi 19
20 Resolving structural hazards Definition of structural hazard: attempt to use same hardware for two different things at the same time Solution 1: Wait (stall) must detect the hazard must have mechanism to stall Solution 2: Use more hardware Dr. Shadrokh Samavi 20
21 Detecting and Resolving Structural Hazard Time (clock cycles) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t r. O r d e r Load Ifetch Instr 1 Instr 2 Stall Instr 3 Ifetch Ifetch DMem DMem DMem Bubble Bubble Bubble Bubble Bubble Ifetch DMem Adapted from Patterson, Katz and Kubiatowicz UCB Dr. Shadrokh Samavi 21
22 Eliminating Structural Hazards at Design Time WB Data Next PC 4 Adder Next SEQ PC RS1 Next SEQ PC Zero? MUX Address Instr Cache IF/ID RS2 File ID/EX MUX MUX EX/MEM Data Cache MEM/WB MUX Datapath Imm Sign Extend RD RD RD Control Path Dr. Shadrokh Samavi 22
23 Instruction strip off signals for execution phase WB strip off signals for memory phase Control Generation M EX WB M strip off signals for write-back phase WB Dst Op Src Branch MemRead MemWrite Memto Write IF/ID ID/EX EX/MEM MEM/WB CSE University of Notre Dame Dr. Shadrokh Samavi 23
24 Role of ISA in Structural Hazard Resolution Simple to determine the sequence of resources used by an instruction opcode tells it all Uniformity in the resource usage Compare MIPS to IA32? MIPS approach => all instructions flow through same 5-stage pipelining Dr. Shadrokh Samavi 24
25 Data Hazards Time (clock cycles) IF ID/RF EX MEM WB I n s t r. add r1,r2,r3 sub r4,r1,r3 Ifetch Ifetch DMem DMem O r d e r and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 Ifetch Ifetch Ifetch DMem DMem DMem Adapted from Patterson, Katz and Kubiatowicz UCB Dr. Shadrokh Samavi 25
26 Program execution order (in instructions) Time (in clock cycles) CC1 CC2 CC3 CC4 CC5 CC6 ADD R1, R2, R3 IM DM LW R4, 0(R1) IM DM SW 12(R1), R4 IM DM Stores require an operand during MEM, and forwarding of that operand is shown here Dr. Shadrokh Samavi 26
27 Data Hazards Classification Resource Objects (R.O.): all addressable locations Data Objects (D.O.): content of resource objects D(I): Domain of instruction I = all R.O. that their D.O. effect the operation of I. R(I): Range of instruction I = all R.O. that their D.O. are effected by the execution of I. Dr. Shadrokh Samavi 27
28 A RAW hazard exists on register if R ( i ) D( j ) A WAW hazard exists on register if R( i ) R(j ) A WAR hazard exists on register if D( i ) R (j ) Dr. Shadrokh Samavi 28
29 D(I) I write R(I) D(J) J Read D(J) RAW D(I) D(J) I write J write R(I) R(J) WAW D(J) J write D(I) R(J) I Read D(I) WAR Dr. Shadrokh Samavi 29
30 Three Generic Data Hazards Read After Write (RAW) Instr J tries to read operand before Instr I writes it I: add r1,r2,r3 J: sub r4,r1,r3 Caused by a Data Dependence (in compiler nomenclature). This hazard results from an actual need for communication. Dr. Shadrokh Samavi 30
31 Three Generic Data Hazards Write After Read (WAR) Instr J writes operand before Instr I reads it I: sub r4,r1,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Called an anti-dependence by compiler writers. This results from reuse of the name r1. Can t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Reads are always in stage 2, and Writes are always in stage 5 Dr. Shadrokh Samavi 31
32 Three Generic Data Hazards Write After Write (WAW) Instr J writes operand before Instr I writes it. I: sub r1,r4,r3 J: add r1,r2,r3 K: mul r6,r1,r7 Called an output dependence by compiler writers This also results from the reuse of name r1. Can t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Writes are always in stage 5 Will see WAR and WAW in later more complicated pipes Dr. Shadrokh Samavi 32
33 Forwarding to Avoid Data Hazard Time (clock cycles) I n s t r. add r1,r2,r3 sub r4,r1,r3 Ifetch Ifetch DMem DMem O r d e r and r6,r1,r7 or r8,r1,r9 Ifetch DMem Ifetch DMem xor r10,r1,r11 Ifetch DMem Dr. Shadrokh Samavi 33
34 Data Hazard Even with Forwarding Time (clock cycles) I n s t r. lw r1, 0(r2) sub r4,r1,r6 Ifetch Ifetch DMem DMem O r d e r and r6,r1,r7 or r8,r1,r9 Ifetch Ifetch DMem DMem Adapted from Patterson, Katz and Kubiatowicz UCB Dr. Shadrokh Samavi 34
35 Resolving this load hazard Adding hardware?... not Detection? Compilation techniques? What is the cost of load delays? Dr. Shadrokh Samavi 35
36 Resolving the Load Data Hazard I n s t r. O r d e r Time (clock cycles) lw r1, 0(r2) sub r4,r1,r6 and r6,r1,r7 or r8,r1,r9 Ifetch DMem Ifetch Ifetch Bubble Bubble Bubble DMem DMem Ifetch How is this different from the instruction issue stall? DMem Dr. Shadrokh Samavi 36
37 Software Scheduling to Avoid Load Hazards Try producing fast code for a = b + c; d = e f; assuming a, b, c, d,e, and f in memory. Slow code: LW Rb,b Fast code: LW Rb, b LW Rc,c LW Rc, c ADD Ra,Rb,Rc LW Re,e SW a,ra ADD Ra, Rb, Rc LW Re,e LW Rf, f LW Rf,f SW a,ra SUB Rd,Re,Rf SUB Rd, Re, Rf SW d,rd SW d,rd Dr. Shadrokh Samavi 37
38 Instruction Set Connection What is exposed about this organizational hazard in the instruction set? k cycle delay? bad, CPI is not part of ISA k instruction slot delay load should not be followed by use of the value in the next k instructions Nothing, but code can reduce run-time delays MIPS did the transformation in the assembler Dr. Shadrokh Samavi 38
39 Fraction of loads that cause a stall compress eqntott espresso 23% 24% 20% 20% gcc li doduc ear hydro2d mdljdp su2cor 45% 40% 41% 35% 30% 25% 24% 20% 15% 10% 12% 10% 10% 5% 4% 0% Benchmark Dr. Shadrokh Samavi 39
40 Control Hazard on Branches => Three Stage Stall 10: beq r1,r3,36 Ifetch DMem 14: and r2,r3,r5 Ifetch DMem 18: or r6,r1,r7 Ifetch DMem 22: add r8,r1,r9 Ifetch DMem 36: xor r10,r1,r11 Ifetch DMem Dr. Shadrokh Samavi 40
41 Example: Branch Stall Impact If 30% branch, Stall 3 cycles significant Two part solution: Determine branch taken or not sooner, AND Compute taken branch address earlier MIPS branch tests if register = 0 or 0 MIPS Solution: Move Zero test to ID/RF stage Adder to calculate new PC in ID/RF stage 1 clock cycle penalty for branch versus 3 Dr. Shadrokh Samavi 41
42 compress 3% 3% 11% eqntott 2% 2% 22% Benchmark espresso gcc li doduc ear 1% 2% 2% 4% 3% 4% 4% 4% 4% 6% 6% 8% 11% 11% 12% The frequency of instructions that may change the PC hydro2d 0% 2% 10% mdljdp su2cor 0% 0% 2% 1% 1% 9% 0% 5% 10% 15% 20% 25% Percentage of instructions executed Forward conditional branches Backward conditional branches Unconditional branches Dr. Shadrokh Samavi 42
43 Four Branch Hazard Alternatives #1: Stall until branch direction is clear #2: Predict Branch Not Taken Execute successor instructions in sequence Squash instructions in pipeline if branch actually taken Advantage of late pipeline state update 47% MIPS branches not taken on average PC+4 already calculated, so use it to get next instruction #3: Predict Branch Taken 53% MIPS branches taken on average But haven t calculated branch target address in MIPS» MIPS still incurs 1 cycle branch penalty» Other machines: branch target known before outcome Dr. Shadrokh Samavi 43
44 Four Branch Hazard Alternatives #4: Delayed Branch Define branch to take place AFTER a following instruction branch instruction sequential successor 1 sequential successor 2... sequential successor n... branch target if taken Branch delay of length n 1 slot delay allows proper decision and branch target address in 5 stage pipeline MIPS uses this Dr. Shadrokh Samavi 44
45 Delayed Branch Where to get instructions to fill branch delay slot? Before branch instruction From the target address: only valuable when branch taken From fall through: only valuable when branch not taken Canceling branches allow more slots to be filled Compiler effectiveness for single branch delay slot: Fills about 60% of branch delay slots About 80% of instructions executed in branch delay slots useful in computation About 50% (60% x 80%) of slots usefully filled Delayed Branch downside: 7-8 stage pipelines, multiple instructions issued per clock (superscalar) Dr. Shadrokh Samavi 45
46 (a) From before (b) From target (c) From fall through ADD R1, R2, R3 if R2 = 0 then Delay slot SUB R4, R5, R6 ADD R1, R2, R3 if R1 = 0 then Delay slot ADD R1, R2, R3 if R1 = 0 then Delay slot OR R7, R8, R9 SUB R4, R5, R6 Becomes Becomes Becomes if R2 = 0 then ADD R1, R2, R3 SUB R4, R5, R6 ADD R1, R2, R3 if R1 = 0 then SUB R4, R5, R6 ADD R1, R2, R3 if R1 = 0 then OR R7, R8, R9 SUB R4, R5, R6 Dr. Shadrokh Samavi 46
47 Canceling or Nullifying Branch. In a canceling branch, the instruction includes the direction that the branch was predicted. When the branch behaves as predicted, the instruction in the branch-delay slot is simply executed as it would normally be with a delayed branch. When the branch is incorrectly predicted, the instruction in the branch-delay slot is simply turned into a no-op. Dr. Shadrokh Samavi 47
48 Delayed-branch scheduling schemes Scheduling strategy Requirements Improves performance when? (a) From before. Branch must not depend on the rescheduled instructions Always. (b) From target (c) From fall through Must be OK to execute rescheduled instructions if branch is not taken. May need to duplicate instructions. Must be OK to execute instructions if branch is taken. When branch is taken. May enlarge program if instructions are duplicated. When branch is not taken. Dr. Shadrokh Samavi 48
49 Branch is NOT TAKEN (wrong prediction) Branch is TAKEN ( predicted correctly) The behavior of a predicted-taken canceling branch depends on whether the branch is taken or not. Dr. Shadrokh Samavi 49
50 Delayed and Canceling Delay Branches Dr. Shadrokh Samavi 50
51 Overall costs of a variety of branch schemes Dr. Shadrokh Samavi 51
52 For an R4000-style pipeline, it takes 3 pipeline stages before the branch target address is known & 1 more cycle to evaluate branch condition. This leads to the following branch penalties: Find the effective addition to the CPI arising from branches given that the relative frequency of unconditional, conditional untaken, and conditional taken branches are 4%, 6%, and 10%, respectively. Dr. Shadrokh Samavi 52
53 Control Hazards 1. Find out whether the branch is taken or not taken earlier in the pipeline. 2. Compute the taken PC (i.e., the address of the branch target) earlier. Branch instruction IF ID EX MEM WB Branch successor IF stall stall IF ID EX MEM WB Branch successor + 1 IF ID EX MEM WB Branch successor + 2 IF ID EX MEM Branch successor + 3 IF ID EX Branch successor + 4 IF ID Branch successor + 5 IF Dr. Shadrokh Samavi 53
54 C.3.Implementation of Pipelining Dr. Shadrokh Samavi 54
55 Instruction fetch Instruction decode/ register fetch Execute/ Address calculation Memory access Write back Dr. Shadrokh Samavi 55
56 IF ID EX M E M IF/ID ID/EX EX/MEM MEM/WB WB INST 1 INST 2 Dr. Shadrokh Samavi 56
57 Events on every pipe stage of the MIPS pipeline. Dr. Shadrokh Samavi 57
58 5 Steps of MIPS Datapath Inst 1 WB Data Instruction Fetch Instr. Decode. Fetch Execute Addr. Calc Memory Access Write Back Next PC Next SEQ PC 4 Adder RS1 Next SEQ PC Zero? MUX Address Memory IF/ID RS2 File ID/EX MUX MUX EX/MEM Memory MEM/WB MUX Datapath Imm Sign Extend RD RD RD Control Path Dr. Shadrokh Samavi 58
59 5 Steps of MIPS Datapath Inst 2 Inst 1 WB Data Instruction Fetch Instr. Decode. Fetch Execute Addr. Calc Memory Access Write Back Next PC Next SEQ PC 4 Adder RS1 Next SEQ PC Zero? MUX Address Memory IF/ID RS2 File ID/EX MUX MUX EX/MEM Memory MEM/WB MUX Datapath Imm Sign Extend RD RD RD Control Path Dr. Shadrokh Samavi 59
60 5 Steps of MIPS Datapath Inst 3 Inst 2 Inst 1 WB Data Instruction Fetch Instr. Decode. Fetch Execute Addr. Calc Memory Access Write Back Next PC Next SEQ PC 4 Adder RS1 Next SEQ PC Zero? MUX Address Memory IF/ID RS2 File ID/EX MUX MUX EX/MEM Memory MEM/WB MUX Datapath Imm Sign Extend RD RD RD Control Path Dr. Shadrokh Samavi 60
61 Dr. Shadrokh Samavi 61
62 Situation No dependence Dependence requiring stall Dependence overcome by forwarding Dependence with accesses in order Example code sequence LWR1,45(R2) ADD R5,R6,R7 SUB R8,R6,R7 OR R9,R6,R7 LWR1,45(R2) ADD R5,R1,R7 SUB R8,R6,R7 OR R9,R6,R7 LWR1,45(R2) ADD R5,R6,R7 SUB R8,R1,R7 OR R9,R6,R7 LWR1,45(R2) ADD R5,R6,R7 SUB R8,R6,R7 OR R9,R1,R7 Action No hazard possible because no dependence exists on R1 in the immediately following three. instructions Comparators detect the use of R1 in the ADD and stall the ADD (and SUB and OR) before the ADD begins EX. Comparators detect use of R1 in SUB and forward result of load to in time for SUB to begin EX. No action required because the read of R1 by OR occurs in the second half of the ID phase, while the write of the loaded data occurred in the first half. Situations that the pipeline hazard detection hardware can see by comparing the destination and sources of adjacent instructions. Dr. Shadrokh Samavi 62
63 Forwarding of data Pipeline register containing source instruction EX/MEM Opcode of source instruction Pipeline register containing destination instruction ID/EX Opcode of destination instruction ister-register, immediate, load, store, branch Destination of the forwarded result Top input EX/MEM isterregister, ID/EX ister-register, Bottom input MEM/WB isterregister, ID/EX ister-register, immediate, load, store, branch Comparison (if equal then forward) EX/MEM.IR == ID/EX.IR EX/MEM.IR == ID/EX.IR MEM/WB.IR == ID/EX.IR MEM/WB isterregister, input ID/EX.IR ID/EX ister-register Bottom MEM/WB.IR == EX/MEM EX/MEM MEM/WB MEM/WB isterregister, immediate immediate immediate immediate ID/EX ister-register immediate, load, store, branch EX/MEM.IR == ID/EX.IR ID/EX ister-register Bottom EX/MEM.IR == input ID/EX.IR ID/EX MEM/WB Load ID/EX ister-register immediate, load, store, branch MEM/WB.IR == ID/EX.IR ID/EX ister-register Bottom MEM/WB.IR == input ID/EX.IR ister-register immediate, load, store, branch Top input Top input Top input Top input MEM/WB.IR == ID/EX.IR MEM/WB Load ID/EX ister-register Bottom MEM/WB.IR == input ID/EX.IR Dr. Shadrokh Samavi 63
64 HW Change for Forwarding NextPC isters Immediate ID/EX mux mux EX/MEM Data Memory MEM/WR mux Dr. Shadrokh Samavi 64
65 WB Data Instruction Fetch Instr. Decode. Fetch Execute Addr. Calc Memory Access Write Back Next PC 4 Adder Next SEQ PC RS1 Next SEQ PC Zero? MUX Address Memory IF/ID RS2 File ID/EX MUX MUX EX/MEM Memory MEM/WB MUX Datapath Imm Sign Extend RD RD RD Dr. Shadrokh Samavi 65
66 Pipelined MIPS Datapath WB Data Instruction Fetch Instr. Decode. Fetch Execute Addr. Calc Memory Access Write Back Next PC 4 Adder Next SEQ PC RS1 Adder MUX Zero? Address Memory IF/ID RS2 File ID/EX MUX EX/MEM Data Memory MEM/WB MUX Imm Sign Extend RD RD RD Data stationary control local decode for each instruction phase / pipeline stage Dr. Shadrokh Samavi 66
67 C.5. Multicycle Operations Dr. Shadrokh Samavi 67
68 The MIPS pipeline with three additional unpipelined, floating-point, functional units. Dr. Shadrokh Samavi 68
69 Latency : the number of intervening cycles between an instruction that produces a result and an instruction that uses the result. The initiation or repeat interval: the number of cycles that must elapse between issuing two operations of a given type. Dr. Shadrokh Samavi 69
70 Dr. Shadrokh Samavi 70
71 The pipeline timing of a set of independent FP operations. A typical FP code sequence showing the stalls arising from RAW hazards. Dr. Shadrokh Samavi 71
72 Three instructions want to perform a write back to the FP register file simultaneously, as shown in clock cycle 11. Dr. Shadrokh Samavi 72
73 Dr. Shadrokh Samavi 73
74 Dr. Shadrokh Samavi 74
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