Fan-Out and Embedded Die: Technologies & Market Trends

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1 From Technologies to Market Fan-Out and Embedded Die: Technologies & Market Trends Sample February 2015

2 REPORT OUTLINES Report scope & definitions Embedded Die in substrates o Scope of the report o Motivations and drivers o Companies cited in this report o Products and technologies o Glossary Products available Executive summary Roadmaps Advanced packaging growth o Supply chain Fan-Out platform Players and positioning within the supply chain o Motivations and drivers o Embedded Die Package commercialization status o Products and technologies o Market forecasts Products available o Equipment & materials Roadmaps Challenges related to yield & supply chain o Supply chain for FOWLP Cost considerations Players and positioning within the supply chain Conclusions & perspectives o FOWLP commercialization status Company presentation o Market forecasts o Equipment & materials Improvement of materials Panel for FOWLP status 2

3 REPORT SCOPE The main objectives of this report are the following: o To update the business status of both embedded wafer level package technologies (FOWLP and Embedded Die Package) markets o To provide a market forecast for the coming years, and estimate future trends o To analyze key market drivers, benefits and challenges of embedded wafer level packages by application o To describe the different existing technologies, their trends and the roadmaps The FOWLP and Embedded Die Package markets are studied from the following angles o State-of-the-art technology and trends o End-user applications and drivers o Market value o Industrial supply chain & value chain 3

4 THE EVOLUTION OF SEMICONDUCTOR PACKAGING A bridging technology between ICs and PCBs Development in CMOS processing capabilities Development in PCB processing capabilities Feature sizes of PCBs Packaging fills the gap in between ICs and PCBs improvement speeds Feature sizes CMOS transistors: 28nm 1970 Through hole technology 1980 Surface mount devices 1990 CSPs/BGAs SiPs 2000 WLCSP more SiPs Flip Chip BGA PoP DIC TSV Fan-out WLCSP Cu pillars Silicon interposers 4

5 PACKAGING ADDED VALUE: More Moore and More than Moore More Than Moore : diversification Biochips Passives Power Sensors Energy Sources Analog + RF SiP 3D integration is seen today as a new paradigm for the future of the semiconductor industry, as it will enable several more decades of chip evolution at ever lower cost, higher performance and smallersize features. 3D approach allows to get all the benefit from chip miniaturization and package integration MEMS IPD GaAS RF SMOS Analog Power Non Volatile Memory RF CMOS Low Power CMOS High Perf. SOI SoC 130nm 90nm 65nm 45nm 32nm 22nm 14nm 10nm More Moore : miniaturization 5

6 WAFER-LEVEL-PACKAGING MARKET DRIVERS I/Os density Cost Lower packaging cost Lower test cost Batch processing Panel capability Form-factor Smallest thickness of the market Smaller thickness Lower footprint Numerous market drivers lead to a WLP solution Lower pitches No standard Smaller dies Higher density of I/Os Integration Low pitch capability Integration capability WLP Improve chip-to-board coupling New materials Lower thickness Multiple RDL Interconnect optimization Electrical performance Smaller Interconnect lines Higher frequencies Higher ackage speed Lower parasitics IPD SiP 3D Thermal performance Lower power consumption Higher package density 6

7 TWO TYPES OF EMBEDDED WAFER-LEVEL-PACKAGES There are two main substrate types for embedding technologies A different approach depending on substrate type: FOWLP is based on a reconfigured molded wafer infrastructure Embedded die in package is based on a PCB type of panel infrastructure 7

8 FAN-OUT WLP PRINCIPLE Tape lamination Carrier with foil and chips Carrier (Metal) Pick and place Embedding in a molding compound allow thin packaging Wafer level Molding Carrier removal / de-bonding Molding with liquid moldcompound Reconstituted wafer after molding Standard WLB process (Passivation, pattern, RDL, bonding) After singulation Dicing WLP Fan-Out wafer Source: Infineon 8

9 FAN-OUT WLP KEY DIFFERENTIATORS Smaller footprint and thinner package than Flip-Chip BGA Lower thermal resistance compared to Flip-Chip BGA Fan-out zone adaptable to customer needs Better board level reliability compared to WL-CSP Numerous advantages position FOWLP as a promising solution Reliable, miniaturized high performance package High degree of package design freedom Mold Chip RoHS and REACH compliant package Excellent electrical performance Shorter interconnections No restriction in bump pitch No laminate substrate required Simplified supply chain and manufacturing infrastructure 9

10 FAN-OUT WLP DRIVERS:WHERE IS THE THRESHOLD? D i e s i z e ( m m / s i d e ) A lot of products are already packaged using Fan-in solution which is cheaper than Fan-Out FOWLP has a sweet spot area where Fan-In cannot fit Fan-in Fan-out P i n s - c o u n t With die size reduction and higher pins count manufacturers will have two options: Reducing ball pitch in order to have more connections within the die surface Going Fan-Out and allowing an easier redistribution Since pitch reduction is very challenging, Fan-Out approach is offering a good opportunity 10

11 FAN-OUT POTENTIAL APPLICATIONS Opportunities for FOWLP in mobile phones Orange: Devices that can be found in FOWLP packages today Green: Devices that could be found in the future in FOWLP FOWLP has the potential to fit in many applications Discrete passives Grey: Devices that will likely remain on WLCSP or flip-chip package or move to 3DIC 11

12 FOWLP ACTIVITIES: GLOBAL MAP OF MAIN PLAYERS FOWLP catches the interest of many companies 12

13 FAN-OUT WLP: TECHNICAL CHALLENGES Topography Warpage Chip-to-mold nonplanarity FOWLP technical challenges to overcome Mold IC 1 IC 2 Reliability Die shift 13

14 TECHNOLOGY ROADMAP FOR FOWLP Key parameters Maximum package size Roadmap of FOWLP follows the high demanding expectations from the market Max level of RDL Line/Space Package minimum thickness (with BGA) Minimum die side size Minimum mold clearance distance Minimum bump pitch Minimum die-to-die distance 14

15 FOWLP ACTIVITY MARKET FORECAST FO-WLP revenues (M $) $900M FOWLP activity revenues (M$) Overall evolution since ewlb technology introduction Yole Developpement Ramp-up with fab-less wireless IC players and wide FOWLP infrastructure/supply-chain A high growth is expected $600M $300M Transition phase CAGR ~ 10% $0M

16 EMBEDDED DIE PACKAGING PROCESS FLOW Example with chip-first face-up approach 1) Die Bonding Adhesive on copper foil Principle of embedded die package in substrate 2) Lamination 3) Laser drilling Pick & place on copper foil Relamination process 3) Structuring Source:AT&S Copper plating, imaging and etching 16

17 EMBEDDED DIE PACKAGE KEY DIFFERENTIATORS Small footprint thanks to more space given to surface components Reduced parasitics thanks to short interconnections High mechanical reliability Embedded Die package advantages High potential for components integration High potential for reducing I/Os thanks to design (wire-bond layout) Chip Laminated PCB Improved thermal performance thanks to proximity with active High design flexibility since chip can be positioned wherever we want New suppliers Low manufacturing cots thanks to very mature products Good for copy protection 17

18 EMBEDDED DIE PACKAGING Technical challenges Resolution Warpage Embedded Die Package technical challenges to overcome Embedded SiP Die positionning Yield 18

19 EMBEDDED DIE PACKAGING: A NEW SUPPLY CHAIN PCB manufacturers can create a new supply chain in semiconductor industry 1) Die Customization (IDM or Wafer Level Technology Provider) Embedded Die Customization Wafer thinning 2)Embedded Die Substrate Fabrication (PCB manufacturer) Embedded Die PCB sort Component placement 3) Product level assembly and final testing Solder paste print Component placement and reflow Wafer sort / Die preparation Multi-layer build up fabrication Product level assembly and test PCB Core Fabrication Supply chain and responsibilities can be defined case by case upon players will of implication Embedded die packaging opens the door for substrate suppliers to realize the whole packaging, assembly and test themselves Good opportunity for substrate suppliers to create new business and potential threat for OSATs market 19

20 TECHNOLOGY ROADMAP FOR EMBEDDED DIE Key parameters Roadmap of Embedded Die package shows the targets to achieve before being fully competitive in mobile market Pad Pitch on die Chip layer stacking Line/Space Package minimum thickness Chip thickness (min-max) Today, Embedded Die Packaging technology only targets low-cost, low I/O pin-count applications (mainly power and analog ICs) However, to enter the digital space and more complex SiP module realization, embedded die technologies are set to evolve 20

21 EMBEDDED DIE ACTIVITY MARKET FORECAST Embedded die package revenues forecast (M$) Overall evolution since technology introduction $300M Embedded Die package market is still a niche $200M $100M $0M

22 Yole Développement From Technologies to Market 2015

23 FIELDS OF EXPERTISE Yole Développement s 30 analysts operate in the following areas Imaging Photonics MEMS & Sensors MedTech Compound Semi. LED/OLED Manufacturing Power Electronics PV Advanced Packaging Name of the report 23

24 4 BUSINESS MODELS o Consulting and Analysis Market data & research, marketing analysis Technology analysis Strategy consulting Reverse engineering & costing Patent analysis o Financial services M&A (buying and selling) Due diligence Fundraising Maturation of companies IP portfolio management & optimization Blu Morpho o Reports o Media Market & Technology reports i-micronews.com website Patent Investigation and patent infringement e-newsletter analysis Technology magazines Teardowns & Reverse Costing Analysis Communication & webcast services Cost Simulation Tool Events 24

25 A GROUP OF COMPANIES M&A operations Due diligences Market, technology and strategy consulting Fundraising Maturation of companies IP portfolio management & optimization Manufacturing costs analysis Teardown and reverse engineering Cost simulation tools IP analysis Patent assessment 25

26 OUR GLOBAL ACTIVITY Yole Korea Yole Japan Yole Inc. 40% of our business is in EU countries 30% of our business is in Asia 30% of our business is in North America 26

27 SERVING THE ENTIRE SUPPLY CHAIN Integrators and end-users Our analysts provide market analysis, technology evaluation, and business plan along the entire supply chain Device makers Suppliers: material, equipment, OSAT, foundries Financial investors, R&D centers 27

28 CONTACT INFORMATION o Consulting and Specific Analysis North America: Steve LaFerriere, Director of Northern America Business Development, Yole Inc. Japan: Yutaka Katano, General Manager, Yole Japan & President, Yole K.K. RoW: Jean-Christophe Eloy, President & CEO, Yole Développement o Report business North America: Steve LaFerriere, Director of Northern America Business Development, Yole Inc. Europe: Fayçal El Khamassi, Headquarter Sales Coordination & Customer Service Japan & Asia: Takashi Onozawa, Sales Asia & General Manager, Yole K.K. Korea: Hailey Yang, Business Development Manager, Korean Office o Financial services o General Jean-Christophe Eloy, CEO & President Follow us on 28

29 ORDER FORM Fan-Out and Embedded Dies: Technologies & Market Trends BILL TO Name (Mr/Ms/Dr/Pr): Job Title: Company: Address: PAYMENT BY CREDIT CARD Visa Mastercard Amex Name of the Card Holder: Credit Card Number: City: State: Postcode/Zip: Country*: *VAT ID Number for EU members: Tel: Card Verification Value (3 digits except AMEX: 4 digits): Expiration date: By bank transfer BANK INFO: HSBC, 1 place de la Bourse, F Lyon, France, Bank code: 30056, Branch code : Account No: , SWIFT or BIC code: CCFRFRPP, IBAN: FR / Date: PRODUCT ORDER Please enter my order for above named report: One user license*: Euro 3,990 Multi user license: Euro 5,990 *One user license means only one person at the company can use the report. Please be aware that our publication will be watermarked on each page with the name of the recipient and of the organization (the name mentioned on the PO). This watermark will also mention that the report sharing is not allowed. For price in dollars, please use the day s exchange rate. All reports are delivered electronically at payment reception. For French customers, add 20% for VAT. Buy more than 3 reports and get significant discount. Do not hesitate to contact us. I hereby accept Yole Développement s Terms and Conditions of Sale (1) Signature: Return order by FAX: +33 (0) MAIL: YOLE DÉVELOPPEMENT, Le Quartz, 75 Cours Emile Zola, Villeurbanne/Lyon - France SALES CONTACTS North America: Steve Laferriere - Japan & Asia: Takashi Onozawa - Europe & RoW: Faycal El Khamassi - Korea: Hailey Yang - General: (1) Our Terms and Conditions of Sale are available at The present document is valid 24 months after its publishing date: Feb. 18, SHIPPING contact First Name: Last Name: Phone: ABOUT YOLE DEVELOPPEMENT Founded in 1998, Yole Développement has grown to become a group of companies providing marketing, technology and strategy consulting, media in addition to corporate fi nance services. With a strong focus on emerging applications using silicon and/or micro manufacturing (technology or process), Yole Développement group has expanded to include more than 50 associates worldwide covering MEMS, Compound Semiconductors, LED, Image Sensors, Optoelectronics, Microfl uidics & Medical, Photovoltaics, Advanced Packaging, Manufacturing, Nanomaterials and Power Electronics. The group supports industrial companies, investors and R&D organizations worldwide to help them understand markets and follow technology trends to develop their business. CONSULTING Market data & research, marketing analysis Technology analysis Reverse engineering & costing services Strategy consulting Patent analysis More information on FINANCIAL SERVICES Mergers & Acquisitions Due diligence Fundraising Coaching of emerging companies IP portfolio management & optimization More information on REPORTS Collection of technology & market reports Manufacturing cost simulation tools Component reverse engineering & costing analysis Patent investigation More information on MEDIA & EVENTS i-micronews.com, online disruptive technologies weekly e-newsletter Technology Magazines dedicated to MEMS, Advanced Packaging, LED and Power Electronics Communication & webcasts services Events: Yole Seminars, Market Briefings More information on CONTACTS For more information about: For more information about : Consulting Services: Jean-Christophe Eloy Financial Services: Jean-Christophe Eloy Report Business: David Jourdan Corporate Communication: Sandrine Leroy

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