INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC6 74HC/HCT/HCU/HCMOS ogic Package Information The IC6 74HC/HCT/HCU/HCMOS ogic Package Outlines 74HC/HCT46 File under Integrated Circuits, IC6 December 99

2 74HC/HCT46 FEATURES Output capability: standard I CC category: MSI GENERA DESCRIPTION The 74HC/HCT46 are high-speed Si-gate CMOS devices and are pin compatible with the 46 of the 4B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT46 are edge-triggered synchronous up/down 4-bit binary counters with a clock input (CP), an up/down count control input (UP/DN), an active OW count enable input (CE), an asynchronous active HIGH parallel load input (P), four parallel inputs (D to D ), four parallel outputs (Q to Q ), an active OW terminal count output (TC), and an overriding asynchronous master reset input (MR). Information on D to D is loaded into the counter while P is HIGH, independent of all other input conditions except the MR input, which must be OW. When P and CE are OW, the counter changes on the OW-to-HIGH transition of CP. UP/DN determines the direction of the count, HIGH for counting up, OW for counting down. When counting up, TC is OW when Q to Q are HIGH and CE is OW. When counting down, TC is OW when Q to Q and CE are OW. A HIGH on MR resets the counter (Q to Q = OW) independent of all other input conditions. ogic equation for terminal count: TC = CE. {(UP/DN). Q.Q.Q 2.Q +(UP DN).Q.Q.Q 2.Q } QUICK REFERENCE DATA GND = V; T amb =2 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS HC HCT UNIT t PH / t PH propagation delay CP to Q n 9 9 ns C = pf; V CC = V f max maximum clock frequency 4 7 MHz C I input capacitance.. pf C PD power dissipation capacitance per package notes and pf Notes. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC For HCT the condition is V I = GND to V CC. V ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS ogic Package Information. December 99 2

3 74HC/HCT46 PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION P parallel load input (active HIGH) 4, 2,, D to D parallel inputs CE count enable input (active OW) 6,, 4, 2 Q to Q parallel outputs 7 TC terminal count output (active OW) 8 GND ground ( V) 9 MR asynchronous master reset input (active HIGH) UP/DN up/down control input CP clock input (OW-to-HIGH, edge-triggered) 6 V CC positive supply voltage Fig. Pin configuration. Fig.2 Fig. IEC logic symbol. December 99

4 74HC/HCT46 FUNCTION TABE H MR P UP/DN CE CP MODE H H H Notes. H = HIGH voltage level = OW voltage level = don t care = OW-to-HIGH clock transition parallel load no change count down count up reset Fig.4 Functional diagram. Fig. Timing diagram. December 99 4

5 74HC/HCT46 Fig.6 ogic diagram. December 99

6 74HC/HCT46 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS ogic Family Specifications. Output capability: standard I CC category: MSI AC CHARACTERISTICS FOR 74HC GND = V; t r =t f = 6 ns; C = pf SYMBO t PH / t PH t PH t PH / t PH t PH / t PH t PH / t PH t PH t PH / t PH PARAMETER propagation delay 72 CP to Q n 26 2 propagation delay 69 MR to Q n 2 2 propagation delay 8 P to Q n propagation delay CP to TC propagation delay CE to TC propagation delay MR to TC propagation delay P to TC T amb ( C) 74HC +2 4 to+8 4 to +2 min. typ. max. min. max. min. max t TH / t TH output transition time t W t W t W clock pulse width CP, CE HIGH or OW parallel load pulse width HIGH master reset pulse width HIGH UNIT TEST CONDITIONS V CC (V) ns ns ns ns ns ns ns ns ns ns ns WAVEFORMS Fig.7 Fig. Fig.9 Fig.7 Fig.8 Fig. Fig.9 Fig.9 Fig.7 Fig. Fig. December 99 6

7 74HC/HCT46 T amb ( C) TEST CONDITIONS SYMBO PARAMETER 74HC +2 4 to+8 4 to +2 min. typ. max. min. max. min. max. UNIT V CC (V) WAVEFORMS t rem t rem t su t su t su t h t h t h f max removal time MR to CP removal time P to CP set-up time UP/DN to CP set-up time CE to CP set-up time D n to P hold time CE to CP hold time D n to P hold time UP/DN to CP maximum clock pulse frequency ns ns ns ns ns ns ns ns MHz Fig. Fig. Fig.8 Fig.8 Fig. Fig.8 Fig. Fig.8 Fig.7 December 99 7

8 74HC/HCT46 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS ogic Family Specifications. Output capability: standard I CC category: MSI Note to HCT types The value of additional quiescent supply current ( I CC ) for a unit load of is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D n P, CE UP/DN CP MR UNIT OAD COEFFICIENT December 99 8

9 74HC/HCT46 AC CHARACTERISTICS FOR 74HCT GND = V; t r =t f = 6 ns; C = pf T amb ( C) TEST CONDITIONS ns Fig ns Fig ns Fig.9 74HCT SYMBO PARAMETER UNIT V +2 4 to +8 4 to+2 CC (V) WAVEFORMS min. typ. max. min. max. min. max. t PH / t PH propagation delay CP to Q n t PH propagation delay MR to Q n t PH / t PH propagation delay P to Q n t PH / t PH propagation delay ns Fig.7 CP to TC t PH / t PH propagation delay ns Fig.8 CE to TC t PH propagation delay 6 7 ns Fig. MR to TC t PH / t PH propagation delay ns Fig.9 P to TC t TH / t TH output transition time ns Fig.9 t W t W t W t rem t rem t su t su t su t h clock pulse width CP, CE HIGH or OW parallel load pulse width HIGH master rest pulse width HIGH removal time MR to CP removal time P to CP set-up time UP/DN to CP set-up time CE to CP set-up time D n to P hold time CE to CP ns Fig ns Fig. 2 2 ns Fig ns Fig ns Fig. 2 2 ns Fig ns Fig ns Fig. 9 ns Fig.8 December 99 9

10 74HC/HCT46 SYMBO t h t h f max PARAMETER hold time D n to P hold time UP/DN to CP maximum clock pulse frequency T amb ( C) 74HCT +2 4 to +8 4 to+2 min. typ. max. min. max. min. max. UNIT TEST CONDITIONS V CC (V) 6 ns Fig. ns Fig MHz Fig.7 WAVEFORMS December 99

11 74HC/HCT46 AC WAVEFORMS () HC : V M = %; V I = GND to V CC. HCT: V M =. V; V I = GND to V. () HC : V M = %; V I = GND to V CC. HCT: V M =. V; V I = GND to V. Fig.7 Waveforms showing the clock (CP) to output (Q n ) and terminal count (TC) propagation delays, the clock pulse width and the maximum clock pulse frequency. Fig.8 Waveforms showing the set-up and hold times form count enable (CE) and up/down (UP/DN) control inputs to the clock pulse (CP), the propagation delays from UP/DN, CE to TC. () HC : V M = %; V I = GND to V CC. HCT: V M =. V; V I = GND to V. () HC : V M = %; V I = GND to V CC. HCT: V M =. V; V I = GND to V. Fig.9 Waveforms showing the preset enable pulse width, preset enable to output delays and output transition times. Fig. Waveforms showing the master reset pulse, master reset to terminal count and Q n delay and master reset to clock removal time. December 99

12 74HC/HCT46 () HC : V M = %; V I = GND to V CC. HCT: V M =. V; V I = GND to V. Fig. Waveforms showing the data set-up and hold times to parallel load (P). December 99 2

13 74HC/HCT46 APPICATION INFORMATION Terminal count (TC) lines at the 2nd, rd, etc. Stages may have a negative-going glitch pulse resulting from differential delays of different 46s. These negative-going glitches do not affect proper 46 operation. However, if the terminal count signals are used to trigger other edge-sensitive logic devices, such as flip-flops or counters, the terminal count signals should be gated with the clock signal using a 2-input OR gate such as HC/HCT2. Fig.2 Cascading counter packages (parallel clocking). Ripple clocking mode: the UP/DN control can be changed at any count. The only restriction on changing the UP/DN control is that the clock input to the first counting stage must be HIGH. For cascading counters operating in a fixed up-count or down-count mode, the OR gates are not required between stages and TC is connected directly to the CP input of the next stage with CE grounded. Fig. Cascading counter packages (ripple clocking). December 99

14 74HC/HCT46 Use the following formulae to calculate N total : N total = f out =f in /N total i π ( 6 N i ) +N Fig.4 State diagram. Fig. Programmable cascaded frequency divider. PACKAGE OUTINES parallel inputs D D 2 D D count-up n count-down n See 74HC/HCT/HCU/HCMOS ogic Package Outlines () () Note. no count; f out is HIGH. December 99 4