FSA2567 Low-Power, Dual SIM Card Analog Switch

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1 Click to see this datasheet in Simplified Chinese! August 2009 Features Low On Capacitance for Data Path: 10pF Typical Low On Resistance for Data Path: 6Ω Typical Low On Resistance for Supply Path: 0.4Ω Typical Wide V CC Operating Range: 1.65V to 4.3V Low Power Consumption: 1μA Maximum - 15μA Maximum I CCT Over Expanded Voltage Range (V IN=1.8V, V CC=4.3V) Wide -3db Bandwidth: > 160MHz Packaged in: - Pb-free 16-Lead MLP & 16-Lead UMLP 3kV ESD Rating, >12kV Power/ ESD Rating Applications Cell phone, PDA, Digital Camera, and Notebook LCD Monitor, TV, and Set-Top Box Description The FSA2567 is a bi-directional, low-power, dual double-pole, double-throw (4PDT) analog switch targeted at dual SIM card multiplexing. It is optimized for switching the WLAN-SIM data and control signals and dedicates one channel as a supply-source switch. The FSA2567 is compatible with the requirements of SIM cards and features a low on capacitance (C ON) of 10pF to ensure high-speed data transfer. The V SIM switch path has a low R ON characteristic to ensure minimal voltage drop in the dual SIM card supply paths. The FSA2567 contains special circuitry that minimizes current consumption when the control voltage applied to the SEL pin is lower than the supply voltage (V CC). This feature is especially valuable in ultra-portable applications, such as cell phones; allowing direct interface with the general-purpose I/Os of the baseband processor. Other applications include switching and connector sharing in portable cell phones, PDAs, digital cameras, printers, and notebook computers. IMPORTANT NOTE: For additional information, please contact analogswitch@fairchildsemi.com. Ordering Information Part Number Top Mark Operating Temperature Range Eco Status FSA2567MPX FSA to +85 C Green FSA2567UMX GX -40 to +85 C Green Package 16-Lead, Molded Leadless Package (MLP) Quad, JEDEC MO-220, 3mm Square 16-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 1.8 x 2.6mm For Fairchild s definition of Eco Status, please visit: 1V SIM 2V SIM 1RST 2RST 1CLK 2CLK 1DAT 2DAT V SIM RST CLK DAT Figure 1. Analog Symbol FSA2567 Rev

2 Pin Assignments 1V SIM 2RST RST 1 2 V SIM 1RST 2V SIM V CC 2CLK 1DAT CLK (Not connected to ) DAT 2DAT No Connect 1CLK Figure 2. Pad Assignment MLP16 (Top Through View) 1V SIM 2RST RST 3 4 V SIM RST 2V SIM V CC 2CLK 1DAT CLK 10 9 DAT 2DAT No Connect 1CLK Figure 3. Pad Assignment UMLP16 (Top Through View) Pin Definitions Pin ndat, nrst, nclk nv SIM V SIM, DAT, RST, CLK Multiplexed Data Source Inputs Multiplexed SIM Supply Inputs Common SIM Ports Switch ect Description Truth Table Logic LOW Logic HIGH Function 1DAT = DAT, 1RST = RST, 1CLK = CLK, 1V SIM = V SIM 2DAT = DAT, 2RST = RST, 2CLK = CLK, 2V SIM = V SIM FSA2567 Rev

3 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V CNTRL DC Input Voltage () (1) -0.5 V CC V V SW DC Switch I/O Voltage (1) -0.5 V CC V I IK DC Input Diode Current -50 ma I SIM DC Output Current - V SIM 350 ma I OUT DC Output Current DAT, CLK, RST 35 ma T STG Storage Temperature C ESD Human Body Model, JEDEC: JESD22-A114 All Pins 3 I/O to 12 Charged Device Model, JEDEC: JESD22-C101 2 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. kv Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit V CC Supply Voltage V V CNTRL Control Input Voltage () (2) 0 V CC V V SW Switch I/O Voltage -0.5 V CC V I SIM DC Output Current - V SIM 150 ma I OUT DC Output Current DAT, CLK, RST 25 ma T A Operating Temperature C Note: 2. The control input must be held HIGH or LOW; it must not float. FSA2567 Rev

4 DC Electrical Characteristics All typical values are at 25 C, 3.3V V CC unless otherwise specified. Symbol Parameter Conditions V CC (V) T A =- 40ºC to +85ºC Min. Typ. Max. V IK Clamp Diode Voltage I IN = -18mA V V IH V IL I IN I nc(off), I no(off), R OND R ONV R OND I CC I CCT Input Voltage High Input Voltage Low Control Input Leakage Off State Leakage Data Path Switch On Resistance (3) V SIM Switch On Resistance (3) 1.65 to to to to Units V SW = 0 to V CC µa nrst, ndat, nclk, nv SIM = 0.3V or 3.6V Figure 10 V SW = 0, 1.8V, I ON = -20mA Figure 9 V SW = 0, 2.3V, I ON = -20mA Figure 9 V SW = 0, 1.8V, I ON = -100mA Figure 9 V SW = 0, 2.3V, I ON = -100mA Figure na Data Path Delta (4) VSW = 0V, ION = -20mA Ω On Resistance Quiescent Supply Current V CNTRL = 0 or V CC, I OUT = µa Increase in I CC Current Per Control V CNTRL = 2.6V, V CC = 4.3V µa Voltage and V CC V CNTRL = 1.8V, V CC = 4.3V µa Notes: 3. Measured by the voltage drop between ndat, nrst, nclk and relative common port pins at the indicated current through the switch. On resistance is determined by the lower of the voltage on the relative ports. 4. Guaranteed by characterization. V V Ω Ω FSA2567 Rev

5 AC Electrical Characteristics All typical value are for V CC=3.3V at 25 C unless otherwise specified. Symbol Parameter Conditions V CC (V) t OND t OFFD t ONV t OFFV Turn-On Time to Output Turn-Off Time to Output Turn-On Time to Output (V SIM) Turn-Off Time to Output (V SIM) t PD Propagation Delay (5) t BBMD t BBMV Q O IRR Xtalk Break-Before-Make (5) Break-Before-Make (5) (V SIM) Charge Injection Off Isolation Non-Adjacent Channel Crosstalk T A =- 40ºC to +85ºC Min. Typ. Max. Units R L = 50Ω, C L = 35pF 1.8 (5) ns V SW = 1.5V Figure 11, Figure to ns R L = 50Ω, C L= 35pF V SW = 1.5V Figure 11, Figure (5) ns 2.7 to ns R L = 50Ω, C L = 35pF 1.8 (5) ns V SW = 1.5V Figure 11, Figure to ns R L = 50Ω, C L = 35pF V SW = 1.5V Figure 11, Figure 12 C L = 35 pf, R L = 50Ω Figure 11, Figure 13 R L = 50Ω, C L = 35pF V SW1 = V SW2 = 1.5V Figure 15 R L = 50Ω, C L = 35pF V SW1 = V SW2 = 1.5V Figure 15 C L = 50pF, R GEN = 0Ω, V GEN = 0V R L = 50Ω, f = 10MHz Figure 17 R L = 50Ω, f = 10MHz Figure (5) to ns ns 2.7 to ns 2.7 to ns 2.7 to pc 2.7 to db 2.7 to db BW -3db Bandwidth R L = 50Ω, C L = 5pF Figure to MHz Note: 5. Guaranteed by characterization. FSA2567 Rev

6 Capacitance Symbol Parameter Conditions T A =- 40ºC to +85ºC Min. Typ. Max. C IN Control Pin Input Capacitance V CC = 0V 1.5 (6) VCC = 3.3V, f = 1MHz C OND RST, CLK, DAT On Capacitance Figure 20 (6) VCC = 3.3V, f = 1MHz C ONV V SIM On Capacitance Figure 20 C OFFD C OFFV RST, CLK, DAT Off Capacitance V SIM Off Capacitance Note: 6. Guaranteed by characterization. V CC = 3.3V Figure 19 V CC = 3.3V Figure Units pf FSA2567 Rev

7 Typical Performance Characteristics RON (Ohms) C 25 C -40 C V IN, V CC =2.7V Figure 4. R ON Data Path Off Isolation (db) Crosstalk (db) Gain (db) RON (Ohms) Frequency Response 85 C 25 C -40 C V IN, V CC =2.7V Figure 5. R ON V SIM Frequency (MHz) V CC =2.7V Figure 6. Off Isolation Frequency Response Frequency (MHz) V CC =2.7V Figure 7. Crosstalk Frequency Response Frequency (MHz) C L = 5pF, V CC =2.7V Figure 8. Bandwidth FSA2567 Rev

8 Test Diagrams nv SIM,nRST, nclk, or ndat V SW V SW nv SIM, nrst, nclk,or ndat V ON R ON =V ON /I ON V SIM, RST, CLK, or DAT I ON V =0orV CC Figure 9. On Resistance V SIM, RST, CLK,or DAT C L R L R L and C L are functions of the application environment (see tables for specific values). C L includes test fixture and stray capacitance. V CC 90% NC I na(off) A V SW V =0orV CC Figure 10. Off Leakage t RISE = 2.5ns t FALL =2.5ns 90% 90% Input V V CC /2 V CC /2 10% 10% VOH 90% Output - V OL t ON t OFF Figure 11. AC Test Circuit Load Figure 12. Turn-On / Turn-Off Waveforms t RISE = 2.5ns t FALL = 2.5ns V CC 90% 90% Input - V SW 10% V OH V CC /2 V CC /2 10% Output - VOUT 50%50% V OL t plh t phl Figure 13. Propagation Delay nv SIM, nrst, nclk, or ndat V SIM, RST, CLK, or DAT V CC Logic Input Off On Off V SW C L R L 0V Δ Figure 14. Charge Injection Q = Δ C L FSA2567 Rev

9 Test Diagrams (Continued) V SEL V SW1 nv SIM, nrst, nclk or ndat V SW2 R L and C L are functions of the application environment (see tables for specific values). C L includes test fixture and stray capacitance. Figure 15. R S and R T are functions of the application environment (see tables for specific values). trise = 2.5ns V V CC SIM,RST, 90% CLK or DAT Input- V CC /2 V 10% 0V C L RL VOUT 0.9 Break-Before-Make Interval Timing Network Analyzer R S V IN R T V S V t BBM R T R S and R T are functions of the application environment (see tables for specific values). 0.9 Network Analyzer V IN R S R T V S Off isolation = 20 Log ( / V IN ) Figure 16. Bandwidth Figure 17. Channel Off Isolation NC Network Analyzer R S V V IN V S R T R S and R T are functions of the application environment (see tables for specific values). R T Crosstalk= 20 Log ( / V IN ) Figure 18. Non-Adjacent Channel-to-Channel Crosstalk Capacitance Meter nv SIM, nrst, nclk, or ndat f=1mhz nv SIM, nrst, nclk, or ndat V =0orV CC Capacitance Meter f=1mhz V SIM,RST, CLK, or DAT nv SIM, nrst, nclk, or ndat V =0or V CC Figure 19. Channel Off Capacitance Figure 20. Channel On Capacitance FSA2567 Rev

10 Physical Dimensions 2X 0.10 C 1.80 PIN #1 IDENT TOP VIEW 0.55 MAX C 0.08 C SIDE VIEW 5 9 A B C X 0.10 C SEATING PLANE X X RECOMMENDED LAND PATTERN TERMINAL SHAPE VARIANTS X 15X PIN 1 NON-PIN 1 Supplier ALL TERMINALS 0.10 C A B 0.05 C X 15X PIN 1 NON-PIN 1 Supplier 2 BOTTOM VIEW A. THIS PACKAGE IS NOT CURRENTLY REGISTERED WITH ANY STANDARDS COMMITTEE B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. TERMINAL SHAPE MAY VARY ACCORDING TO PACKAGE SUPPLIER, SEE TERMINAL SHAPE VARIANTS E. LAND PATTERN IS A MINIMAL TOE DESIGN F. DRAWING FILE NAME : UMLP16AREV3 Figure Lead Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: For current tape and reel specifications, visit Fairchild Semiconductor s online packaging area: FSA2567 Rev

11 Physical Dimensions Figure Terminal Molded Leadless Package (MLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings: FSA2567 Rev

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