Semiconductor Memories. Prof. MacDonald

Transcription

1 Semiconductor Memories Prof. MacDonald

2 Types of Memories! l Volatile Memories require power supply to retain information dynamic memories l use charge to store information and require refreshing static memories l use feedback (latch) to store information no refresh required l Non-Volatile Memories ROM (Mask) EEPROM FLASH NAND or NOR MRAM

3 Memory Hierarchy! 100pS 1nS 10nS 100nS 1us RF L1 SRAM L2 SRAM L3 DRAM 100 s of bytes Disks / Flash 10 s of Kbytes 100 s of Kbytes 100 s of Mbytes Gbytes

4 Memory Hierarchy! l Large memories are slow l Fast memories are small l Memory hierarchy gives us illusion of large memory space with speed of small memory. temporal locality spatial locality

5 Register Files! l Fastest and most robust memory array l Largest bit cell size l Basically an array of large latches l No sense amps bits provide full rail data out l Often multi-ported (i.e. 8 read ports, 2 write ports) l Often used with ALUs in the CPU as source/destination l Typically less than 10,000 bits bit fixed point registers bit floating point registers

6 SRAM! l Same process as logic so often combined on one die l Smaller bit cell than register file more dense but slower l Uses sense amp to detect small bit cell output l Fastest for reads and writes after register file l Large per bit area costs six transistors (single port), eight transistors (dual port) l L1 and L2 Cache on CPU is always SRAM l On-chip Buffers (Ethernet buffer, LCD buffer) l Typical sizes 16k by 32

7 Static Memory Cell! Wordline! T1! T3! True! Bit! Line! T5! T6! Complement! Bit! Line! T2! T4!

8 Example Chip! LCD Frame Buffer SRAM SRAM cache Register file

9 SRAM Interface!! l Dirt simple clk only required if registered inputs and/or outputs csn usually negatively active chip select wen usually negatively active write enable a address bus logarithmically related to number of locations d data in bus inputs used during writes q data out bus outputs used during reads l l read csn active / wen inactive data in the byte located by A bus launches out Q bus write csn active / wen active D bus value is loaded into memory location determined by A

10 SRAM Operation!!

11 Dual Port SRAM Operation!! l Two complete single port interfaces can read two locations simultaneously can write two different locations simultaneously can not write one location with two different ports Typically requires 2 additional transistors per bit l (6 to 8 for 33% increase) Typically requires 4 bit lines and 2 word lines l double the global routing than single port

12 Dual Port SRAM Interface!! l Two merged SRAM interfaces clk if registered inputs and/or outputs csna / csnb usually negatively active chip select wena / wenb usually negatively active write enable aa / ab address bus logarithmically related to number of locations da / db data in bus inputs used during writes qa / ab data out bus outputs used during reads

13 Two Port Memory Cell! Word Line! Port 0! True! Bit! Line! Port 0! T5! T1! T2! T6! Complement! Bit! Line! Port 0! True! Bit! Line! Port 1! T7! T8! T3! T4! Word! Line! Port 1! Complement! Bit! Line! Port 1!

14 Memory Compilers! l ASIC library providers give logic designers: Standard cells - ANDs, NANDs, FLIP-FLOPs, etc Chip IOs Memory compilers l single port SRAM, l dual port SRAM, and l register files. l Dial in size and generates verilog, layout, timing. l DRAM, FLASH not supported

15 Motherboard architecture

16 Dynamic RAM! l Most dense RAM (1 Gbit chips available) l Historically, different semiconductor process so built on a separate die l L3 Cache (old days) and computer main memory l Requires refresh of data due to leakage l New push to combine DRAM and logic embedded DRAM, edram business case hard to close yields drop

17 DRAM Bit Cells (1T) DRAM used since the early 70s Destructive Read Highest density bitline wordline Cbl Cb

18 DRAM Bit Cells (3T) DRAM used in the early 70s Non-destructive read write bitline read bitline write wordline read wordline

19 DRAM Cross Section

20 DRAM Array

21 DRAM Interface Evolution! l Asynch DRAM up until early 90 s l Synch DRAM add a clock l Double Data Rate (DDR) SDRAM l DDR2 SDRAM Faster l Others RAMBUS Intel supported dead except for PS3 graphics versions specifically for frame buffers Mobile SDRAM low power, good for palm pilots

22 DRAM Read Timings RAS CAS Addr RA1 CA1 RA CA Addr data 1 data 2

23 DRAM Read Timings (EDO) RAS CAS Addr RA1 CA1 CA Addr data 1 data 2

24 SDRAM l Same array as Asynch DRAM l Add pipelining to data to increase bandwidth l Requires new clock signal l Treats RAS, CAS, WE as command inputs l Replaced by DDR for high performance apps l Still alive for mobile applications due to power

25 SDRAM Block

26 SDRAM Commands

27 Maskable ROM! l Most dense ROM l Tie bit high or low at mask level (metallization) l Mistakes take weeks to fix with new silicon hold lots at metal layer for quick implementation

28 SDRAM Timings command is just the value of CSN, CAS, RAS and WEN together in that cycle address is usually 9-11 bits plus 2 bits for bank address

29 ROM/EEPROM/FLASH! l Metal Mask ROM l Electrically erasable programmable ROM l FLASH is block erasable only EEPROM l EEPROM can be byte-written but requires extra transistor l FLASH may take over the world replacing disk drives with FLASH drives (no moving parts more reliable). l Motorola is leader in combining FLASH with logic l Intel leader in NOR Flash l Toshiba / Samsung leaders in NAND Flash

30 EPROM! l Erasable Programmable ROM l Can be erased by UV light l Programmed by Hot Carrier Injection l Obsolete but still mentioned only used in EE2369 to provide historical perspective

31 NOR ROM Structure!

32 NOR ROM Structure!

33 NAND ROM Structure!

34 Flash Cross Section!

35 FLASH!

36 FLASH! l NOR Flash less dense (256 Mbit) but provides fast random read access Erase FN / Program HEI 100,000 write cycles Slow erase, fast program and read SRAM like interface give an address get a byte of data great for code memory ( bios, boot-up, cell phone, etc) l NAND Flash More than 2X denser up to 2Gbit Erase FN/ Program FN Fast erase, slow program and read 1,000,000 write cycles IO like interface not as simple as NOR good for data storage memory cards, IPODs, USB keydrives

37 Flash Cross Section!

38 NOR FLASH!

39 NAND Flash Reading!

40 Tunneling vs Injection!

41 Charge Pumps! l Flash and EEPROM architectures need unavailable higher voltage for programming (+10v) l Charge pumps can pump a cap to get high voltage l DC to DC (higher) converter - without inductors l Need to consider Vmax across any gate oxide l Generally cannot provide much power (I*V) l Charge pumps used for a lot of other things like overdrive voltages and PLLs

42 Basic charge pump concept!

43 Staged Diode Charge Pump!

44 Dickson Charge Pump! V 1 V 2 V 3 V 4 V in V out M d1 M d2 M d3 M d4 M d15 C C C C C out φ φ

45 Improved versions! V 1 V 2 V 3 V 4 M D1 M D2 M D3 M D4 M Do V in V out M s1 M s2 M s3 M s4 M D5 C C f M N1 M N2 M N3 M N4 M P 1 C M P 2 M P 3 M P 4 C C C _ 1 _ 2 Stage 1 Stage 2 V DD N1 N2 N3 N4 P1 P3 P7 C out P2 P4 P8 C1 C3 _ 1 _ 2 C2 C4

46 Clock booster! N 2b N 2 C 1b P 2 P 1 Out b N 1b C 1 N 1 Out V o V ob

47 4 Phase Charge Pump! Clk 2 Clk 4 C b1 C b2 M 2 M 4 V in V out M 0 M 1 M 3 M n C 1 C 2 C 3 Clk 1 Clk 3 Clk 1

48 CAMs! l SRAM structure that will do a parallel compare against the contents to provide a hit signal for each row (value) l Used by caches to find if data is in cache l Also used for translation look-aside buffers l Also used in switches / routers to check destination address in ethernet against list of addresses l Ternary CAMs allow for bit masking the compare

49 Encoders / Decoders 3 to 8 line decode Encoder Decoder input

50 Read Only Memories - ROM Address Data Out n ROM m 2 n addresses addressed by n bit m output data bits

51 Read Only Memories - ROM n n to 2 n decoder 2 n Memory array Address input word lines m data output

52 ROM memory array weak pull down word line 2 N -1 pd pd pd pd pd pd word line 2 N -2 word line 2 word line 1 word line 0 programmed one programmed zero data m-1 data m-2 data 2 data1 data0 bit lines

53 Random Access Memory (RAM) bitline bitlinen wordline 6 Transistor SRAM cell word lines Address input n+c n n to 2 n decoder 2 n sram array of 6-t cells rnw c data in peripheral circuits column mux, sense amps, write circuitry m data out m

54 SRAM Organization!! l Blocks with unity aspect ratio l Rows l Columns l IO

55 Static Memory Cell! Wordline! T1! T3! True! Bit! Line! T5! T6! Complement! Bit! Line! T2! T4!

56 4D - Static Memory Cell! Wordline! True! Bit! Line! T! C! Complement! Bit! Line! Cell!

57 SRAM Read Cross-Section! DRAMs precharge! to half Vdd so PFET enable required as well! Set! Sense! Amp! Isolation Circuit! Precharge! Circuit! Bit! Line! Isolation! TSA! CSA! Bit! Line! Precharge! TBL! T! CBL! Wordline! Cell!

58 SRAM Isolation & Pre-charge Circuits! Sense Amp! Bit Switch Circuit! Bit! Line! Isolation! Pre-charge! Circuit! Bit! Line! Pre-charge! Cells!

59 SRAM Sense Amplifier Circuit! DRAMs precharge! to half Vdd so PFET enable required as well! TSA! CSA! Set! Sense! Amp! Bit Switch!

60 SRAM Internal Memory Waveforms! Clock! Word line!!!! Isolation!! Set Sense Amp!!!! Sense Amp Output!!! Data!

61 SRAM Write Head Circuit! Bit Line! True! Bit Line! Complement! Write! Enable! Data!

62 SRAM Decode Circuit! WL0! WL1! WL2! WL3! Clock! W0C! W0T! W0C! W0T! W1C! W1T!

63 SRAM Cell with Center GND Contact Vdd PFET diffusion Ground NFET diffusion Word line (Polysilicon) Bit line contacts

64 SRAM Cell with Shared Vdd Contact PFET diffusion Vdd Ground NFET diffusion Bit line contacts Word line (Polysilicon)

65 Split Word Line SRAM Cell Bit line contact Word line (Polysilicon) PFET diffusion NFET diffusion Ground Vdd Bit line contact

66 Bit Cell Analysis Read Disturb! Wordline! T1! T3! precharged to 1.8v True! Bit! Line! T5! T6! Complement! Bit! Line! T2! T4! starts at 0v but will jump up. If it jumps too high, can flip the bit. T6 is often not min L to keep the jump low.

67 Bit Cell Analysis Read Disturb! If low, right data node (Vrd) cannot exceed the threshold of T2 or bit may flip. (Kn6 / 2) (Vdd Vrd Vtn) 2 = (Kn5 / 2) ( 2 ( Vdd Vtn)*Vrd Vrd 2 ) Kn6/Kn5 < (2(Vdd 1.5 Vtn) Vtn) / (Vdd 2*Vtn) 2

68 Bit Cell Analysis - Write! l Must ensure that write head circuit can over power cell by the end of the write cycle. l The side of the bit cell with a 0 dominates the write transaction as the pass transistor is an NFET. l When the word line asserts the write head circuit drives a zero on one of the two sides. l The bit data in the cell must be brought below the threshold of the cross-coupled inverter to flip the bit.

69 Bit Cell Analysis Soft Error! l Radiation (particularly in space but occasionally on Earth) causes the generation of charge in circuits. l SOI technology helps as it shields transistors from charge in the bulk silicon. l The bit cell node has a capacitance and introduced charge will change the voltage at the node. l If the voltage swing exceeds the threshold of the crosscoupled inverter, the bit will flip (i.e. soft error) l Qcrit is charge required to flip bit. l Data is bad, but the bit cell still works (thus soft error).

70 Bit Cell Analysis Soft Error! Wordline! T1! T3! True! Bit! Line! T5! T6! Complement! Bit! Line! T2! T4! constant current source turned on for time t Qcrit = I * t

71 Redundancy and Repair! l DRAM and SRAMs often have extra rows, columns, IOs and / or Blocks to replace those that are bad. l Two dimensional redundancy (i.e. rows and columns) provides good coverage with minimized. l Rule of thumb (which changes over time) is currently that 2 Mbit memories and above will benefit in terms of yield if redundancy is included.

72 Redundancy and Repair!

73 Built-In Self Test! l Many register files and embedded SRAMs in ASICs now come with wrapper logic that will test the memory. l The BIST includes muxes that all the test logic access to the ports of the memory. l A BIST state machine generates address and data and writes to the ram, followed by reads and compares of the data. l Some BIST also implement redundancy if necessary This is often referred to as Built-In Self Repair.