Developments towards high-density silicon photonics integrated circuits in Japan

Transcription

1 ECOC2012 Workshop WS07 Low-Cost Open Access to Photonic Integration Technology 4 th European Photonic Integration Forum Developments towards high-density silicon photonics integrated circuits in Japan T. Nakamura a,b, Y. Urino a,b, T. Horikawa a,c and Y. Arakawa a,d a: Institute for Photonics-Electronics Convergence System Technology (PECST) b: Photonics Electronics Technology Research Association (PETRA) c: National Institute of Advanced Industrial Science and Technology (AIST) d: Institute of Industrial Science, The University of Tokyo

2 Outline Background: Concept of P-E Convergence System Silicon Photonics Technology - Waveguide - Silicon Optical Modulator - Germanium Photodetector - Light Source Assembly - Integration 300mm Foundry Shuttle Service by AIST Summary *AIST : National Institute of Advanced Industrial Science and Technology 2

3 Concept of Photonics-Electronics Convergence System for inter-chip interconnects Photonics-Electronics Convergence System LSIs (Bare chips) Laser diode Si LSI substrate LSI LSI Electronic wires Optical modulators Photo detectors Optical waveguides LSI modules Printed circuit board (PCB) ~3cm Small size Wide bandwidth High density Low cost 3

4 Bandwidth (Gbps) Trend of optical interconnects Transmission density Our target AOC etc. Luxtera LightWire PODAvago PETIT2(NEC 10) Luxtera Inter-Rack Inter-Board Inter-chip Silicon photonics LAN WAN PETIT(NEC 08) 10 Light Peak(Intel 10) 1 300pin-MSA (10Gx1) 0.01 XFP (10Gx1) POP4( 05) QSFP( 08) SNAP12(IBM 04) / Transceiver Footprint (cm -2 ) 4

5 Features of CMOS Lines in AIST at Tsukuba Research Line Integration Line Wafer diameter 100mm 300mm Process Modules Frontend process module for SOI-CMOS (including Ge-ch. FET) Frontend and backend process modules (45nm node technology) VSB-EB Immersion ArF resolution 30nm (Iso. line) resolution 45nm (Iso. line) Lithography overlay 30nm 70nm (hole) Silicon Photonics Technologies Silicon Photonics stich 30nm (main field) overlay 6.5nm Development Foundry Shuttle Service I-line Dry ArF, KrF by PETRA & AIST by AIST Gate Stack Metal gate/ high-k Metal gate/ high-k Salicide NiSi NiSi Interlayer Dielectric Wiring SiO 2 Low-k (k~3.0, 2.4) 2 layers, Al 4-6 layers, Cu (dual damascene) 5

6 An example of fabrication flow for photonic integrated circuits on SOI wafers Core pattern formation (Waveguide, MMI, MZI) Specified processes for modulator and detector (i.e. Ge epitaxy, impurity doping, electrode formation) Clad for waveguide Contact through clad Waveguide Wiring Clad for SSC Modulator Detector Mount stage formation for LD array LD assembly 6

7 Waveguide loss (db/cm) Si-wire and a-si:h waveguide Si-wire waveguide : Low-loss of 1~2 db/cm Wide range operation in 2 2 MMI coupler of over 150nm a-si:h waveguide : Record low-loss of 1.2 db/cm Height : 220nm l = 1550nm TE mode a-si:h waveguide 440nm Propagation loss ; 1.2dB/cm 210nm Waveguide width (nm) Si-wire waveguide loss a-si:h waveguide loss 2 2 MMI Coupler K. Furuya, et al., Appl. Phys. Lett., 100, (2012). P1 P2 IN OUT PA PB 7

8 Modulator with Side-Wall Grating Transmission (db) Silicon waveguide Aluminum electrode Input Port 1 Port 2 Phase Shifter SiO 2 W 0-10 Transmission spectrum Stop band Operating window -20 Al n nm Si 460 nm p + BOX n - : 1~ cm -3 p - : ~ cm Port 1 Port 2 Port 1 + Port Wavelength (nm) S. Akiyama et. al, Group Ⅳ Photonics 2012, ThC2 8

9 50-Gb/s Large-Signal Operation Driving configuration +0.5 V Pre-emphasis-electrical signal Port V pp +0.5 V L = 250 mm PIN-diode Port ps/div. Optical waveform Port 1 Port 2 ER = 4.3 db 5 ps/div. ER = 4.1 db 5 ps/div. ER: dynamic extinction ratio Clear 50-Gb/s eye openings using 250-mm phase shifter S. Akiyama et. al, Group Ⅳ Photonics 2012, ThC2 9

10 Two Types of Ge Photodetectors MSM Ge photodetector PIN Ge photodetector MSM : Metal-Semiconductor-Metal metal metal n + -Ge metal Feature Selectively-grown Ge Si waveguide Process simplicity Flexibility in metal layout ->Applicable to various kinds of optoelectronic circuits. Technical issues Suppression of large dark current p-si Feature Selectively-grown Ge Si waveguide High-speed characteristics ->Beneficial to systems with wide bandwidth. Technical issues Reduction of contact resistance on Ge M. Miura et. al, INC8, Japan Nano Day, #112 10

11 Current (A) MSM Ge Photodetectors Low dark current (0.4 na/μm 2 ), 64% of quantum efficiency, and 20Gbps eye opening were achieved by optimization of Si cap growth condition on Ge. TEM image of MSM Photodetector I-V Characteristics λ:1550nm 0.4mW Photo Current Output Waveforms at 20 Gbps 20 Gbps A/W Dark Current 100 mv 20 ps PD Size: 5x30 μm Applied voltage (V) M. Miura et. al, INC8, Japan Nano Day, #112 11

12 PIN Ge Photodetectors Reduction of resistance in PIN Ge photodetector by optimization of P concentration at NiGe/Ge junction -> Bandwidth higher than 50GHz is estimated -> 40Gbps eye opening was achieved (will be presented in SSDM 2012 by J. Fujikata) Series resistances in pin photodetector Total resistance of photodetector Calculated bandwidth M. Miura et. al, INC8, Japan Nano Day, #112 12

13 Newly Proposed SSC for Hybrid Integrated Light Source Hybrid integration Single laser diode array is mounted on a silicon waveguide platform Newly Proposed Trident SSC Simple Fabrication Process Large Manufacturing Tolerance N. Hatori et. al, Group Ⅳ Photonics 2012, ThB2 13

14 Coupling loss (db) Coupling loss (db) Coupling Characteristics & Manufacturing Tolerance Inversed taper SSC ±0.9µm (horizontal) ±0.85µm (vertical) Measured Horizontal Vertical LD Deviation (µm) Trident SSC Tip width w (nm) Zero deviation Coupling loss : 2.3dB 1dB- coupling tolerance Horizontal : ±0.9µm Vertical : ±0.85µm The proposed trident SSC structure is superior to the conventional one in terms of manufacturing tolerance. N. Hatori et. al, Group Ⅳ Photonics 2012, ThB2 14

15 Over 100ch. Light Output Ports by Multi-port & Multi-LD Chip Bonding 500µm Array LD1 Array LD2 Si-bench Solder bump SSC Silicon waveguide 1ch 53ch 52ch All 104 (13ch. x 4 x 2LDs) ports output was demonstrated. 104ch The light source over 100 output ports corresponding to 1Tbit/s transmitter, assuming 10 Gbit/s for each port. T. Shimizu et. al, IPR2012, ITu4B.5 N. Hatori et. al, Group Ⅳ Photonics 2012, ThB2 15

16 Integration Tuesday, 18 September Tu :00~16:15 Demonstration of 12.5-Gbps Optical Interconnects Integrated with Lasers, Optical Splitters, Optical Modulators and Photodetectors on a Single Silicon Substrate will be presented by Yutaka Urino (PETRA/PECST) 16

17 AIST Launching 300mm Foundry Shuttle Services in Japan AIST announced the Silicon Photonics Shuttle Service launch in May INC8. Competency Building Block is 45nm CMOS process featuring Immersion ArF Lithography. Core Competency Building Blocks, AIST SCR SCR holds cutting edge facility, knowledge and partnership in JPN. Lithography Roadmap against the CD Control NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (AIST) AIST Confidential 17

18 Acknowledgements This research is supported by JSPS through its FIRST Program. This work was conducted at the TIA Super Clean Room operated by Innovation Center for Advanced Nanodevices (ICAN), National Institute of Advanced Industrial Science and Technology (AIST), Japan. A part of the fabrication was conducted at the Nano- Processing Facility, supported by IBEC Innovation Platform in AIST. Thank you for your attention. 18