Silicon photonics for high performance optical communications

Transcription

1 Silicon Photonics Silicon-based micro and nanophotonic devices Silicon photonics for high performance optical communications G. Rasigade, L. Virot*, M. Ziebell, P. Chaisakul, M-S. Rouifed, P. Crozat, P. Damas, E. Cassan, L. Vivien, Institut d Electronique Fondamentale, Université Paris Sud J-M. Fédéli, S. Olivier, J-M. Hartmann CEA-LETI, Minatec G. Isella, D. Chrastina, J. Frigerio L-NESS, Politecnico di Milano, C. Baudot, F. Boeuf STMicroelectronics Crolles * Also at STMicroelectronics and CEA-Leti

2 Outline 1. Silicon photonics : motivation 2. Optoelectronic devices on silicon photonics: Photodetection Optical modulation Optical laser source 3. Electronic-photonic convergence 4. Conclusion 2/61

3 Explosion of data trafic Source : Intel 3/61

4 Explosion of data trafic VIDEO!! Source : Cisco Transmission capacity of several times 100 Tbps per fibre predicted in backbone network, in year 2020 (source : Photonics 21 roadmap) 4/61

5 Data center Source : Google Copper cables Optical communications 10 Gbit/s a few meters-long communication Gbit/s A few hundreds of km-long communications 5/61

6 Data center Today s data center consumes a lot of energy Facebook Google Major challenge : high data rate optical interconnect with low power consumption and low cost. 6/61

7 Data centers Optical telecommunications Environment Interconnects Silicon photonics Chemical/Biological sensors Free space communications FTTH 7/61 Military

8 Microelectronic circuits Roadmap ITRS 8/61

9 Microelectronic circuits Increase of integrated circuit performances Increase of the number of transistors Reduction of transistor s dimensions Source: ITRS Increase of the length and density of metallic interconnects Metallic interconnect limitations RC delay Signal distortion Power consumption Limitation of the clock frequency increase 9/61

10 Microelectronic circuits Performance = Parallelism x Frequency 80 Cores 48 Cores Intel Use photonics at the chip scale (intra-chip or inter-chip) to: Increase the data transmission (-> Tbit/s per link thanks to WDM, multi-level modulation formats) Reduce the power consumption 10/61

11 Towards at the end Laser Photonics Beam splitter + CMOS Analog & Digital Circuits modulator detector = Photonic / electronic integrated circuits Silicon photonics Source: Luxtera 11/61

12 Optics vs microelectronics Microelectronics Building blocks Transistor Material Silicon Dimensions Manufacturing technology <µm CMOS 12/61

13 Optics vs microelectronics Microelectronics Silicon Photonics Building blocks Transistor Laser, waveguides, photodetectors, modulator, microresonators, Material Silicon Silicon-based III-V? Other? Dimensions Tens to hundreds of nms fews µms -> mms Manufacturing technology CMOS CMOS compatible process 13/61

14 Silicon for optics: Pro s and Cons Transparent in µm region Take advantage of CMOS platform Mature technology High production volume Low cost Silicon On Insulator (SOI) wafer Natural optical waveguide High-index contrast (n Si =3.5 n SiO2 =1.5) Strong light confinement Small footprint (450nm x 220nm) Indirect bandgap material No or weak electro-optic effect Lacks efficient light emission No Si laser No detection in µm region SiO 2 Si SiO 2 Si 14/61

15 Passive silicon photonic integrated circuits SOI microwaveguides: the basic device Strip waveguides Si SiO 2 SiO 2 Mode size 0.1µm 2 Propagation loss 1dB/cm Si SOI wafer = Optical planar waveguide Rib waveguides 100 nm 420 nm 290 nm 15/61 Mode size 0.2µm 2 Propagation loss 0.5dB/cm =1.55µm

16 Passive photonic devices Waveguides WDM 8 µm 14 µm 90 -turns Beam splitter Fiber coupler 16/61

17 Optical communication link using silicon photonics Goal : silicon photonics for : Intra-chip communications Inter-chip communications Data-com communications 17/61

19 Photodetection: basic principle Light absorption Carrier collection hn h + e - h + e /61

20 Photodetector specifications Compatibility with silicon technology Large wafer scale technology Low cost integration schemes Compact devices high absorption coefficient efficient carrier collection Low dark current quality of the layer electrical configuration High bandwidth > 10 GHz carrier transit time RC constant 20/61

21 Germanium on silicon: Pros and Cons Germanium Absorption coefficient of pure Ge: 9000 cm -1 at =1.3µm L 95% ABS 3.3µm (!) Low capacitance devices High frequency operation Lattice misfit with Si of about 4.2% specific growth strategies required (wafer-scale and localized) High carrier mobility 21/61

22 Ge growth strategies Thick virtual SiGe substrates (10µm) Too thick for a good integration with classical optical Si waveguide Growth on thin SiGe buffers The thickness of the thin SiGe buffer is around 1µm Always too thick Low/high temperature process 22/61

23 Germanium growth Two-step growth process: Direct growth of Ge on Si using a low temperature ( 350 ) CVD process thin (a few 10nm) highly-dislocated Ge Optical layer absorption Close to bulk values Bandgap shrinkage (50 nm) Growth of a thick Ge layer (a few 100nm) at a higher temperature ( 600 ) high quality Ge absorbing layer Tensile strain Absorption up to 1.6 µm Thermal annealing to reduce the dislocation density HT Ge ( 600 C, nm) LT Ge ( 350 C, 50nm) Si substrate (001) 23/61 UHV-CVD (IEF) RP-CVD (LETI)

24 Ge photodetector Lateral Ge photodiode buttcoupled with SOI waveguide RF electrodes Input waveguide 10 µm 24/61

25 Experimental set-ups 25/61

26 Results : Bandwidth measurement Opto-electric frequency response measurement using 50GHz Lightwave Component Analyzer (@1550nm) W i = 0.5 µm -3dB Optical Bandwidth Over 0V Responsivity : 0.5 A/W 26/61

27 Data transmission Under zero-bias 10 Gbit/s Results beyond specifications Coll.: 20 Gbit/s 40 -1V High responsivity: > 0.5A/W High bandwidth: 40Gbit/s Low dark current: -1V 30 Bias Gbit/s voltage: 0V 40 Gbit/s 27/61

29 Optical modulation in silicon I 0 Optical intensity t Electrical driver Optical modulator t I max I min Modulated optical intensity t Figures of merit ER IL f c Extinction ratio Insertion loss -3dB bandwidth Voltage swing Power consumption 29/61

30 Optical modulation in silicon I 0 Optical intensity t Electrical driver Optical modulator t I max I min Modulated optical intensity Tapez une équation ici. t E 0 e L/2 e j2pnl/ E 0 Intensity modulation Phase modulation 30/61

31 Optical modulation in silicon I 0 Optical intensity t Electrical driver Optical modulator t I max I min Modulated optical intensity t Electroabsorption Absorption coefficient variation with electric field Intensity modulation Electrorefraction Refractive index variation with electric field In silicon : index variation by free carrier concentration variation Interferometric structure to convert phase modulation into intensity modulation 31/61

32 Optical modulation in silicon Mach Zehnder based modulator: No temperature and wavelength sensitivity L p = /2Dn eff Ring based modulator: Compact 32/61

33 Silicon optical modulator Metal PIPIN diode Metal P-doped region N-doped region Europe: Univ. Paris Sud, CEA Leti, Univ. of Southampton Asia: A*Star, Petra, AIST, Chinese Academy of Sciences, Samsung Electronics, Tokyo Institute of Technology North America: Intel, IBM, Cornell, Luxtera, Ligthwire, Kotura, Oracle 33/61

34 Silicon modulator design Example : carrier depletion in interleaved pn diode Free carrier concentration variations when a reverse voltage is applied on the diodes N Light propagation P Efficiency / rapidity / loss compromise 34/61

35 Silicon modulators in 300 mm platform 200mm wafer 300mm wafer 35/61 High volume Sub-65nm CMOS node 193nm immersion photolithography Sub-50nm resolution Wafer thickness uniformity < ±5nm on 300-mm ~ ±10nm on 200-mm

36 300 mm-based Si modulators Geometry: 0,95mm long Mach-Zehnder modulator Taux d extinction : 8 db Pertes = 4 db 40 Gbit/s D. Marris-Morini et al, Opt. Exp. (2013) 36/61

37 Silicon modulators Short distance and high volume applications (electrical bottleneck) Main challenges: Driving voltage of modulator Power consumption Optical interconnects Data-center ITRS Roadmap : Optical interconnect : ( ) A large variety of CMOS compatible modulators have been proposed in the literature ( ) The primary challenges for optical interconnects at the present time are producing cost effective, low power components. 37/61

38 Puissance consommée Mach Zehnder 3 pj/bit Spécifications concernant l énergie des émetteurs : pour les liaisons à courtes distances : ~100 fj/bit à quelques fj/bit (D.A.B. Miller, Opt Exp., 2012) Résonateur en anneau 0.5 to 1 pj/bit électroabsorption? 38/61

39 Electroabsorption in Group IV materials Germanium : indirect gap material with direct gap properties, at telecommunication wavelengths. 39/61

40 Germanium for silicon photonics Bulk Ge Photodetectors on SOI Laser sources based on doped, strained Ge Electroabsorption by Franz-Keldysh effect Ge/SiGe quantum well Electroabsorption by Quantum Confined Stark Effect (QCSE) 40/61

41 Electroabsorption in QW structures Quantum confined Stark effect (QCSE) E=0 E 0 Excitonic peak reduction and red-shift absorption spectra with electrical field 41/61

42 Optoelectronic properties of Ge/SiGe QW QCSE : polarization dependance QCSE at 1.3 µm P. Chaisakul et al, Optics letters (2011), APL (2013) M-S. Rouifed, et al Optics Letters (2012) Study of the dynamics Electroluminescenc e Electro-refraction by QCSE P. Chaisakul et al, APL (2011) P. Chaisakul et al, APL (2011) J. Frigerio et al, APL (2013) 42/61

43 Ge/SiGe electroabsorption modulator Ge QW P. Chaisakul et al, Opt. Express (2013) Power consumption: 70 fj/bit Extinction ratio > 6 db on 20 nm spectral range Electro-optical bandwidth > 20 GHz 43/61 Remind : Mach Zehnder 3 pj/bit Anneau pj/bit

44 Photonics integrated circuits based on Ge/SiGe QW? Si 0.1 Ge 0.9 dopé N Si 0.1 Ge 0.9 QWs 2 µm Si 0.1 Ge 0.9 buffer relaxé Si 0.1 Ge 0.9 Si 0.15 Ge 0.85 Ge 15 nm 10 nm Si 0.15 Ge nm Si 0.1 Ge 0.9 dopé P 2 µm Si 0.1 Ge 0.9 buffer relaxé 13 µm buffer graduel de Si jusque Si 0.1 Ge µm buffer graduel de Si jusque Si 0.1 Ge 0.9 Si Schematic description Si More realistic scale Challenge : coupling the light from silicon to Ge/SiGe QW 44/61

45 Integration on bulk silicon 1 st option: waveguide in the relaxed SiGe layer (thanks to the graded buffer ) Si 0.09 Ge 0.91 dopé N Si 0.09 Ge 0.91 QWs Si 0.09 Ge 0.91 Si 0.15 Ge 0.85 Ge 15 nm 10 nm Si 0.15 Ge nm Si 0.09 Ge 0.91 dopé P 1.5 µm Si 0.16 Ge 0.84 buffer relaxé Ge concentration in the waveguide : compromise between Strain compensation Optical loss 8 µm buffer graduel de Si jusque Si 0.17 Ge 0.83 Si P. Chaisakul et al, soumis Optical loss of each device, including input/output coupling with Si 0.16 Ge 0.84 waveguide < 5dB 45/61

46 Integration on SOI 2 nd option : decrease the thickness of the buffer layer Challenge : keeping homogeneous and high qulity layers Buffer homogène Si 0.1 Ge 0.9 Si SiO 2 Buffer graduel de Si jusque Si 0.1 Ge 0.9 Si Ge/SiGe modulator integrated with SOI : estimated performance : Extinction ratio = 7.7 db, loss = 4 db M-S. Rouifed et al, soumis Under fabrication 46/61

48 Laser on silicon courtesy: Blas Garrido 48/61

51 Laser on silicon courtesy: Blas Garrido 51/61 INL, CEA, IMEC,3-5 lab

53 Germanium laser Indirect to direct bandgap SC The first Ge laser ; J. Liu, X. Sun, L.C. Kimerling, J. Michel : Presentation at Group IV photonics San Francisco (September 2009). 53/61

54 Electrically pumped Gemanium laser Rodolfo E. Camacho-Aguilera, et al. Opt. Express 20, (2012) 54/61

56 Laser on silicon INL, CEA, IMEC J. Van Campenhout, et al, Optics express /61

57 Photonics-electronics integration Photonics Photonics Transistors Photonics Transistors Transistors Front-end fabrication Very low parasitics Custom SOI, specific libraries process co-integration Back-end fabrication On top of CMOS or in metal layers Serial process Compound yield Thermal budget < 400C 57/61 3D integration Separate processes No change in CMOS Front-End No thermal budget! Other layers: MEMS, antennas Higher (but reasonable) parasitics

58 Overview of Industry involved in silicon photonics Si photonics activity (2012) OpSIS foundry services uses BAE & IME foundries JePPIX foundry uses Oclaro & FhG HHI foundries (InP) epixfab uses IMEC & LETI foundries Product manufacturing (> 100,000 chips) Product manufacturing (< 100,000 chips) R&D/ development stage Courtesy: 2012 Yole report R&D/MPW Fabless Foundries Business model Devices Systems 58/61

59 Perspectives Photonics / electronics integrated circuits Source : IBM 59/61

60 To go further Paris Aout 2014 Edition: April /61

61 Acknowledgements: Funding and collaborations National Research Agency SILVER, MICROS, GOSPEL, MASSTOR, ULTIMATE, Ca-Re-Lase, POSISLOT HELIOS Photonics Electronics functional integration on CMOS Silicon photonics group Plat4M photonic libraries and technology for manufacturing SASER Safe and Secure European Routing 61/61