Configuration of Plastic Packages PACKAGING. Package Configuration. Package Codes. Package Characteristics
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1 Configuration of Plastic s PACKAGING Configuration s Characteristics
2 Page 2 of 7 Configuration Micro SMD Characteristics Epoxy Coating Thick Small/large bump BP BL only Thin Small/large bump TP TL Ultra thin Small bump UL UP Plastic Small Outline Transistor SOT23/3Ld SOT23/5Ld SOT23/6Ld M3 M5 M6 MF SOT223/4Ld SOT223 SOT223/5Ld MP Plastic configuration Rev.: September 2004
3 Page 3 of 7 Configuration Leadless Leadframe (LLP) Characteristics Solder Plate Contact Plating Low Thermal Resistance Reduced Board Area Pullback LLP LD LQ SnPb- and Pb-free devices available No Pullback LLP Laminated Chip Scale (CSP) Regular Thin Ultra thin SD SN SP SQ SR SU SLB SLD SLE SL SnPb- and Pb-free devices available JEDEC Reg. No. MO-208 Board area reduction up to 50% compared to standard SOIC or TSSOP Thermal resistance enhancement accomplished by thermal vias and thermal pads Pb-free by design SC-70 M7 MG SC-70/5Ld SC-70/6Ld Plastic configuration Rev.: September 2004
4 Page 4 of 7 Configuration MINI-SOIC 8 Leads 10 Leads MM Characteristics Plastic Small Outline (SOIC) Narrow Body Wide Body M MA MW WM EIAJ and JEDEC Styles Small Outline (SOIC) Plastic Shrink Small Outline (SSOP) SSOP SSOP-EIAJ Plastic Thin Shrink Small Outline s (TSSOP) Molded Dual-In-Line (MDIP) MS MSA MQA MEA MQ ME MXA MXF TM MTC MTD MTE MT MH N NA EIAJ and JEDEC Styles Small Outline (SOIC) EIAJ Styles Through Hole Solder Plate or Solder Dip Lead Finish Sidebrazed Dual-In-Line (SB and Cerdip) Plastic configuration Rev.: September 2004
5 Page 5 of 7 Configuration Thin Quad Flat Pack (TQFP) (t = 1.0 mm) Low Profile Quad Flat Pack (LQFP) (t = 1.4 mm) Plastic Quad Flat Pack (PQFP) (t > 1.4 mm) V(X,X) VE VJ VQ VS VT VU V(X,X) VB VE VH VJ VN VP VT VV VY V(X,X) VC VD VE VF VG VH VJ VK VL VM VO VQ VU Characteristics Reduced Height High Density Application Reduced Height Thermally enhanced with Heat Spreader High Density Application High Density Application Plastic configuration Rev.: September 2004
6 Page 6 of 7 Configuration Plastic Leaded Chip Carrier (PLCC) V VA Characteristics J-Bend Lead Configuration Quad J-Bend (CQJB) Fine Pitch Ball Grid Array (FBGA) SLC SM JEDEC Reg. No. 205 Epoxy Coating Pb-free devices on request Low Profile Ball Grid Array (LBGA) UF Reduced Height Epoxy Coating Pb-free devices on request Plastic Ball Grid Array (PBGA) U(X,X) UC SnPb Solder Balls Plastic configuration Rev.: September 2004
7 Page 7 of 7 Configuration Characteristics TO s Through Hole and Surface Mount Designed with Heat Sink for High Power Applications (TO-220) TO-92 TO-220 TO92: Z ZA TO-220: T TA TO-263 TO-252 TO-263: S TS TO-252: DT TD Plastic configuration Rev.: September 2004
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PARA LIGHT ELECTRONICS CO., LTD. 4F, No.1, Lane 93, Chien Yi Road, Chung Ho City, Taipei, Taiwan, R.O.C. Tel: 886-2-2225-3733 Fax: 886-2-2225-4800 E-mail: para@para.com.tw http://www.para.com.tw DATA SHEET
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CHS2411-QDG Description GaAs Monolithic Microwave IC in SMD leadless package The CHS2411-QDG (CHS2412-QDG, see Note) is a monolithic reflective SP4T switch in K-Band. Positive supply voltage only is required.
Power Dissipation Considerations in High Precision Vishay Sfernice Thin Film Chips Resistors and Arrays (P, PRA etc.) (High Temperature Applications)
VISHAY SFERNICE Resistive Products Application Note ABSTRACT On our thin film chips resistors and arrays the main path for the heat, more than 90 %, is conduction through the body of the component, the
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