Self Qualification Results
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1 (ATO) Divisional Philips Semiconductors Philips Internal Report No.: RNR /RdH/RdH QTS Report Database No.: Self Qualification Results NiPdAu lead- free solution of SO14/16/20 Products for General Purpose Logic, Specialty Logic and Digital Datacom assembled in Philips Semiconductors Thailand (PST) A u t h o r : Rob de Heus Tel: Sr. Project Leader Advanced Development Tel: ATO Innovation Fax: Philips Semiconductors Nijmegen E- mail: rob.de.heus@philips.com Building BY G erstweg 2, 6534 AE Nijmegen, the Netherlands Issue Date: O c t o b e r 7 t h, , u p d a t e N o v e m b e r 3 r d
2 Table of Contents 1. Introduction Assembly Facility Materials selection background N i P d A u p r e -p lated leadframes Constructional Details of Test vehicles Reliability Test Program Reliability Test Descriptions Construction Analysis Tests Descriptions Summary of Solder Joint Reliability Tests for leadfree, leadframe based packages Variants included in the Investigation C o n c l u s i o n s Remarks Self-qualfication results NiPdAu packages Conclusion Implementation Document Revision Sheet D a t e : 0 3 N o v e m b e r A u t h o r : Rob de Heus Page: 2 Revision: 02
3 1. Introduction The intention of the change to Pb- free packages from Philips has been announced in the Advanced CP C N f o r P b - free, issued in May 2003, CPCN # The final CPCN will be issued in 5 different phases, each phase showing qualification results of a certain group of packages. This self qualification report presents an overview of the qualification data completed to release the first group of packages to be assembled in NiPdAu. This report covers the results of SO14/16/20 packages ( in small die- pads for General Purpose Logic, Specialty Logic and Digital Datacom products) assembled in NiPdAu in assy factory PST (Philips Semiconductors Thailand). The updated qualification plans for the other packages can be found in the updated Self Qualification plan, document number RNR /RdH/RdH , r e p o r t d a t a b a s e # In order to validate assembly quality and reliability, a self - qualification program has been performed f o r N i P d A u p r e- plated leadframes in SO14/16/20 family from assy center PST. The results of this qualification demonstrate that Philips Semiconductors can achieve distinctive assembly quality with equal or better product quality and reliability when compared to the lead - tin plated versions of these products. With the introduction of NiPdAu as Pb- free solution, the Bill of Materials (BoM) of the mentioned packages is fully compliant to the RoHS legislation requirements. 2. Assembly Facility PST Philips Semiconductors Thailand has been in operation in Bangkok Thailand since With a current workforce of approximately 3,800 personnel and its 60,000 square meter site, PST is capable of assembly and test of a wide range of DIP, SILP, SO, T/SSOP, IC Module and Contactless Module packages. Testing for QFP and PLCC is also available at PST. PST obtained ISO9001 certification in 1991, ISO14001 certification and the internal Philips Quality Awar d ( P Q A - 90) in 1996, and QS9000 certification in A strong emphasis on quality improvement programs has also resulted in PST receiving the Golden Pentastar Award from Chrysler Corporation. In August 2003, PST was ISO/TS certified. D a t e : 0 3 N o v e m b e r A u t h o r : Rob de Heus Page: 3 Revision: 02
4 3. Materials selection background 3.1 NiPdAu pre-plated leadframes main characteristics : good solderability with SnPb and Pb free solders good solder joint reliability used in high volume offered by major lead frame suppliers n on whisker - sensitive technology NiP d A u p r e- plated leadframes are chosen as alternative Pb- free solution and will be applied in SO, SSOP and TSSOP packages. Initially just for in - house assembly, later also at subcontractors delivering to Philips. Untill subcontractors can offer NiPdAu, their packages will be in matte Sn. In the long term roadmap, the part of NiPdAu might be increased to other families. D a t e : 0 3 N o v e m b e r A u t h o r : Rob de Heus Page: 4 Revision: 02
5 4. Constructional Details of Test vehicles Small pad SO for General Purpose Logic, Specialty Logic and Digital Datacom. Lot PST-1-01 PST-1-02 PST-1-03 PST-1-04 Assy Site PST PST PST PST Package / Pin S O 1 4 S O 1 4 S O 1 4 S O 1 6 O u t l i n e SOT108-1 SOT108-1 SOT108-1 SOT109-1 M o u l d i n g c o m p o u n d Die-Attach Adhesive P D D P Wire diameter in µ Pitch/ E or P / P / P / P / P Die Pad Size (mm) x x x x Die Size (mm) x x x x Vehicle name 7 4 H C 1 4 D 7 4 H C 1 0 D 7 4 L V D HEF4094BT Lot PST-1-05 PST-1-06 PST-1-07 PST-1-08 Assy Site PST PST PST PST Package / Pin S O 1 6 S O 1 6 S O 1 6 S O 2 0 O u t l i n e SOT109-1 SOT109-1 SOT109-1 SOT163-1 M o u l d i n g c o m p o u n d Die-Attach Adhesive P P D P Wire diameter in µ Pitch/ E or P / P / P / P / P Die Pad Size (mm) x x x x Die Size (mm) x x x x Vehicle name 7 4 A H C D HEF4794BT HEF4516BT 74LVC573AD Lot PST-1-09 PST-1-10 PST-1-11 Assy Site PST PST PST Package / Pin S O 2 0 S O 2 0 S O 2 0 O u t l i n e SOT163-1 SOT163-1 SOT163-1 M o u l d i n g c o m p o u n d Die-Attach Adhesive P P P Wire diameter in µ Pitch/ E or P / P / P / P Die Pad Size (mm) x x x Die Size (mm) x x x Vehicle name 7 4 A L V C D HEF4894BT 7 4 H C D D a t e : 0 3 N o v e m b e r A u t h o r : Rob de Heus Page: 5 Revision: 02
6 5. Reliability Test Program An extensive qualification program has been executed to demonstrate that PST can assemble P b - free NiPdAu packages with a high quality and reliability. 5.1 Reliability Test Descriptions In this section the reliability tests are described in d etail. These tests are stated in Philips Semiconductors General Quality Specification (SNW- FQ - 611) and the Plastic Package Qualification Guideline (SNW- FA ). AEC_Q100 is used as a guideline for specific automotive products. Pcon Preconditioning S MD Qualification samples for PPOT, HAST/THBS and TMCL undergo SMD reflow preconditioning before reliability test is performed. This preconditioning is performed in accordance with the latest revision of the IPC/JEDEC J- STD- 020B specification, as described in Philips Semiconductors specification SNW- FQ - 225A. SMD Packages are preconditioned to the appropriate MSL level. Peak temperature applied is 260 C. PPOT Pressure Pot Test Pressure Pot Test autoclave (121 C, 100%R.H., 96 hrs release time point), unbiased with Pcon. This test is particularly suitable to evaluate the moisture resistance of the package. HAST Highly Accelerated Stress Test Highly Accelerated Stress Test (130 C/85% R.H., 96 hrs release time point), with electrical bias and Pcon. This test stresses both the electrical endurance of the design/process, as well as the resistance to moisture of the package. THBS Temperature Humidity Bias Stress Temperature Humidity Bias Stress (85 C/85% R.H., 1000 hrs release time point), with electrical b ias and Pcon. This test stresses both the electrical endurance of the design/process, as well as the resistance to moisture of the package. This test is sometimes done instead of HAST TMCL Temperature Cycling Temperature Cycling (air to air 6 5 C C, 500 cyc release point) with Pcon. This test is aimed at the mechanical integrity of the whole product, under the severe circumstances of rapid changes in temperature. HTSL High Temperature Storage Life High Temperature Storage Life (150 C, h r s release time point). This test evaluates the reliability of the product after long term storage D a t e : 0 3 N o v e m b e r A u t h o r : Rob de Heus Page: 6 Revision: 02
7 5.2 Construction Analysis Tests Descriptions In addition to the reliability evaluation, qualification lots will be subjected to Construction Analysis and Moistu re Sensitivity Level assessment testing per the following test methods : Visual/Mechanical Inspection (V/M) S N W- FQ B Lead Finish Inspection (LFNH) Local document Moisture Sensitivity Level Assessment S N W- FQ B X - Ray Inspection (X- R A Y ) S N W- FQ SCAT Inspection (SCAT) S N W- FQ Die Shear Testing (DISH) S N W- FQ Bond Pull Testing (BPT) S N W- FQ Bond Shear Testing (BST) S N W- FQ Cross Section Inspection (CROSS) S N W- FQ Solderability Inspection (SOLD) S N W- FQ D a t e : 0 3 N o v e m b e r A u t h o r : Rob de Heus Page: 7 Revision: 02
8 5.3 Summary of Solder Joint Reliability Tests for leadfree, leadframe based packages Variants included in the Investigation SMD packages with gull wing and J leads (SO.,VSO, QFP..,PLCC ) Lead frame material : Copper - alloy (mainly) and FeNi42. Terminal finish : Matte Tin 100, NiPdAu (only for Copper alloy) 2 layer FR4 board, (CE 5004) Reflow soldering : SnPb36Ag2 and SnAg 3.8Cu0.7 Wave soldering with SnPb38Bi2 and SnAg3.8Cu0.7 Temperature Cycling º C/125º C according to IEC Electrical test (Daisy Chain) at around 2k intervals and visual inspection Conclusions No rejects up to 2000 cycles for all combinations. Mean time to failure over 6600 cycles except for FeNi based VSO56 and HTQFP100. Reflow solder : No significant difference in failure times/fracture modes between SnPb paste and SnAgCu paste. Wave solder : No significant difference in failure times/fracture modes between SnPb solder and SnAgCu solder. High profile packages / lead forms show less degradation due to a better compliancy Remarks All package variants applied with Pb and Pb- free soldering process Weibull graphs are shown in the E3 presentation. D a t e : 0 3 N o v e m b e r A u t h o r : Rob de Heus Page: 8 Revision: 02
9 Philips Semiconductors Leadfree for SO14/16/20 from PST 5.4 Self-qualfication results NiPdAu packages Table 1 : Reliability Tests NiPdAu Lot PPOT HAST TMCL HTSL Package No. Device Pcon hrs pcon 96 hrs 192 hrs Pcon 200c 500c 1000h 2000h hrs SO14 PST HC14D 0/77 0/ /77 0/77 0/77 0/77 - SO14 PST HC10D 0/77 0/ /77 0/77 0/77 0/77 - SO14 PST LV4066D 0/77 0/ /77 0/77 0/77 0/77 - SO16 PST-1-04 HEF4094BT 0/77 0/77-0/45 0/45-0/77 0/77 0/77 0/77 - SO16 PST AHC595D 0/77 0/ /77 0/77 0/77 0/77 - SO16 PST-1-06 HEF4794BT 0/77 0/77-0/45 0/45-0/77 0/77 0/77 0/77 - SO16 PST-1-07 HEF4516BT 0/77 0/ /77 0/77 0/77 0/77 - SO20 PST LVC573AD 0/77 0/ /77 0/77 0/77 0/77 - SO20 PST ALVC573D 0/77 0/ /77 0/77 0/77 0/77 - SO20 PST-1-10 HEF4894BT 0/77 0/77-0/45 0/45-0/77 0/77 0/77 0/77 - SO20 PST HC299D 0/77 0/ /77 0/77 0/77 0/77 - Reliability qualification requirements time points are shown in bold, additional points are for engineering evaluation. Date: 03 Novemb e r A u t h o r : Rob de Heus Page: 9 Revision: 02
10 Philips Semiconductors Leadfree for SO14/16/20 from PST Table 2: Construction Analysis tests NiPdAu. Lot Construction Analysis Tests Package No. Device MSLA V/M LFNH SOLD XRAY SCAT DISH BP/BS CROSS 260 C See note SO14 PST HC14D L1 0/15 0/9 4x0/11 0/8 0/8 0/3 0/3 0/3 SO14 PST HC10D L SO14 PST LV4066D L1 0/15 0/9 4x0/11 0/8 0/8 0/3 0/3 0/3 SO16 PST-1-04 HEF4094BT L SO16 PST AHC595D L1 0/15 0/9 4x0/11 0/8 0/8 0/3 0/3 0/3 SO16 PST-1-06 HEF4794BT L1 0/15 0/9 4x0/11 0/8 0/8 0/3 0/3 0/3 SO16 PST-1-07 HEF4516BT L1 0/15 0/9 4x0/11 0/8 0/8 0/3 0/3 0/3 SO20 PST LVC573AD L SO20 PST ALVC573D L1 0/15 0/9 4x0/11 0/8 0/8 0/3 0/3 0/3 SO20 PST-1-10 HEF4894BT L1 0/15 0/9 4x0/11 0/8 0/8 0/3 0/3 0/3 SO20 PST HC299D L Note: 11 parts tested in SnPb solder after 8h steam age, 5 sec, 215 ºC 11 parts tested in SnPb solder after 16h dry-bake, 5 sec, 215 ºC 11 parts tested in SAC solder after 8h steam age, 3 sec, 245 ºC 11 parts tested in SAC solder after 16h dry-bake, 3 sec, 245 ºC RMA flux used for all tests. Date: 03 Novemb e r A u t h o r : Rob de Heus Page: 1 0 Revision: 02
11 Philips Semiconductors Leadfree for SO14/16/20 from PST Table 3: Construction Analysis tests NiPdAu, additional tests for automotive. Lot Package No. Device BPT after TMCL 500c SO14 PST HC14D 0/5 SO14 PST HC10D 0/5 SO14 PST LV4066D 0/5 SO16 PST-1-04 HEF4094BT 0/5 SO16 PST AHC595D 0/5 SO16 PST-1-06 HEF4794BT 0/5 SO16 PST-1-07 HEF4516BT 0/5 SO20 PST LVC573AD 0/5 SO20 PST ALVC573D 0/5 SO20 PST-1-10 HEF4894BT 0/5 SO20 PST HC299D 0/5 Construction Analysis Tests Date: 03 Novemb e r A u t h o r : Rob de Heus Page: 1 1 Revision: 02
12 Assembly & Test Organization Philips Semiconductors Leadfree for SO14/16/20 from PST 6. Conclusion An extensive qualification program has been executed to demonstrate that PST can assemble S O 1 4 / 1 6 / 2 0 p a c k a g e s i n N i P d A u p r e- plated lead - frames at a high quality and reliability level. All parts tested in this qualification program, show that the Moisture Sensitivity Levels at 260 ºC are level 1, as before with Cu - A g- spot leadframes. With the positive completion of the Qualification tests, the Assembly and Test Organization Philips Semiconductors announces the release of NiPdAu pre- plated leadframes for use in SO14/16/20 p r o d u c t s f o r G e n e r a l P u r p o s e Logic, Specialty Logic and Digital Datacom, assembled in PST, via final CPCN F phase Implementation Deliveries will start from December 2003 onwards. 8. Document Revision Sheet R E V I S I O N S H E E T DATE REV DESCRIPTION A U T H O R yyyy/mm/dd Self Qualification Results phase 1 for Lead (Pb) R o b d e H e u s free lead - finish of leadframe - based IC packages. SO14/16/20 for General Purpose Logic Minor update R o b d e H e u s D a t e : 0 3 N o v e m b e r A u t h o r : Rob de Heus Page: 12 Revision: 02
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