INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 NTEGRATED CRCUTS DATA SEET For a complete data seet, please also download: Te C 74C/CT/CU/CMOS Logic Family Specifications Te C 74C/CT/CU/CMOS Logic Package nformation Te C 74C/CT/CU/CMOS Logic Package Outlines 4-bit bidirectional universal sift register File under ntegrated Circuits, C December 199

2 FEATURES Sift-left and sift-rigt capability Syncronous parallel and serial data transfer Easily expanded for bot serial and parallel operation Asyncronous master reset old ( do noting ) mode Output capability: standard CC category: MS GENERAL DESCRPTON Te are ig-speed Si-gate CMOS devices and are pin compatible wit low power Scottky TTL (LSTTL). Tey are specified in compliance wit JEDEC standard no. 7A. Te functional caracteristics of te 4-bit bidirectional universal sift registers are indicated in te logic diagram and function table. Te registers are fully syncronous. Te 194 design as special features wic increase te range of application. Te syncronous operation of te device is determined by te mode select inputs (S, S 1 ). As sown in te mode select table, data can be entered and sifted from left to rigt (Q Q 1 Q 2, etc.) or, rigt to left (Q 3 Q 2 Q 1, etc.) or parallel data can be entered, loading all 4 bits of te register simultaneously. Wen bot S and S 1 are LOW, existing data is retained in a old ( do noting ) mode. Te first and last stages provide D-type serial data inputs (D SR, D SL ) to allow multistage sift rigt or sift left data transfers witout interfering wit parallel load operation. Mode select and data inputs are edge-triggered, responding only to te LOW-to-G transition of te clock (CP). Terefore, te only timing restriction is tat te mode control and selected data inputs must be stable one prior to te positive transition of te clock pulse. Te four parallel data inputs (D to D 3 ) are D-type inputs. Data appearing on te D to D 3 inputs, wen S and S 1 are G, is transferred to te Q to Q 3 outputs respectively, following te next LOW-to-G transition of te clock. Wen LOW, te asyncronous master reset (MR) overrides all oter input conditions and forces te Q outputs LOW. Te 194 is similar in operation to te 195 universal sift register, wit added features of sift-left witout external connections and old ( do noting ) modes of operation. QUCK REFERENCE DATA GND = V; T amb =25 C; t r =t f = ns TYPCAL SYMBOL PARAMETER CONDTONS C CT UNT t PL / t PL propagation delay C L = 15 pf; V CC =5 V CP to Q n ns t PL MR to Q n ns f max maximum clock frequency Mz C input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine te dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C L V 2 CC f o ) were: f i = input frequency in Mz f o = output frequency in Mz =(C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For C te condition is V = GND to V CC ; for CT te condition is V = GND to V CC 1.5 V December 199 2

3 ORDERNG NFORMATON See 74C/CT/CU/CMOS Logic Package nformation. PN DESCRPTON PN NO. SYMBOL NAME AND FUNCTON 1 MR asyncronous master reset input (active LOW) 2 D SR serial data input (sift rigt) 3, 4, 5, D to D 3 parallel data inputs 7 D SL serial data input (sift left) 8 GND ground ( V) 9, 1 S, S 1 mode control inputs 11 CP clock input (LOW-to-G edge-triggered) 15, 14, 13, 12 Q to Q 3 parallel outputs 1 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 EC logic symbol. December 199 3

4 Fig.4 Functional diagram. FUNCTON TABLE OPERATNG MODES NPUTS OUTPUTS CP MR S 1 S D SR D SL D n Q Q 1 Q 2 Q 3 reset (clear) L L L L L old ( do noting ) q q 1 q 2 q 3 sift left sift rigt Notes 1. = G voltage level = G voltage level one prior to te LOW-to-G CP transition L = LOW voltage level = LOW voltage level one prior to te LOW-to-G CP transition q,d = lower case letters indicate te state of te referenced input (or output) one prior to te LOW-to-G CP transition = don t care = LOW-to-G CP transition q 1 q 2 q 3 q 1 q 2 q 3 L L q q 1 q 2 q q 1 q 2 parallel load d n d d 1 d 2 d 3 December 199 4

5 Fig.5 Logic diagram. Fig. Typical clear, clear-load, sift-rigt, sift-left, inibit and clear timing sequences. December 199 5

6 DC CARACTERSTCS FOR 74C For te DC caracteristics see 74C/CT/CU/CMOS Logic Family Specifications. Output capability: standard CC category: MS December 199

7 AC CARACTERSTCS FOR 74C GND = V; t r =t f = ns; C L = 5 pf SYMBOL t PL / t PL t PL PARAMETER propagation delay 47 CP to Q n 14 propagation delay 39 MR to Q n t TL / t TL output transition time 19 7 t W t W t rem f max clock pulse widt G or LOW master reset pulse widt; LOW removal time MR to CP D n to CP S, S 1 to CP D SR, D SL to CP D n to CP S, S 1 to CP D SR, D SL to CP maximum clock pulse frequency T amb ( C) 74C to to +125 min. typ. max. min. max. min. max UNT TEST CONDTONS V CC (V) ns 2.. ns 2.. ns 2.. ns 2.. ns 2.. ns 2.. ns 2.. ns 2.. ns 2.. ns 2.. ns 2.. ns 2.. Mz 2.. WAVEFORMS Fig.7 Fig.8 Fig.7 Fig.7 Fig.8 Fig.8 Fig.9 Fig.1 Fig.9 Fig.1 Fig.7 December 199 7

8 DC CARACTERSTCS FOR 74CT For te DC caracteristics see 74C/CT/CU/CMOS Logic Family Specifications. Output capability: standard CC category: MS Note to CT types Te value of additional quiescenpply current ( CC ) for a unit load of 1 is given in te family specifications. To determine CC per input, multiply tis value by te unit load coefficient sown in te table below. NPUT D n D SR, D SL CP MR S n UNT LOAD COEFFCENT December 199 8

9 AC CARACTERSTCS FOR 74CT GND = V; t r =t f = ns; C L = 5 pf T amb ( C) TEST CONDTONS ns Fig ns Fig.8 74CT SYMBOL PARAMETER UNT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t PL / t PL propagation delay CP to Q n t PL propagation delay MR to Q n t TL / t TL output transition time ns Fig.7 t W t W t rem f max clock pulse widt G or LOW master reset pulse widt; LOW removal time MR to CP D n to CP S, S 1 to CP D SR, D SL to CP D n to CP S, S 1 to CP D SR, D SL to CP maximum clock pulse frequency ns Fig ns Fig ns Fig ns Fig ns Fig ns Fig.9 7 ns Fig.9 5 ns Fig.1 7 ns Fig Mz Fig.7 December 199 9

10 AC WAVEFORMS (1) C : V M = 5%; V = GND to V CC. CT: V M = 1.3 V; V = GND to 3 V. (1) C : V M = 5%; V = GND to V CC. CT: V M = 1.3 V; V = GND to 3 V. Fig.7 Waveforms sowing te clock (CP) to output (Q n ) propagation delays, te clock pulse widt, te output transition times and te maximum clock frequency. Fig.8 Waveforms sowing te master reset (MR) pulse widt, te master reset to output (Q n ) propagation delays and te master reset to clock (CP) removal time. Te saded areas indicate wen te input is permitted to cange for predictable output performance. (1) C : V M = 5%; V = GND to V CC. CT: V M = 1.3 V; V = GND to 3 V. Te saded areas indicate wen te input is permitted to cange for predictable output performance. (1) C : V M = 5%; V = GND to V CC. CT: V M = 1.3 V; V = GND to 3 V. Fig.1 Waveforms sowing te set-up and old times from te mode control inputs (S n ) to te clock input (CP). PACKAGE OUTLNES Fig.9 Waveforms sowing te set-up and old times from te data inputs (D n, D SR and D SL ) to te clock (CP). See 74C/CT/CU/CMOS Logic Package Outlines. December 199 1