TSV Interposer: The Most Cost-Effective Integrator for 3D IC Integration

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1 Interposer: The Most Cost-Effective Integrator for 3D IC Integration John H. Lau Electronics & Optoelectronics Research Laboratories Industrial Technology Research Institute (ITRI) Chutung, Hsinchu, Taiwan 310, R.O.C ,

2 Objectives To investigate the significant roles of Cu-filled passive interposers for 3D IC integration. Emphasis is placed on the roles they play as: (1) Substrates (2) Reliability buffers (3) Carriers (4) Thermal management tools It is shown that the Cu-filled passive interposers are the most cost-effective integrator for 3D IC integration system-inpackage (SiP).

3 Contents (1) INTRODUCTION (2) 3D IC INTEGRATION (3) 3D IC MEMORY-CHIPS STACKING (4) 3D IC INTEGRATION: ACTIVE INTERPOSERS (5) 3D IC INTEGRATION: PASSIVE INTERPOSERS A. Passive Interposers as Substrates/Carriers (2.5D IC Integration) B. Cu-Filled Passive Interposers as Reliability Buffers for Moore s Law chips C. Passive Interposers as the Integrators for Moore s Law Chips (3D IC Integration) D. Passive Interposers used as Effective Thermal Management tools and Low-Cost Integrators for Moore s Law chips (3D IC Integration) (6) SUMMARY AND RECOMMENDATIONS (7) ACKNOWLEDEGEMENTS

4 3D Integration Technologies 3D IC Packaging 3D IC Integration 3D Si Integration Mass Production Full swing production for memories. Testing and yield challenges give way for package stacking Maturity Commercialization Applied R&D Basic/A pplied R&D Die Stacking with wire bonds Package on Package Stacking (PoP) C2C, C2W, W2W Stacking Active applied R&D is undertaken by Research Institutes. System level challenges are key. In the phase of industrialization. Still in upstream research, technological challenges such as yield & device architecture are key issues. W2W Stacking Lau Technology 4 Lau, Lee, Prem, Yu, 3D MEMS Packaging, McGraw-Hill, 2009

5 Evolution of 3D integration The origin of 3D Integration (1980) 3D integration was trigged by the silicon-on-insulator (SOI) technology 30 years ago, when people thought Moore s law could be hitting the wall by the 1990s. 3D Si Integration (was favored in 1980s) Stacking up wafers with s for electrical feed through. Bumpless! 3D IC Integration (was rejected in 1980s) Stacking up the chips with s and solder bumps The invention of (1958) Shockley's invention was not meant for 3D integration A boost (1985) by Richard Feynman Go 3D instead of all on a surface of a chip! Long way to go! Need Ecosystem, EDA, Technology 3D IC Integration with microbumps and thin chips (has been favored since 2000s) Because of the disappointment of 3D Si Integration, and using thin chips and microbumps No sight in Volume Production in the next 10 years The right way to go and compete with Moore s law. Hopefully in production (at least for memory-chips stacking) by 2020! Memorychips Stacking Cost issues and Competing technology Active Interposers (Memory/Logic + CPU/Logic) Need Ecosystem, EDA, and Business models Passive Interposers (2.5D & 3D) Will be used the most in the next 10 years Thin Wafers 560μm thick 2Gb Chips (16Gb) 2.5D IC Integration with Passive Interposer /RDL/IPD Passive Interposer Micro Bump W2W (SiO 2 -SiO 2 ) bonding Cu Bumpless Cu Micro bump Memory CPU/ Logic Micro bump 3D IC Integration with Passive Interposer /RDL/IPD Passive Interposer Micro Bump

6 Xilinx s 4 FPGAs on a Passive Interposer

7 Xilinx s FPGA Wide I/O Interface

8 ITRI Phase-I 3D IC Integration Test Vehicle Not-to-scale Electrical Stress sensor : 10μm Micro bumps is optional 100μm Mechanical :15μm :10μm 50μm IPD Thermal :15μm 100μm 80μm /RDL/IPD Interposer Ordinary bumps RDL RDL ` ` :15μm 1mm Organic (BT) substrate I/O:400 ball array, pitch:450μm 350μm Solder balls 1.2mm I/O:400 ball array, pitch:1mm PCB PCB ITRI Phase-I 3D IC Integration SiP 8

9 ITRI Phase-I 3D IC Integration Test Vehicle ITRI s Phase-I 3D IC integration SiP Mechanical Chip 4-chip stacked Thermal chip interposer BT-substrate

10 Semi-Embedded Interposer with Stress Relief Gap Moore s Law chips 10

11 Cu-filled can be a Stress Relief (Reliability) Buffer for the Cu-low-k Pads of a Moore s law Chip TCE = 2.5x10-6 / o C u-filled interposer Mirco solder joint Moore s law Chip Special Underfill TCE = 8-10x10-6 / o C Ordinary Underfill BT-Substrate MPa a) PCB Ordinary solder joint MPa Mirco solder joint Moore s law Chip BT-Substrate Special Underfill Conventional FCBGA with 42MPa FCBGA with interposer and underfill Category FCBGA1 Category interposer 2 Category 3 b) PCB Lau TCE = 15x10-6 / o C Selcanayagam and Lau, et al., IEEE/ECTC08, Also, IEEE Transactions Zhang, Lau, et al., IEEE/ECTC 2009, Also, IEEE Transactions 2010 Lau and Zhang, ASME Paper: InterPACK

12 IME Interposers (Carriers)

13 Evolution of 3D integration The origin of 3D Integration (1980) 3D integration was trigged by the silicon-on-insulator (SOI) technology 30 years ago, when people thought Moore s law could be hitting the wall by the 1990s. 3D Si Integration (was favored in 1980s) Stacking up wafers with s for electrical feed through. Bumpless! 3D IC Integration (was rejected in 1980s) Stacking up the chips with s and solder bumps The invention of (1958) Shockley's invention was not meant for 3D integration A boost (1985) by Richard Feynman Go 3D instead of all on a surface of a chip! Long way to go! Need Ecosystem, EDA, Technology 3D IC Integration with microbumps and thin chips (has been favored since 2000s) Because of the disappointment of 3D Si Integration, and using thin chips and microbumps No sight in Volume Production in the next 10 years The right way to go and compete with Moore s law. Hopefully in production (at least for memory-chips stacking) by 2020! Memorychips Stacking Cost issues and Competing technology Active Interposers (Memory/Logic + CPU/Logic) Need Ecosystem, EDA, and Business models Passive Interposers (2.5D & 3D) Will be used the most in the next 10 years Thin Wafers 560μm thick 2Gb Chips (16Gb) 2.5D IC Integration with Passive Interposer /RDL/IPD Passive Interposer Micro Bump W2W (SiO 2 -SiO 2 ) bonding Cu Bumpless Cu Micro bump Memory CPU/ Logic Micro bump 3D IC Integration with Passive Interposer /RDL/IPD Passive Interposer Micro Bump

14 passive interposer supporting high-power chips (e.g., microprocessor and logic) on its top side and low-power chips (e.g., memory) on its bottom side Microbumps Adhesive Interposer with RDL & IPD TIM Heat Spreader + Sink (if needed) Microprocessor/ ASIC Stiffener ring Simple organic substrate PCB Ordinary solder bumps Memory Solder balls Special underfills are needed between the Cu -filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

15 interposer supporting high-power chips on its top side and low-power chips on its bottom side with a cavity. Microbumps Adhesive /RDL/IPD interposer with a cavity TIM Heat Spreader + Sink (if needed) Microprocessor/ ASIC Stiffener ring Simple organic substrate PCB Ordinary solder bumps Solder balls Special underfills are needed between the Cu-filled interposer and all the chips. Ordinary underfills are needed between the interposer and the organic substrate.

16 Passive interposer with RDL and IPD supporting highpower chips on its top-side and low-power chips at its bottom-side. The organic substrate is with a cavity

17 Dimensions of the passive interposer with 4 highpower flip chips on its top and 16 low-power flip chips at its bottom (the gist of the 3D IC integration SiP.) Interposer 10mm Interposer 5mm 35mm 10mm 35mm 5mm Interposer High Power Chip 200µm 200µm High power chip Low power chip Low Power Chip 200µm 60mm Solder bump 35mm 35mm The 4 high power chips are the same and uniformly distributed over the interposer. 150µm High Power Chip There are 66 bumps on each side. Totally 260 bumps. 60µm Solder Bump The 16 low power chips are the same and uniformly distributed over the interposer. 400µm Low power chip There are 11 bumps on each side. Totally 40 bumps. 60µm Solder bump 850µm Cu 20µm 200µm Interposer There are 1600 s in the interposer. So there are 400 s in the quarter model. Top View Bottom View Side View ASME Paper no. IMECE Lau

18 Thermal Management System of 3D IC Integration Supported by a Interposer Thermal Interface Material Stiffener Heat Spreader Heat Sink Micro Bumps Adhesive High-power Chip High-power Chip Low-power Chip Heat Slug PCB PCB Organic Substrate Ordinary Solder Bumps Interposer with RDL & IPD Solder Balls Special underful between the interposer and the high- and low-power flip chips. Ordinary underful between the interposer and the organic substrate.

19 Low-Cost TSH (Through-Si Holes) Interposer for 3D IC Integration Through-Si Holes (TSH) Interposer Moore s Law chip Solder joints Non-metallization holes on the TSH interposer RDL RDL RDL Solder bump RDL RDL Cu/Au Stud, wire, or pillow RDL Solder bump Organic Substrate/PCB 1. Underfills are optional between the Moore s law chips and the interpose when they are subjected to thermal loading! However, for shock and vibration loads, and depending on chip size, underfills may be needed! 2. Underfills between the TSH and the organic substrate/pcb are necessary!

20 Embedded 3D IC Integration with Optical Devices Serializer or deserializer Driver chip or TIA Heat Slug VCSEL or PD Cu Heat Spreader TIM Solder Ball TIM Heat Slug Heat Slug Mirror Polymer Waveguide Optical layer support (film) Mirror Laminated Substrate/Board Special Underfills (e.g., Transparent) Buried via (filled or unfilled) for electrical interconnects Special Underfills (e.g., Transparent) VCSEL = Vertical Cavity Surface Emitted Laser (transparent); PD = Photo Diode Detector (transparent); TIA = Trans-Impedance Amplifier 20

21 3D IC integration SiP consists of a series of /RDL/IPD interposers with embedded fluidic channels to support multiple Moore s law chips without any s /RDL/IPD Interposer with embedded fluidic channels to support multiple Moore s law chips without any s Substrate PCB

22 /RDL/IPD interposer with embedded fluidic channels supporting all kinds of chips on its top and bottom sides /RDL/IPD interposer with embedded fluidic channels to support Moore s law chips with no s IPD RDL Moore s law chips s Micro-channels Microbumps Solder bumps

23 Interposer (carrier) with s for electrical feed through and fluidic microchannels for thermal management Fluidic inlet Fluidic outlet Fluidic channel Fluidic inlet Fluidic outlet Top-side Fluidic Channel Bottom-side

24 Fabricated and embedded fluidic microchannel carrier (interposer). The, sealing ring for s, sealing ring for micochannels. Au20Sn solder bumps and Ti/Cu/Ni/Au UBMs

25 For channel height = 700μm, flow rate = 0.54L/min. Top Left (interposer and LEDs temperature distribution); Top Right (LEDs temperature distribution); Bottom Left (ASICs temperature distribution); Bottom Right (flow path in channel) Interposer and LEDs temperature distribution LEDs temperature distribution ASICs temperature distribution Flow path in channel

26 3D IC integration ( interposer with embedded fluidic microchannels) 3D Integration Roadmap Volume Production 3D IC integration ( interposer with chips on both sides) 2.5D IC integration ( interposer with chips on top-side) CIS with (2.5D) CIS with and DSP MEMS on ASIC with Multi-LEDs on chip with Wide I/Os DRAM Memory/Logic + CPU/Logic with Memory stacking Memory/Logic + CPU/Logic

27 SUMMARY AND RECOMMENDATIONS The roles played by the Cu-filled passive interposers for 3D IC integration have been investigated in this study. It has been demonstrated that the Cu-filled passive interposers are cost-effective 2.5D IC integration substrates and carriers, as well as 3D IC integrator, thermal management tools, and reliability buffers. Some important results and recommendations are summarized in the following. 1. In the next 10 years, the s will be fabricated the most (by the number of vias) for Cu-filled passive interposers. 2. Passive interposer is the most cost-effective 3D IC integrator. It is not only for substrates, carriers, but also thermal managements. Let the passive interposer be the workhorse of 3D IC integration SiPs! 3. Besides it is the most cost-effective 3D IC integrator, the Cu-filled passive interposer acts like a stress relief (reliability) buffer, which reduces the stress acting on the Cu-low-k pads on Moore s law chips. This advantage becomes more pronounced when the feature size is getting smaller and so does the allowable stress of the chip pads. 4. A few true cost-effective 3D IC integration SiPs with Cu-filled passive interposers have been proposed. 5. 3D Si integration is the right way to go and compete with Moore s law. Hopefully, by 2020 at least the memory chips stacking could be manufactured at lower costs and higher throughputs by using the 3D Si integration technology. The industry should stride to make this happens!

28 Acknowledgements The author would like to express thanks to the financial support by Ministry of Economic Affairs (MOEA), Taiwan, R.O.C., and the strong support by the VP and Director of Electronics & Optoelectronics Research Lab, Dr. Ian Chan of ITRI.

29 Thank you very much for your attention! Lau 29

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