Diode-Transistor Logic (DTL) University of Connecticut 56

Transcription

1 Diode-Transistor Logic (DTL) University of Connecticut 56

2 Diode Logic AND GATE OR GATE Diode Logic suffers from voltage degradation from one stage to the next. Diode Logic only permits the OR and AND functions. Diode Logic is used extensively but not in integrated circuits! University of Connecticut 57

3 Level-Shifted Diode Logic AND GATE =5V x R H DL R L With either input at 0V, V x =0.7V, D L is just cut off, and =0V. With both inputs at 1V, V X =1.7V and =1V. With = =5V, both input diodes are cut off. Then V R V V CC 0. 7 OUT = L R + R H L Level shifting eliminates the voltage degradation from the input to the ouput. However, the logic swing falls short of rail-to-rail, and the inverting function still is not available without using a transistor! University of Connecticut 58

4 Diode-Transistor Logic (DTL) Primitive Precursor to DTL Q 1 If any input goes high, the transistor saturates and goes low. If all inputs are low, the transistor cuts off and goes high. This is a NOR gate. Current Hogging is a problem because the bipolar transistors can not be matched precisely. University of Connecticut 59

5 Diode-Transistor Logic (DTL) R B Improved gate with reversed diodes. Q 1 If all inputs are high, the transistor saturates and goes low. If any input goes low, the base current is diverted out through the input diode. The transistor cuts off and goes high. This is a NAND gate. The gate works marginally because V D = EA = 0.7V. University of Connecticut 60

6 Diode-Transistor Logic (DTL) R B x Basic DTL NAND gate. Q 1 R D If all inputs are high, V x = 2.2V and the transistor is saturated. If any input goes low (0.2V), V x =0.9V, and the transistor cuts off. The added resistor R D provides a discharge path for stored base charge in the BJT, to provide a reasonable t PLH. University of Connecticut 61

7 DTL VTC 5 4 R B x 3 Q 1 2 R D V IN V OH = V OL = V IL = V IH = The noise margins are more symmetric than in the RTL case. University of Connecticut 62

8 DTL Power Dissipation R B =3.4kΩ =4.8kΩ R D =1.6kΩ P L = R B x Q 1 R D P H = Scaling R B and involves a direct tradeoff between speed and power. P = University of Connecticut 63

9 DTL Fanout R B =3.4kΩ =4.8kΩ R D =1.6kΩ β F =50 R B I CS = x Q 1 R D I BS = Good fanout requires high β F, large R D /R B. I CS = N max = University of Connecticut 64

10 930 Series DTL (ca 1964 A.D.) β F = kΩ 2kΩ Q 1 6kΩ One of the series diodes is replaced by Q 1, providing more base drive for Q 2 and improving the fanout (N max = 45). Does Q 1 saturate? 5kΩ Q DTL Characteristics V OH / V OL V IH / V IL Fanout Dissipation t P 5.0V / 0.2V 1.5V / 1.4V 45 10mW 75ns University of Connecticut 65

11 930 DTL Propagation Delays β F =50 C L =5pF t PLH >> t PHL 1.75kΩ 6kΩ t PLH = t S +t r /2 2kΩ t s = Q 1 Q 2 5kΩ t r University of Connecticut 66

12 Transistor-Transistor Logic (TTL) University of Connecticut 67

13 Why TTL? DTL TTL The DTL input uses a number of diodes which take up considerable chip area. In TTL, a single multi-emitter BJT replaces the input diodes, resulting in a more area-efficient design. DTL was ousted by faster TTL gates by University of Connecticut 68

14 Basic TTL NAND Gate. =5V ALL INPUTS HIGH. R B P Q I is reverse active. Q O is saturated. Q I D 1 R D Q O V OL = ES ANY INPUT LOW. Q I is saturated. Q O is cut off. V OH = Multi-emitter transistor. Forward-biased emitter base junctions override reverse-biased junctions in determining the base and collector currents. University of Connecticut 69

15 TTL Switching Speed: t PLH =5V R B P Q I Q S Q O C R L D The depletion capacitance of the Q I EB junction must discharge; Base charge must be removed from the saturated Q S ; Ditto for Q O ; and The capactive load must be charged to. Multi-emitter transistor. Forward-biased emitter base junctions override reverse-biased junctions in determining the base and collector currents. University of Connecticut 70

16 TTL Switching Speed: t PLH =5V R B P Q I Q S Q O C R L D The time required to discharge the Q I depletion layers is << 1ns. The time required to extract the Q S base charge is also << 1ns: Q I becomes forward active; I BR becomes large for Q S Removal of base charge from Q O is similar to the DTL case. With R D = 1 kω, t s = 10ns (these are typical values for 7400 series TTL). University of Connecticut 71

17 TTL Switching Speed: t PLH =5V 5 4 R B P 3 Q I Q S 2 Q O 1 R D C L t (ns) Charging of the capacitive load can be slow with passive pullup. e.g., with a 5kΩ pull-up resistor and a 15 pf load (ten TTL gates) RC = 75 ns and t r = 2.3RC = 173 ns! University of Connecticut 72

18 TTL with Active Pullup In the previous example, the dominant switching speed limitation was the charging of capacitive loads through the pullup resistor. A small pullup resistance will improve the switching speed but will also increase the power and reduce the fanout. R D When the output is low, Q P is cutoff, Q P minimizing the power and maximizing the fanout; Q O With active pullup, we can achieve the best of both worlds: when the output goes high, Q P becomes forward active to provide maximum drive current for a quick rise time. University of Connecticut 73

19 TTL with Active Pullup With a high output, Q S is cutoff Q P is forward active With a low output, Q S is saturated Q P should be cutoff The low output case is unsatisfactory with this circuit: P = V EP = EP = =5V R B Q P Q I Q S Q O R D The Totem Pole Output solves this problem. University of Connecticut 74

20 TTL with Totem Pole Output R B =5V P During turn-off, Q S switches off before Q O. Q P begins to conduct when Q I Q S Q P D L S = ESO +V D +EAP = 1.6V Initially, I BP = Q O R D P limits the collector current to a safe value. University of Connecticut 75

21 Typical 74xx Series TTL Q I 4kΩ Q S =5V 1.6kΩ 130Ω Q P D L 74xx TTL Characteristics t PLH t PHL Fanout Dissipation PDP 12 ns 8 ns mw 100 pj 1/3 T. I triple 3-input NAND 1kΩ Q O The anti-ringing diodes at the input are normally cut off. During switching transients, they turn on if an input goes more negative than -0.7V. University of Connecticut 76

22 Standard TTL: VTC β F =70 β R = 0.1 =5V V IN =0. Q I is saturated; Q S, Q O are cutoff; Q P is forward active. 4kΩ 1.6kΩ 130Ω V OH = Q P V IN Q I Q S D L (the drop in the base resistor is small) 1kΩ Q O First Breakpoint. Q S turns on. 1/6 NSC 7404 Hex Inverter V IL = (at the edge of conduction, I C =0) University of Connecticut 77

23 Standard TTL: VTC β F =70 β R = 0.1 4kΩ =5V 1.6kΩ Q P 130Ω Second Breakpoint. Q O turns on. V IN = = V IN Q I Q S 1kΩ Q O D L Third Breakpoint. Q O saturates. V IH = 1/6 NSC 7404 Hex Inverter University of Connecticut 78

24 Standard TTL: VTC 1/6 NSC 7404 Hex Inverter =5V 5 4kΩ V IN Q I Q S 1.6kΩ Q P 130Ω D L β F =70 β R = 0.1 1kΩ Q O V IN V NML = V NMH = University of Connecticut 79

25 Standard TTL: Low State R OUT collector current (ma) Characteristics for a Texas Instruments junction isolated digital npn BJTat 25 o C ma 0.08V 2.4 ma 2 ma 1.6 ma 1.2 ma 0.8 ma I B = 0.4mA collector-emitter voltage (V) For the saturated BJT with I B = 2.4 ma, the output impedance is R OL = The very low output impedance means that noise currents are translated into tiny noise voltages. Thus only a small noise margin is neccesary. University of Connecticut 80

26 Standard TTL: Input Current 1/4 TI 7400 Quad 2-input NAND 4kΩ =5V 1.6kΩ 130Ω I IH (Q I is reverse active) I BI = Q I Q S Q P D L I IH = β F =70 β R = 0.1 1kΩ Q O I IL (Q I is saturated) I IL = University of Connecticut 81

27 Standard TTL: DC Fanout 1/4 TI 7400 Quad 2-input NAND 4kΩ =5V 1.6kΩ 130Ω With high inputs, I I CI CS = = Q I Q S Q P D L β F =70 β R = 0.1 1kΩ Q O I BO = To keep Q O saturated, N max = AC considerations usually limit the fanout to a much lower number. University of Connecticut 82

28 Standard TTL: DC Dissipation 1/4 TI 7400 Quad 2-input NAND =5V P H = 4kΩ 1.6kΩ 130Ω Q I Q S Q P D L P L = β F =70 β R = 0.1 N = 10 1kΩ Q O P = University of Connecticut 83

29 Advanced TTL Designs Schottky Clamping. Q S and Q O may be Schottky clamped, preventing saturation. This greatly improves t PLH. Darlington Pullup. The Darlington pullup arrangement increases the average output drive current for charging a capacitive load. Although P limits the maximum output current, this maximum drive is maintained over a wider range of than with a single pullup transistor. Squaring Circuit. Active pull-down for the base of the output transistor squares the VTC, improving the low noise margin. An added benefit is faster charge removal for the output transistor. Improved Fabrication. Smaller devices, and oxide isolation, have steadily reduced parasitic capacitances and reduced RC time constants. University of Connecticut 84

30 Darlington Pullup 900Ω R EP 3.5kΩ Q P =5V P 50Ω Q P2 Q P2 is added, forming a Darlington pair with Q P. The EB junction of Q P2 introduces a 0.7V level shift, so DL can be eliminated. Q P2 can not saturate, so Schottky clamping is not neccessary. R EP is needed to provide a discharge path for Q P2 base charge. The Darlington emitter follower provides a very low output impedance, approaching /β 2. This greatly reduces the rise time. University of Connecticut 85

31 Squaring Circuit R BD 500Ω Q S Q D RCD 250Ω Q O V OH There is no path for Q S emitter current until Q D and Q O turn on. Q S and Q O begin to conduct simultaneously. BP1 is eliminated from the VTC; in other words, the VTC is squared. V OL V IL is increased, improving the low noise margin V IL BP V IH BP S00 V IN University of Connecticut 86

32 Schottky TTL (74S / 54S Series) 1/4 74S00 quad 2-input NAND =5V Features: R B P 2.8kΩ Q I 900Ω Q S R EP 3.5kΩ Q P Q P2 50Ω Schottky clamping Schottky anti-ringing diodes Darlington pullup circuit Squaring circuit Scaled resistors R BD 500Ω Q D RCD 250Ω Q O Performance: P = 20 mw t P = 3 ns (15 pf) PDP = 60 pj University of Connecticut 87