0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L U.L U.L U.L U.L. 15 (7.5) U.L. CONNECTION DIAGRAM DIP (TOP VIEW)

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1 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL -TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54/ coists of eight latches with 3-state outputs for bus organized system applicatio. The flip-flops appear traparent to the data (data changes asynchronously) when Latch Enable () is HIGH. When is LOW, the data that meets the setup times is latched. ata appears on the bus when the Output Enable () is LOW. When is HIGH the bus output is in the high impedance state. The SN54/ LS3 is a high-speed, low-power Octal -type Flip-Flop featuring separate -type inputs for each flip-flop and 3-state outputs for bus oriented applicatio. A buffered Clock () and Output Enable () is common to all flip-flops. The SN54/ LS3 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families. Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered -Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp iodes Limit High Speed Termination Effects PIN NAMES LOAING (Note a) HIGH LOW 0 7 O0 O7 ata Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH going edge) Input Output Enable (Active LOW) Input Outputs (Note b) 65 () U.L. 0. U.L. 0. U.L. 0. U.L. 0. U.L. 5 (7.5) U.L. NOTES: a) TTL Units Load (U.L.) = 40 µa HIGH/.6 ma LOW. b) The Output LOW drive factor is 7.5 U.L. for Military (54) and U.L. for Commercial () Temperature Ranges. The Output HIGH drive factor is U.L. for Military (54) and 65 U.L. for Commercial () Temperature Ranges. SN54/ SN54/LS3 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL -TYPE FLIP-FLOP WITH 3-STATE OUTPUT LOW POWER SCHOTTKY ORERING INFORMATION SN54LSXXXJ Ceramic SNLSXXXN Plastic SNLSXXXW SOIC J SUFFIX CERAMIC CASE N SUFFIX PLASTIC CASE W SUFFIX SOIC CASE SN54/ O7 7 6 O6 O CONNECTION IAGRAM IP (TOP VIEW) O4 9 SN54/ LS3 O7 7 6 O6 O O O0 0 O O O3 GN NOTE: The Flatpak version has the same pinouts (Connection iagram) as the ual In-Line Package O0 0 O O O3 GN FAST AN LS TTL ATA 5-

2 SN54/ SN54/LS3 TRUTH TAB LS3 n On H H L H L H L L X L L 0 X X H Z* H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance n On H L H L L L X X H Z* * Note: Contents of flip-flops unaffected by the state of the Output Enable input (). LOGIC IAGRAMS SN54LS/ LATCH ENAB G G 2 G 3 G 3 4 G 4 5 G G G = PIN GN = PIN 0 = PIN NUMBERS O0 O O2 O3 O4 O5 O6 O SN54LS/ LS O0 O O2 O3 O4 O5 O6 O GUARANTEE OPERATING RANGES Symbol Parameter Min Typ Max Unit Supply Voltage V TA Operating Ambient Temperature Range C IOH Output Current High ma IOL Output Current Low ma FAST AN LS TTL ATA 5-2

3 SN54/ SN54/LS3 C CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Min Typ Max Unit Test Conditio VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage V Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp iode Voltage V = MIN, IIN = 8 ma VOH Output HIGH Voltage Output LOW Voltage V = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table 54, V IOL = ma = MIN, VIN =VIL or VIH 0.35 IOL = 24 ma per Truth Table IOZH Output Off Current HIGH µa = MAX, = 2.7 V IOZL Output Off Current LOW µa = MAX, = 0.4 V IIH Input HIGH Current µa = MAX, VIN = 2.7 V 0. ma = MAX, VIN = 7.0 V IIL Input LOW Current 0.4 ma = MAX, VIN = 0.4 V IOS Short Circuit Current (Note ) ma = MAX ICC Power Supply Current 40 ma = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CHARACTERISTICS (TA = C, = 5.0 V) Symbol Parameter Min Typ Max Min Typ Max Unit Test Conditio LS3 fmax Maximum Clock Frequency MHz Propagation elay, ata to Output Clock or Enable to Output CL =45pF pf, RL = 667 Ω Output Enable Time Output isable Time 5 5 CL = 5.0 pf AC SETUP REUIREMENTS (TA = C, = 5.0 V) LS3 Symbol Parameter Min Max Min Max Unit tw Clock Pulse Width 5 5 ts Setup Time 5.0 th Hold Time 0 EFINITION OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to traition from HIGH-to-LOW in order to be recognized and traferred to the outputs. HOL TIME (th) is defined as the minimum time following the traition from HIGH-to-LOW that the logic level must be maintained at the input in order to eure continued recognition. FAST AN LS TTL ATA 5-3

4 SN54/ AC WAVEFORMS tw tw.3 V ts th n OUTPUT Figure.3 V.3 V.3 V.3 V VOH.3 V.3 V.3 V.3 V Figure 2 Figure 3 AC LOA CIRCUIT TO OUTPUT UNER TEST SW RL SWITCH POSITIONS SYMBOL SW SW2 Open Closed Closed Open Closed Closed Closed Closed 5.0 kω CL* SW2 * Includes Jig and Probe Capacitance. Figure 4 FAST AN LS TTL ATA 5-4

5 SN54/LS3 AC WAVEFORMS twh twl.3 V.3 V.3 V.3 V.3 V ts th n OUTPUT.3 V.3 V.3 V.3 V.3 V Figure 6 Figure 5.3 V.3 V.3 V VOH.3 V Figure 7 AC LOA CIRCUIT RL SWITCH POSITIONS SYMBOL SW SW2 SW Open Closed Closed Open TO OUTPUT UNER TEST Closed Closed Closed Closed 5.0 kω CL* SW2 * Includes Jig and Probe Capacitance. Figure 8 FAST AN LS TTL ATA 5-5