Overview. Ad-Hoc DFT Methods. Definition. Ad-Hoc DFT Methods. Ad-Hoc DFT Methods. VLSI Design Verification and Testing

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1 VLSI esign Verificaion and Tesing esign for Tesabiliy (FT) - 1 Mohammad Tehranipoor Elecrical and Compuer Engineering Universiy of Connecicu Overview efiniion Ad-hoc mehods Scan design esign rules Scan regiser Scan flip-flops Scan es sequences Overhead Scan design sysem Summary 27 Ocober Ocober 29 2 efiniion Ad-Hoc FT Mehods esign for esabiliy (FT) refers o hose design echniques ha make es generaion and es applicaion cos-effecive. FT mehods for digial circuis: Ad-hoc mehods Srucured mehods: Scan Parial Scan Buil-In Self-Tes (BIST) Boundary Scan Good design pracices learned hrough experience are used as guidelines: on -s and o-s Avoid asynchronous (unclocked) feedback. Avoid delay dependan. Avoid parallel drivers. Avoid monosables and self-reseing. Avoid gaed clocks. Avoid redundan gaes. Avoid high fanin fanou combinaions. 27 Ocober Ocober 29 4 Ad-Hoc FT Mehods Good design pracices learn hrough experience are used as guidelines: on -s and o-s (cond.) Make flip-flops iniializable. Separae digial and analog circuis. Provide es conrol for difficul-o-conrol signals. Buses can be useful and make life easier. Limi gae fanin and fanou. Consider ATE requiremens (risaes, ec.) esign Reviews Manual analysis Ad-Hoc FT Mehods Conduced by expers Programmed analysis Using design audiing ools Programmed enforcemen Mus use cerain design pracices and cell ypes. Objecive: Adherence o design guidelines and esabiliy improvemen echniques wih lile impac on performance and area. 27 Ocober Ocober

2 Ad-Hoc FT Mehods isadvanages of ad-hoc FT mehods: Expers and ools no always available Tes generaion is ofen manual wih no guaranee of high faul coverage Funcional paerns esign ieraions may be necessary Very ime consuming Objecives Scan esign Simple read/wrie access o all or subse of sorage elemens in a design. irec conrol of sorage elemens o an arbirary value ( or 1). irec observaion of he sae of sorage elemens and hence he inernal sae of he circui. Key is Enhanced conrollabiliy and observabiliy. 27 Ocober Ocober 29 8 Scan esign Scan esign Circui-Under-Tes (CUT) Scan-ou (SO) Circui is designed using pre-specified design rules. Tes srucure (hardware) is added o he verified design: Add one (or more) es conrol () primary inpu. Primary Inpus Primary Oupus Replace flip-flops by scan flip-flops and connec o form one or more shif regisers in he es mode. Make inpu/oupu of each scan shif regiser conrollable/observable from /. Scan-in (SI) Scan Flip-Flop Use combinaional ATPG o obain ess for all esable fauls in he combinaional. Add shif regiser ess and conver ATPG ess ino scan sequences for use in manufacuring es. 27 Ocober Ocober 29 1 Scan esign Rules Correcing a Rule Violaion All clocks mus be conrolled from s. Use only clocked -ype flip-flops for all sae variables. A leas one pin mus be available for es; more pins, if available, can be used. All clocks mus be conrolled from s. Clocks mus no feed daa inpus of flip-flops. 2 1 FF 2 1 FF 27 Ocober Ocober

3 Correcing a Rule Violaion Scan Flip-Flop (Maser-Slave) Maser lach Slave lach SI 1 S Logic overhead MUX SE flip-flop Flip-Flop Scan Flip-Flop Maser open Slave open Normal mode, seleced Scan mode, S seleced 27 Ocober Ocober Level-Sensiive Scan-esign Lach (LSS) Adding Scan Srucure Maser lach Slave lach M S S T Logic overhead Level Sensiive raher han edge sensiive M T M T S flip-flop Normal mode Scan mode or T Scan Pah Also called Scan Chain No shown: or M/S feed all s (scan Flipflops). 27 Ocober Ocober Tes Vecors Tes Vecors I1 I2 on care or random bis S1 S2 I1 I2 O1 O2 1 1 O1 O2 Presen sae S1 S2 N1 N2 Nex sae N1 N2 Sequence lengh = (n sff + 1) n comb + n sff clock periods n comb = number of combinaional vecors n sff = number of scan flip-flops 27 Ocober Ocober

4 Tesing Scan Regiser Scan regiser mus be esed prior o applicaion of scan es sequences. A shif sequence of lengh n sff +4 in scan mode (=) produces, 1, 11 and 1 ransiions in all flip-flops and observes he resul a oupu. Toal scan es lengh: ((n sff + 1) n comb + n sff ) + (n sff + 4) clock periods. (n comb + 2) n sff + n comb + 4 clock periods. Example: 2, scan flip-flops, 5 comb. vecors, oal scan es lengh ~ 1 6 clocks. Muliple scan regisers reduce es lengh. Muliple Scan Regisers Scan flip-flops can be disribued among any number of shif regisers, each having a separae scanin and scanou pin. Tes sequence lengh is deermined by he longes scan shif regiser. Jus one es conrol () pin is essenial. / M U X / 27 Ocober Ocober 29 2 Muliple Scan Regisers Scan flip-flops can be disribued among any number of shif regisers, each having a separae scanin and scanou pin. SI1 SI2 SI3 Scan Chain 1 Scan Chain 2 Scan Chain 3 SO1 SO2 SO3 Scan Overhead IO pins: One pin necessary. Area overhead: Gae overhead = [4 n sff /(n g +1n ff )] x 1%, where n g = comb. gaes; n ff = flip-flops; Example n g = 1k gaes, n ff = 2k flip-flops, overhead = 6.7%. More accurae esimae mus consider scan wiring and layou area. Performance overhead: Muliplexer delay added in combinaional pah; approx. wo gae-delays. Flip-flop oupu loading due o one addiional fanou; approx. 5-6%. 27 Ocober Ocober Hierarchical Scan Opimum Scan Layou Scan flip-flops are chained wihin subneworks before chaining subneworks. Advanages: Auomaic scan inserion in nelis Circui hierarchy preserved helps in debugging and design changes isadvanage: Non-opimum chip layou. IO pad Flipflop cell X cell Y Y X Scanin 1 4 Scanou Scanin 1 3 Scanou SCAN OUT 2 3 Hierarchical nelis 4 2 Fla layou Rouing channels Inerconnecs Acive areas: XY and X Y 27 Ocober Ocober

5 Scan Area Overhead Linear dimensions of acive area: X = (C + S) / r X = (C + S + αs) / r Y = Y + ry = Y + Y(1--β) / T Area overhead X Y --XY = x 1% XY 1--β = [(1+αs)( ) 1] x 1% T 1--β = (αs ) x 1% T y = rack dimension, wire widh+separaion C = oal comb. cell widh S = oal non-scan FF cell widh s = fracional FF cell area = S/(C+S) α = cell widh fracional increase r = number of cell rows or rouing channels β = rouing fracion in acive area T = cell heigh in rack dimension y 27 Ocober Example: Scan Layou 2,-gae CMOS chip Fracional area under flip-flop cells, s =.478 Scan flip-flop () cell widh increase, α =.25 Rouing area fracion, β =.471 Cell heigh in rouing racks, T = 1 Calculaed overhead = 17.24% Acual measured daa and performance: Scan implemenaion Area overhead Normalized clock rae None. 1. Hierarchical 16.93%.87 Opimum layou 11.9% Ocober ATPG Example: S5378 Auomaed Scan esign Number of combinaional gaes Number of non-scan flip-flops (1 gaes each) Number of scan flip-flops (14 gaes each) Gae overhead Number of fauls / for ATPG Faul coverage Faul efficiency CPU ime on SUN Ulra II, 2MHz processor Number of ATPG vecors Scan sequence lengh Sequenial ATPG Original 2, % 4,63 35/49 7.% 7.9% 5,533 s Full-scan 2, % 4,63 214/ % 1.% 5 s ,662 Rule violaions vecors Scan design rule audis ATPG Scan sequence and es program generaion Tes program Behavior, RTL, and esign and verificaion Gae-level nelis Scan chain order esign and es daa for manufacuring Scan hardware inserion Scan nelis Chip layou: Scanchain opimizaion, iming verificaion Mask daa 27 Ocober Ocober Timing and Power Summary Small delays in scan pah and clock skew can cause race condiion. Large delays in scan pah require slower scan clock. ynamic muliplexers: Skew beween and signals can cause momenary shoring of and S inpus. Random signal aciviy in combinaional circui during scan can cause excessive power dissipaion. Scan is he mos popular FT echnique: Rule-based design Auomaed FT hardware inserion ATPG Advanages: esign auomaion High faul coverage; helpful in diagnosis Hierarchical scan-esable modules are easily combined ino large scan-esable sysems Moderae area (~1%) and speed (~5%) overhead isadvanages: Large es daa volume and long es ime Basically a slow speed (C) es 27 Ocober Ocober