SRDA3.3-6 and SRDA05-6 RailClamp Low Capacitance TVS Diode Array

Transcription

1 Description RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The SR series has been specifically designed to protect sensitive components which are connected to data and transmission lines from overvoltage caused by electrostatic discharge (ESD), electrical fast transients (ET), and lightning. The unique design of the SRDA series devices incorporates surge rated, low capacitance steering diodes and a TS diode in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. The internal TS diode prevents over-voltage on the power line, protecting any downstream components. The low capacitance array configuration allows the user to protect six high-speed data or transmission lines. The low inductance construction minimizes voltage overshoot during high current surges. SRDA3.3-6 and SRDA5-6 RailClamp Low Capacitance TS Diode Array eatures Transient protection for high-speed data lines to IEC (ESD) ±15k (air), ±k (contact) IEC (ET) 4A (5/5ns) IEC (Lightning) 24A (/2µs) Array of surge rated diodes with internal TS diode Protects six I/O lines and power supply line Low capacitance (<15p) for high-speed interfaces Low operating & clamping voltages Solid-state technology Mechanical Characteristics JEDEC SO- package UL 497B listed Molding compound flammability rating: UL 94- Marking : Part number, date code, logo Packaging : Tube or Tape and Reel Applications USB Power & Data Line Protection T1/E1 secondary IC Side Protection Token Ring HDSL, SDSL secondary IC Side Protection ideo Line Protection Microcontroller Input Protection Base stations I 2 C Bus Protection Circuit Diagram Schematic and PIN Configuration I/O 1 1 GND I/O I/O 6 +RE 3 6 I/O 5 I/O I/O 4 S- (Top iew) Revision 1/15/ 1

2 Absolute Maximum Rating Rating Symbol alue Units Peak Pulse Power (t = /2µs) P p k Peak orward (I = 1A, tp=/2µs) P p. 5 5 Watts 1 Lead Soldering Temperature T L 26 ( sec. ) C Operating Temperature T J -55 to +125 C Storage Temperature T STG 55 to C Electrical Characteristics SRDA3.3-6 Parameter Symbol Conditions Minimum Typical Maximum Units Stand-Off WM R. 3 3 Punch-Through Snap-Back PT SB I PT I SB = 2µ A 3. 5 = 5mA 2. Leakage Current I R RWM = 3.3, T=25 C 1 µ A C = 1A, tp = /2µ s 5. 3 C = A, tp = /2µ s C = 25A, tp = /2µ s 15 Peak Pulse Current P t p = /2µ s 25 A I P Junction Capacitance C j Between I/O pins and Ground =, f = 1MHz R Between I/O pins =, f = 1MHz R 15 p 4 p Note: (1) The SRDA3.3-6 is constructed using Semtech s proprietary EPD process technology. See applications section for more information. 2 Semtech Corp. 2

3 Electrical Characteristics (continued) SRDA5-6 Parameter Symbol Conditions Minimum Typical Maximum Units Stand-Off RWM 5 Breakdown B I t = 1mA 6 R Leakage Current I R RWM = 5, T=25 C µ A C = 1A, t = /2µ s p 9. C = A, t = /2µ s p 12 C = 25A, t = /2µ s p 2 Peak Pulse Current I P P t p = /2µ s 25 A Junction Capacitance C j Between I/O pins and Ground =, f = 1MHz R Between I/O pins =, f = 1MHz R 15 p 4 p 2 Semtech Corp. 3

4 Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve Peak Pulse Power - Ppk (kw) Pulse Duration - t p (µs) % of Rated Power or IPP Ambient Temperature - T A ( o C) Pulse Waveform vs. Peak Pulse Current Percent of IPP e -t td = IPP/2 Waveform Parameters: tr = µs td = 2µs Time (µs) - C () SRDA5-6 SRDA3.3-6 Waveform Parameters: tr = µs td = 2µs Peak Pulse Current - (A) ariation of Capacitance vs. orward vs. orward Current % Change in Capacitance R () orward - () Waveform 2 Parameters: tr = µs 1 td = 2µs orward Current - I (A) 2 Semtech Corp. 4

5 Applications Information Device Connection Options for Protection of Six High- Speed Lines The SRDA TS is designed to protect four data lines from transient overvoltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode ) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins 1, 2, 4, 5, 6 and 7. The negative reference is connected at pin. These pins should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference is connected at pins 2 and 3. In the case of the SRDA3.3-6, pins 2 and 3 are connected internally to the cathode of the low voltage TS. It is not recommended that these pins be directly connected to a DC source greater than the snap-back votlage ( SB ) as the device can latch on as described below. EPD TS Characteristics These devices are constructed using Semtech s proprietary EPD technology. By utilizing the EPD technology, the SRDA3.3-6 can effectively operate at 3.3 while maintaining excellent electrical characteristics. Data Line Protection Using Internal TS Diode as Reference EPD TS I Characteristic Curve IPP I SB I PT BRR The EPD TS employs a complex nppn structure in contrast to the pn structure normally found in traditional silicon-avalanche TS diodes. Since the EPD TS devices use a 4-layer structure, they exhibit a slightly different I characteristic curve when compared to conventional devices. During normal operation, the device represents a high-impedance to the circuit up to the device working voltage ( RWM ). During an ESD event, the device will begin to conduct and will enter a low impedance state when the punch through voltage ( PT ) is exceeded. Unlike a conventional device, the low voltage TS will exhibit a slight negative resistance characteristic as it conducts current. This characteristic aids in lowering the clamping voltage of the device, but must be considered in applications where DC voltages are present. When the TS is conducting current, it will exhibit a slight snap-back or negative resistance characteristics due to its structure. This point is defined on the I R RWM SB PT C curve by the snap-back voltage ( SB ) and snap-back current (I SB ). To return to a non-conducting state, the current through the device must fall below the I SB (approximately <5mA) and the voltage must fall below the SB (normally 2. volts for a 3.3 device). If a 3.3 TS is connected to 3.3 DC source, it will never fall below the snap-back voltage of 2. and will therefore stay in a conducting state. I BRR 2 Semtech Corp. 5

6 Applications Information (continued) approximation, the clamping voltage due to the characteristics of the protection diodes is given by: = + C CC PIN = Descriptions - C (for positive duration pulses) (for negative duration pulses) However, for fast rise time transient events, the effects of parasitic inductance must also be considered as shown in igure 2. Therefore, the actual clamping voltage seen by the protected circuit will be: = + + L di /dt (for positive duration pulses) C CC P ESD = - - L di /dt (for negative duration pulses) C G ESD ESD current reaches a peak amplitude of 3A in 1ns for a level 4 ESD contact discharge per IEC Therefore, the voltage overshoot due to 1nH of series inductance is: igure 1 - Rail-To-Rail Protection Topology (irst Approximation) = L di /dt = 1X -9 (3 / 1X -9 ) = 3 P ESD Example: Consider a = 5, a typical of 3 (at 3A) for the CC steering diode and a series trace inductance of nh. The clamping voltage seen by the protected IC for a positive k (3A) ESD pulse will be: = (nh X 3/nH) = 335 C This does not take into account that the ESD current is directed into the supply rail, potentially damaging any components that are attached to that rail. Also note the high of the discrete diode. It is not uncommon for the of discrete diodes to exceed the damage threshold of the protected IC. This is due to the relatively small junction area of typical discrete components. It is also possible that the power dissipation capability of the discrete diode will be exceeded, thus destroying the device. The RailClamp is designed to overcome the inherent disadvantages of using discrete signal diodes for ESD suppression. The RailClamp s integrated TS diode helps to mitigate the effects of parasitic inductance in the power supply connection. During an ESD event, igure 2 - The Effects of Parasitic Inductance When Using Discrete Components to Implement Rail-To-Rail Protection igure 3 - Rail-To-Rail Protection Using RailClamp TS Arrays 2 Semtech Corp. 6

7 Applications Information (continued) the current will be directed through the integrated TS diode to ground. The total clamping voltage seen by the protected IC due to this path will be: = + C (RailClamp) TS This is given in the data sheet as the rated clamping voltage of the device. or an SRDA5-6 the typical clamping voltage is <16 at I =3A. The diodes PP internal to the RailClamp are low capacitance, fast switching devices that are rated to handle high transient currents and maintain excellent forward voltage characteristics. determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint. Using the RailClamp does not negate the need for good board layout. All other inductive paths must be considered. The connection between the positive supply and the SRDA and from the ground plane to the SRDA must be kept as short as possible. The path between the SRDA and the protected line must also be minimized. The protected lines should be routed directly to the SRDA. Placement of the SRDA on the PC board is also critical for effective ESD protection. The device should be placed as close as possible to the input connector. The reason for this is twofold. irst, inductance resists change in current flow. If a significant inductance exists between the connector and the TS, the ESD current will be directed elsewhere (lower resistance path) in the system. Second, the effects of radiated emissions and transient coupling can cause upset to other areas of the board even if there is no direct path to the connector. By placing the TS close to the connector it will divert the ESD current immediately and absorb the ESD energy before it can be coupled into nearby traces. (Reference Semtech application note SI99-1 for further information on board layout) Matte Tin Lead inish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of % tin solder with large grains. Since the solder volume on the leads is small compared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be 2 Semtech Corp. 7

8 Outline Drawing - SO- 2X E/2 ccc C 2X N/2 TIPS aaa C SEATING PLANE C N A 1 2 D e D E1 E e/2 B A2 A A1 bxn bbb C A-B D GAGE PLANE.25 H SIDE IEW h L (L1) DETAIL A h c 1 SEE DETAIL A DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A A A b c D E E e.236 BSC.5 BSC 6. BSC 1.27 BSC h L L1 N 1 (.41) - (1.4) - aaa bbb ccc..2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD LASH, PROTRUSIONS OR GATE BURRS. 4. REERENCE JEDEC STD MS-12, ARIATION AA. Land Pattern - SO- X DIMENSIONS DIM INCHES MILLIMETERS C (.25) (5.2) (C) G Z G P X.24.6 Y Y Z P NOTES: 1. THIS LAND PATTERN IS OR REERENCE PURPOSES ONLY. CONSULT YOUR MANUACTURING GROUP TO ENSURE YOUR COMPANY'S MANUACTURING GUIDELINES ARE MET. 2. REERENCE IPC-SM-72A, RLP NO. 3A. 2 Semtech Corp.

9 Ordering Information Part Number Lead inish Qty/Pkg Reel Size SRDA3.3-6.TB SRDA5-6.TB SRDA3.3-6.TBT SRDA5-6.TBT SRDA3.3-6 SRDA5-6 SRDA3.3-6.T SRDA5-6.T SnPb SnPb Pb free Pb free SnPb SnPb Pb free Pb free 5/Reel 7 Inch 5/Reel 7 Inch 5/Reel 7 Inch 5/Reel 7 Inch 95/Tube N/ A 95/Tube N/ A 95/Tube N/ A 95/Tube N/ A Note: Lead-free devices are RoHS/WEEE Compliant Contact Information Semtech Corporation Protection Products Division 2 lynn Road, Camarillo, CA 9312 Phone: (5) AX (5) Semtech Corp. 9